KR20090019128A - Method of manufacturing in a semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve a breakdown voltage by increasing a distance between a contact plug and a gate while decreasing the size of a high voltage transistor. A semiconductor substrate(300) is provided. A gate insulating layer(304) , a first conductive layer(306) and a dielectric layer(308) are formed on the semiconductor substrate. The dielectric film of the contact plug region is etched. A first contact hole is formed to expose the first conductive layer. The second conductive layer(314) is formed on the first conductive layer and the dielectric layer. The second conductive layer is patterned. The first conductive layer exposed through the first contact hole is etched. The remaining dielectric layer and the first conductive layer are patterned. A trench is formed in the semiconductor substrate of the contact plug region. The insulating layer is formed on the semiconductor substrate with the trench. The second contact hole is formed in the insulating layer of an upper part of the trench.

Description

Method of manufacturing in a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing the size of a high voltage transistor.

Since NAND flash memory devices perform program and erase operations using FN tunneling (FN tunneling), higher operating voltages are required than conventional NOR flash memory devices. Since the coupling ratio of the cell decreases gradually due to the characteristics of the highly integrated memory device, a high voltage transistor having a high breakdown voltage (BV) is required. In general, the most important factors that determine breakdown voltage (BV) are the junction and well concentration. The graph is as follows.

1 is a graph illustrating a breakdown voltage (BV) of a high voltage transistor according to a doping concentration.

The intrinsic breakdown voltage (BV) values that can be represented by the concentrations of junctions and wells that may have acceptable leakage current values are 25V to 35V.

As shown in FIG. 1, the main factor determining the breakdown voltage (BV) of a high voltage transistor is factors disposed at the periphery of the contact plug since the leakage current between the junction and the well determines the allowable concentration. A graph of the breakdown voltage BV is shown in FIG. 2.

FIG. 2 is a graph showing the breakdown voltage (BV) of a high voltage transistor with respect to the contact plug and main factors disposed at the periphery of the contact plug.

Curve a shows breakdown voltage (BV) with distance between contact plug and gate, curve b shows breakdown voltage (BV) with distance between field stop implant and end of active region, curve c shows contact plug And breakdown voltage (BV) according to the distance between the end of the active region.

As shown in FIG. 2, in order to maintain a high breakdown voltage (BV), the distance between the contact plug and the gate formed in the high voltage transistor, the distance between the contact plug and the active region, and the distance between the field stop implant and the end of the active region are shown. You should increase it.

Since the breakdown voltage BV of the high voltage transistor is caused by impact ionization, as the distance between the junction end and the contact plug increases, the ratio of impact ionization rapidly decreases and the breakdown voltage BV increases.

Therefore, in order to have a high breakdown voltage (BV), a large high voltage transistor is required, which is a major obstacle to the reduction of the peripheral circuit area of the NAND flash memory device. That is, if the high voltage transistor of the X-decoder cannot be located within one block pitch of the cell, the high voltage transistor of the X-decoder must be placed within the two block pitches of the cell. This means that the area occupied by the high voltage transistor in the X-decoder direction is doubled. This situation also occurs in the page buffer, and the area occupied by the high voltage transistor in the page buffer direction is also doubled unless the high voltage transistor that is responsible for the select line of the bit line falls within the 16 bit line pitch.

Since the program voltage required for the NAND flash memory device is 20V to 26V, the breakdown voltage BV of the high voltage transistor is 24V to 30V. In this case, the length of the high voltage transistor for arranging one high voltage transistor occupies about 3 μm to 4 μm. However, when the block of the cell or the pitch of 16 bit lines becomes smaller, the size of the flash memory device becomes inevitable. Therefore, the size of high voltage transistors is a direct limiting factor in the high integration of NAND flash memory devices.

According to the present invention, the breakdown voltage (BV) can be improved by increasing the distance between the contact plug, the gate and the active region, and simultaneously reducing the high voltage transistor.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention, a semiconductor substrate having a gate insulating film, a first conductive film, and a dielectric film is provided. The dielectric film of the contact plug region is etched to form a first contact hole exposing the first conductive film. A first conductive hole is formed, and a second conductive layer is formed on the first conductive layer and the dielectric layer. The first conductive layer exposed through the first contact hole is etched while the second conductive layer is patterned. A trench is formed in the semiconductor substrate of the contact plug region while patterning the remaining dielectric film and the first conductive film. An insulating film is formed on the semiconductor substrate including the trench. A second contact hole is formed in the insulating film on the trench.

In the above, the thickness of the gate insulating film is different from the contact plug region. In the gate insulating film, the thickness of the gate insulating film of the contact plug region is smaller than the thickness of the remaining regions. The gate insulating film of the contact plug region is formed to a thickness of 50 kPa to 150 kPa. The first contact hole is also formed in the region where the gate is formed.

The width of the first contact hole is determined in consideration of the size of the contact plug and a change situation when an overlay occurs. The depth of the trench is adjusted according to the thickness and etching recipe of the dielectric film, the first conductive film, and the gate insulating film. If the thickness of the first conductive film and the thickness of the dielectric film are formed thicker, the depth of the trench becomes deeper.

If the gate insulating film of the contact plug region is formed to have the same thickness as the gate insulating film of the remaining regions, the semiconductor substrate is not etched while the dielectric film is etched. And forming a source and drain junction region in the semiconductor substrate by performing an ion implantation process after forming the trench.

As described above, the effects of the present invention are as follows.

First, a trench may be formed in a semiconductor substrate using a dielectric film contact hole formed in a region where a contact plug is to be formed, and a contact plug may be formed in the trench to form the contact plug in a three-dimensional structure instead of a flat plate structure.

Second, by forming the contact plug in a three-dimensional structure, the distance between the contact plug and the gate and the distance between the contact plug and the end of the active region are increased as much as possible (that is, by 2 × B) while the high voltage transistor is reduced by 2 × B. The breakdown voltage (BV) can be improved.

Third, NAND flash memory devices that are competitive in price can be manufactured because no additional process is performed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, an isolation region 302 is formed in the semiconductor substrate 300 to define an active region and an isolation region.

Thereafter, a gate insulating layer 304 is formed on the semiconductor substrate 300. At this time, the gate insulating film 304 is formed of an oxide. In the etching process, the gate insulating layer 304 formed in the region where the contact plug is to be subsequently formed is partially etched. At this time, the etched gate insulating film 304 has a thickness of 50 kPa to 150 kPa. Part of the etching of the gate insulating layer 304 formed in the region where the contact plug is to be formed is to partially etch the semiconductor substrate 300 during the etching process for forming the gate.

Referring to FIG. 3B, a first conductive layer 306, a dielectric layer 308, a capping conductive layer 310, and a first photoresist pattern 312 are formed on the gate insulating layer 304. In this case, the first conductive film 306 and the capping conductive film 310 are formed of a polysilicon film, and the dielectric film 308 is formed of an oxide-nitride-oxide (ONO) film. The capping conductive layer 310 is formed to protect the dielectric layer 308 during the subsequent etching process, and the first photoresist pattern 312 is formed to expose a portion of the region where the gate is to be formed and a region where the contact plug is to be formed. do.

Referring to FIG. 3C, the capping conductive layer 310 and the dielectric layer 308 are etched using the first photoresist pattern 312 as an etch mask, and the dielectric layer contact hole is formed in the same region as the gate insulating layer 304. After forming the first photoresist pattern 312 is removed. At this time, the dielectric film contact hole is formed in a portion where a contact plug is to be formed later and a region where a gate is to be formed. The width of the dielectric film contact hole is determined in consideration of the size of the contact plug and fluctuations in case of an overlay.

Next, a second conductive layer 314, a hard mask layer 316, and a second photoresist pattern 318 are formed on the capping conductive layer 310. At this time, the second conductive film 314 is formed of a polysilicon film.

Referring to FIG. 3D, the hard mask layer 316, the second conductive layer 314, and the capping conductive layer 310 are etched using the second photoresist pattern 318 as an etching mask. At this time, since the dielectric film 308 is formed under the capping conductive film 310 during the etching process of the second conductive film 314 and the capping conductive film 310, the etching process is stopped on the dielectric film 308. In the region where the dielectric film contact hole is formed, since the dielectric film 308 is removed, an etching process is performed to the first conductive film 306.

Referring to FIG. 3E, the dielectric layer 308 is etched using the second photoresist pattern 318 as an etch mask. In this case, the gate insulating layer 304 and a part of the semiconductor substrate 300 are etched in the region where the contact plug is to be formed while the dielectric layer 308 is etched by the etching process for forming the gate. The first conductive layer 306 is etched using the second photoresist pattern 318 as an etching mask. In this case, during the etching of the first conductive layer 306 by the etching process for forming the gate, the semiconductor substrate 300 is partially etched to form the trench 320 in the region where the contact plug is to be formed.

Accordingly, the depth B of the trench 320 may be adjusted according to the thickness and etching recipe of the dielectric layer 308, the gate insulating layer 304 formed in the region where the contact plug is to be formed, and the first conductive layer 306. Can be. When the thickness of the first conductive layer 306 and the thickness of the dielectric layer 308 are formed to be thick, the depth B of the trench 320 may be deepened, and the gate insulating layer 304 of the region where the contact plug is to be formed is formed. In the case of forming a thick layer, the semiconductor substrate 300 may be prevented from being etched while the dielectric layer 308 is etched. This may reduce the depth B of the trench 320.

If a mask used in the gate insulating film 304 etching process and the dielectric film contact hole forming process is formed in the region where the contact plug is to be formed, mis-alignment occurs, the contact during the dielectric film 308 etching process The dielectric film 308 outside the region where the plug is formed may be etched.

However, in this case, the thick gate insulating film 304 formed outside the region where the contact plug is formed protects the semiconductor substrate 300 from being etched while the dielectric film 308 and the first conductive film 306 are etched. There is no room for the semiconductor substrate 300 to be etched in the undesired region.

Next, the second photoresist pattern 318 is removed to remove the gate insulating film 304, the first conductive film 306, the dielectric film 308, the capping conductive film 310, the second conductive film 314, and the hard film. A gate 322 having a structure in which the mask film 316 is stacked is formed.

Then, an ion implantation process is performed to form source and drain junction regions 324 in the semiconductor substrate 300 on both sides of the gate 322.

Referring to FIG. 3F, an insulating film 326 is formed on the semiconductor substrate 300 including the gate 322 to fill the trench 320. At this time, the insulating film 326 is formed of an oxide.

Then, the insulating layer 326 formed on the trench 320 is etched by an etching process to form a contact hole in the trench 320, and then a third conductive layer is formed on the insulating layer 326 including the contact hole to fill the contact hole. Form.

Thereafter, a chemical mechanical polishing (CMP) process is performed to expose the insulating layer 326 to form the contact plug 328. As a result, the distance between the gate 322 and the contact plug 328 becomes A + B + C, and the distance between the contact plug 328 and the end of the active region becomes B + D + E.

Accordingly, the high voltage transistor can be reduced by 2 x B, and at the same time, the distance between the gate 322 and the contact plug 328 and the distance between the contact plug 328 and the end of the active region are increased by B, respectively. You can. As a result, the breakdown voltage BV can be improved.

As described above, the trench 320 is formed in the semiconductor substrate 300 using the dielectric film contact hole formed in the region where the contact plug is to be formed, and the contact plug 328 is formed in the trench 320. ) Can be formed into a three-dimensional structure rather than a flat plate structure. This increases the distance between the contact plug 328 and the gate 322 and the distance between the contact plug 328 and the end of the active region to the maximum (that is, by 2 × B) while minimizing the high voltage transistor by 2 × B. The breakdown voltage can be improved. In addition, since no additional process is performed, a NAND flash memory device that is competitive in terms of price can be manufactured.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a graph illustrating a breakdown voltage (BV) of a high voltage transistor according to a doping concentration.

FIG. 2 is a graph showing the breakdown voltage (BV) of a high voltage transistor with respect to the contact plug and main factors disposed at the periphery of the contact plug.

3A to 3F are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

300: semiconductor substrate 302: device isolation film

304: gate insulating film 306: first conductive film

308 dielectric film 310 capping conductive film

312: First Photoresist Pattern 314: Second Conductive Film

316: hard mask film 318: second photoresist pattern

320: trench 322: gate

324 source and drain junction regions 326 insulating film

328: Contact Plug

A + B + C: distance between gate and contact plug

B + D + E: distance between contact plug and end of active area

Claims (10)

Providing a semiconductor substrate having a gate insulating film, a first conductive film and a dielectric film formed thereon; Etching the dielectric layer of the contact plug region to form a first contact hole exposing the first conductive layer; Forming a second conductive layer on the first conductive layer and the dielectric layer, the second conductive layer including the first contact hole; Etching the first conductive layer exposed through the first contact hole while patterning the second conductive layer; Forming a trench in the semiconductor substrate of the contact plug region while patterning the remaining dielectric film and the first conductive film; Forming an insulating film on the semiconductor substrate including the trench; And And forming a second contact hole in the insulating film over the trench. The method of claim 1, The gate insulating layer has a thickness different from that of the contact plug region and the remaining region. The method of claim 1, And the gate insulating layer has a thickness of the gate insulating layer of the contact plug region being smaller than that of the remaining regions. The method of claim 3, And the gate insulating film of the contact plug region is formed to a thickness of 50 kV to 150 kV. The method of claim 1, The first contact hole is formed in the region where the gate is formed. The method of claim 1, The width of the first contact hole is determined in consideration of the variation of the size of the contact plug and when the overlay occurs. The method of claim 1, The depth of the trench is controlled according to the thickness and etch recipe of the dielectric film, the first conductive film and the gate insulating film. The method of claim 1, The thickness of the first conductive film and the thickness of the dielectric film is formed thicker manufacturing method of a semiconductor device deeper the depth of the trench. The method of claim 3, If the gate insulating film of the contact plug region is formed to the same thickness as the gate insulating film of the remaining region, the semiconductor substrate is not etched while the dielectric film is etched. The method of claim 1, After forming the trench And forming a source and a drain junction region in the semiconductor substrate by performing an ion implantation process.

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