KR20040106664A - Method for fabricating NOR flash memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a NOR type flash memory device is provided to reduce a resistance of a source line without increasing the amount of implanted ions by implanting ions into a silicon substrate among plural word line patterns. CONSTITUTION: A plurality of word line patterns are formed to one direction on a silicon substrate(21) including an active region defined by a trench oxide layer. A photoresist pattern is formed to expose a tunnel oxide layer, the trench oxide layer, and the silicon substrate among the word line patterns. A surface height of the active region is reduced by etching the silicon substrate among the word line patterns. The trench oxide layer among the word line patterns is etched. A source line(39) is formed by implanting impurities into the silicon substrate among the word line patterns.

Description

Method for fabricating a quinoa flash memory device {Method for fabricating NOR flash memory device}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a NOR type flash memory device.

Generally, there are various kinds of semiconductor memory devices. Dual RAM (random access memory) memory devices have the characteristic that the stored information is lost when the power supply is interrupted, whereas ROM (read only memory) memory devices retain the stored information even when the power supply is interrupted from the outside. It has the property to remain as it is. Therefore, this ROM type memory device is called a nonvolatile memory device. Among these nonvolatile memory devices, a flash memory device capable of electrically erasing or writing (programming) information is widely used in computers, memory cards, and the like. The flash memory device may be roughly classified into a NOR flash memory device and a NAND flash memory device. Among them, a quinoa flash memory device is widely used due to its integration.

However, in the related art quinoa flash memory device, a word line pattern including a floating gate, an insulating layer, and a control gate is formed, and then a source line is formed. That is, after forming the word line pattern, the field oxide film is etched using the etching selectivity between the silicon substrate and the field oxide film. Subsequently, a source line of the flash memory device is formed through ion implantation into the silicon substrate on which the field oxide film is etched. Such a source line forming method is described in US Pat. Nos. 4,500, 899 and the like.

It is preferable to lower the resistance of the source line of the noah type flash memory device. In particular, an increase in the resistance of the source line causes a body effect of the cell transistor to increase the threshold voltage distribution of the programmed cell, thereby reducing the operating margin of the memory device. In order to reduce the resistance of the source line, when the conventional source line forming method is used, an ion implantation dose for forming the source line may be increased. However, increasing the amount of ion implantation is limited because of the source-drain punchthrough of the cell-transistor.

Accordingly, an object of the present invention is to provide a method of manufacturing a Noah type flash memory device capable of lowering the resistance of a source line without increasing the amount of ion implantation during ion implantation for source line formation.

1A is an equivalent circuit diagram of a unit cell of a quinoa flash memory device according to the present invention.

1B is a layout diagram of a quinoa flash memory device according to the present invention.

2 to 4 are cross-sectional views illustrating a method of manufacturing a quinoa flash memory device according to a first embodiment of the present invention.

5 and 6 are cross-sectional views illustrating a method of manufacturing a quinoa flash memory device according to a second embodiment of the present invention.

In order to achieve the above technical problem, a method of manufacturing a quinoa flash memory device of the present invention forms a plurality of word line patterns in one direction on a silicon substrate in which an active region is defined by a trench oxide film. A photoresist pattern exposing the tunnel oxide layer, the trench oxide layer, and the silicon substrate between the word line patterns formed in one direction is formed. The silicon substrate between the word line patterns is etched to self-align the word line patterns to lower the surface height of the active region of the silicon substrate. The trench oxide layers between the word line patterns are etched. An impurity is implanted into the silicon substrate between the word line patterns to form a source line.

The photoresist pattern may be removed after forming the source line. The photoresist pattern may serve as a mask when etching the silicon substrate, trench oxide etching, and source lines. A hard mask pattern may be further formed on the word line pattern.

The surface height of the active region formed by etching the silicon substrate between the word line patterns may be higher than the bottom height of the trench oxide layer. The source line may be formed to be bent on the bottom and sidewalls of the trench and the silicon substrate.

The surface height of the active region formed by etching the silicon substrate between the word line patterns may be the same as the bottom height of the trench oxide layer. The source line may be formed flat to the same height as the bottom of the trench.

As described above, in the method of manufacturing the quinoa flash memory device of the present invention, since the source height is formed by lowering the surface height of the active region between the word line patterns and then implanting impurities into the silicon substrate between the word line patterns, ion implantation amount is increased. The resistance of the source line can be lowered without increasing.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the size or thickness of films or regions is exaggerated for clarity. In addition, when a film is described as "on" another film or substrate, the film may be directly on top of the other film, and a third other film may be interposed therebetween.

1A is an equivalent circuit diagram of a unit cell of a quinoa flash memory device according to the present invention.

Specifically, a word line (W / L), which is a means for selecting the desired cell transistor, and a bit line (B / L) connected to the drain 13 of the cell transistor. And a source line S / L corresponding to the source of the cell transistor. The word line has a control gate when viewed in a unit cell, and an insulating layer, a floating gate, and a tunnel oxide layer are disposed under the control gate. The floating gate serves to store data. As a result, the word line pattern 11 includes a tunnel oxide film, an insulating film, a floating gate, and a control gate.

1B is a layout diagram of a quinoa flash memory device according to the present invention.

Specifically, in the quinoa flash memory device according to the present invention, a plurality of word lines W / L and word line patterns are formed in a horizontal direction (one direction). A source line S / L is positioned in the horizontal direction between the word lines. The source line S / L is self-aligned to the word lines (word line patterns). The bit line B / L and the common source line CS / L are positioned in the vertical direction perpendicular to the word line W / L. The bit line B / L is connected to the drain of the cell through the contact hole 15, and the common source line is connected to the source line S / L through the contact hole 17.

2 to 4 are cross-sectional views illustrating a method of manufacturing a quinoa flash memory device according to a first embodiment of the present invention. In particular, FIGS. 2A, 3A, and 4A are cross-sectional views taken along the AA ′ direction of FIG. 1B, and FIGS. 2B, 3B, and 4B are cross-sectional views taken along the BB ′ direction of FIG. 1B, and FIGS. 2C, 3C, and 4C. Is a cross-sectional view taken along the direction CC ′ of FIG. 1B.

2A, 2B, and 2C illustrate forming a word line pattern.

2A, 2B, and 2C, a trench oxide film 23 is formed in a trench in the silicon substrate 21 to define the active region 25. Next, a word line pattern including a tunnel oxide film 27, a floating gate 29, an insulating film 31, and a control gate 33 is formed on the silicon substrate 21. The floating gate 29 is formed of a polysilicon layer doped with impurities. The insulating film 31 is formed of an ONO film (oxide film-nitride film-oxide film). The control gate 33 is formed of a polysilicon layer 33a and a metal silicide layer 33b doped with impurities. A hard mask pattern 35 is formed on the word line pattern to easily form the word line pattern. In FIG. 2A, the tunnel oxide layer 27 is exposed between the word line patterns, and in FIG. 2C, the trench oxide layer 23 and the silicon substrate 21 are exposed.

3A, 3B, and 3C illustrate forming a photoresist pattern and etching a silicon substrate.

Referring to FIGS. 3A, 3B, and 3C, a photoresist pattern 37 exposing the tunnel oxide layer 27, the trench oxide layer 25, and the silicon substrate 21 between the word line patterns is formed. Subsequently, the silicon substrate 21 between the word line patterns is etched to self-align the word line patterns, thereby lowering the surface height of the active region 25 of the silicon substrate 21 by "a". That is, the surface height of the active region 25 of the silicon substrate 21 is lowered by "a" but is adjusted higher than the bottom height of the trench oxide layer. When etching the silicon substrate 21, the photoresist pattern 37 may serve as an etching mask. The lowering of the height by etching the silicon substrate between the word line patterns is to lower the resistance of the source line in a subsequent process. In addition, when etching the silicon substrate between the word line patterns, the remaining polysilicon layer of the source line region may be etched due to an etching failure due to abnormal growth of the floating gate polysilicon layer.

4A, 4B, and 4C illustrate etching trench trenches and forming source lines.

Referring to FIGS. 4A, 4B, and 4C, as illustrated in FIG. 4C, the trench oxide layer 23 between the word line patterns is etched. The etching of the trench oxide layer 23 uses an etching selectivity between the silicon substrate 21 and the silicon oxide layer 23. The hard mask pattern 35 protects the silicon silicide layer 33b having low silicon and etch ratio. Subsequently, an ion is implanted into the silicon substrate 21 between the word line patterns to form a source line 39. The source line 39 is formed to be bent on the bottom and sidewalls of the trench and the silicon substrate 21. Since the source line 39 lowers the height of the active region 25 of the silicon substrate 21 in FIGS. 3A and 3C, the resistance is lowered even if the ion implantation amount is not increased during ion implantation. In FIG. 4C, reference numeral 41 denotes the surface of the silicon substrate 21 before lowering the height of the active region 25.

The photoresist pattern 37 serves as a mask when forming the etching of the silicon substrate 21, the trench oxide etching 23, and the source line 39. The photoresist pattern 37 may be removed after the etching step of the silicon substrate 21, or may be removed after the source line 39 is formed.

5 and 6 are cross-sectional views illustrating a method of manufacturing a quinoa flash memory device according to a second embodiment of the present invention. In particular, FIGS. 5A and 6A are cross-sectional views taken along the AA ′ direction of FIG. 1B, FIGS. 5B and 6B are taken along the BB ′ directions of FIG. 1B, and FIGS. 5C and 6C are CC ′ of FIG. 1B. Sectional view along the direction. In Figs. 5 and 6, the same reference numerals as Figs. 2 to 5 denote the same members.

5A, 5B and 5C illustrate forming a photoresist pattern and etching a silicon substrate.

5A, 5B and 5C, a word line pattern is formed in the same manner as shown in FIGS. 2A, 2B and 2C of the first embodiment. Subsequently, a photoresist pattern 37 exposing the tunnel oxide layer 27, the trench oxide layer 25, and the silicon substrate 21 between the word line patterns is formed.

Subsequently, the silicon substrate 21 between the word line patterns is etched to self-align the word line patterns, thereby lowering the surface height of the active region 25 of the silicon substrate 21 by "b". That is, the surface height of the active region 25 of the silicon substrate 21 is lowered by "b", but adjusted to be equal to the bottom height of the trench oxide layer. When etching the silicon substrate 21, the photoresist pattern 37 may serve as an etching mask. The lowering of the height by etching the silicon substrate between the word line patterns is to lower the resistance of the source line in a subsequent process. In addition, when the silicon substrate is etched between the word line patterns, the remaining polysilicon layer of the source line region may be etched due to an etching failure due to abnormal growth of the floating gate polysilicon layer.

6A, 6B, and 6C illustrate etching trench trenches and forming source lines.

6A, 6B, and 6C, the trench oxide layer 23 between the word line patterns is etched as shown in FIG. 6C. Subsequently, an impurity is implanted into the silicon substrate 21 between the word line patterns to form a source line 51. The source line 51 is formed flat to the same height as the bottom of the trench. Since the source line 51 has lowered the height of the active region 25 of the silicon substrate 21 in FIGS. 5A and 5C, the resistance is lowered even when the ion implantation amount is not increased. In Fig. 6C, reference numeral 53 denotes the surface of the silicon substrate 21 before the height of the active region 25 is lowered.

The photoresist pattern 37 serves as a mask when the etching of the silicon substrate 21, the trench oxide etching 23, and the source line 51 are formed. The photoresist pattern 37 may be removed after the etching step of the silicon substrate 21, or may be removed after the source line 51 is formed.

As described above, in the method of manufacturing a Noah type flash memory device of the present invention, the trench oxide layer is etched after lowering the surface height of the active region between the word line patterns. Subsequently, since the source line is formed by implanting impurities into the silicon substrate between the word line patterns, the resistance of the source line can be lowered without increasing the ion implantation amount.

In addition, according to the method of manufacturing a quinoa flash memory device of the present invention, the residual polysilicon film of the source line region caused by an etch failure due to abnormal growth of the floating gate polysilicon film may be etched.

Claims (10)

Forming a plurality of word line patterns in one direction on a silicon substrate having an active region defined by a trench oxide film; Forming a photoresist pattern exposing the tunnel oxide layer, the trench oxide layer, and the silicon substrate between the word line patterns formed in one direction; Etching the silicon substrate between the word line patterns to self-align the word line patterns to lower the surface height of the active region of the silicon substrate; Etching trench oxide layers between the word line patterns; And And implanting impurities into the silicon substrate between the word line patterns to form a source line. The method of claim 1, wherein the photoresist pattern is removed after the source line is formed. The method of claim 1, wherein the photoresist pattern serves as a mask when etching the silicon substrate, forming a trench oxide layer, and forming a source line. The method of claim 1, wherein a hard mask pattern is further formed on the word line pattern. The method of claim 1, wherein a surface height of an active region formed by etching the silicon substrate between the word line patterns is higher than a bottom height of the trench oxide layer. The method of claim 5, wherein the source line is formed to be bent on the bottom and sidewalls of the trench and the silicon substrate. The method of claim 1, wherein a surface height of an active region formed by etching the silicon substrate between the word line patterns is equal to a bottom height of the trench oxide layer. The method of claim 7, wherein the source line is formed to be flush with the bottom of the trench. Forming a plurality of word line patterns in one direction on a silicon substrate having an active region defined by a trench oxide film; Forming a photoresist pattern exposing the tunnel oxide layer, the trench oxide layer, and the silicon substrate between the word line patterns formed in one direction; Etching the silicon substrate between the word line patterns to self-align the word line patterns so that the surface height of the active region of the silicon substrate is higher than or equal to the bottom height of the trench oxide film; Etching trench oxide layers between the word line patterns; And And implanting impurities into the silicon substrate between the word line patterns to form a source line. The method of claim 9, wherein the photoresist pattern is removed after forming a source line.