KR20010054267A - Method of forming a common source line in nand type flash memory - Google Patents

Abstract

PURPOSE: A method for forming a common source line in an NAND type flash memory is provided to form simultaneously a gate layer and a common source line. CONSTITUTION: A gate oxide layer(212), a floating gate electrode layer(214), an interlayer dielectric(216), and a control gate electrode layer(218) are deposited on a semiconductor substrate(210). A groove is formed by etching the control gate electrode layer(218), the interlayer dielectric(216), the floating gate electrode layer(214), and the gate oxide layer(212). N type ions are implanted into the semiconductor substrate(210) of the groove. The groove is filled with the conductive layer. An insulating layer(226) is deposited on the conductive layer. The insulating layer(226), the conductive layer, the control gate electrode layer(218), the interlayer dielectric(216), and the floating gate electrode layer(214) are patterned to expose the gate oxide layer(212).

Description

METHODO OF FORMING A COMMON SOURCE LINE IN NAND TYPE FLASH MEMORY}

The present invention relates to a method of forming a CSL in a NAND type flash memory, and more particularly, to a method of forming a CSL having a height lower than that of a gate line.

Semiconductor memory is largely divided into volatile memory and non volatile memory. Volatile memory is characterized in that the stored information is lost when the supply of electricity is interrupted, it has the advantage of high capacity and high speed. Representative of volatile memory is DRAM (Dynamic Random Access Memory), which is growing remarkably in terms of density and capacity. Currently, the capacity of DRAM is entering the giga bit era. On the contrary, the nonvolatile memory has a feature of maintaining information even when the supply of electricity is interrupted, but has a disadvantage in that high capacity and high speed are relatively difficult. Representative examples of the nonvolatile memory include erasable programmable read only memory (EPROM), electretically EPROM (EEPROM), and flash memory. Flash memory is a memory made to realize the advantages of EPROM and EEPROM at the same time. It uses the principle of EPROM when programming data, and the principle of EEPROM when data is destroyed. Flash memory has a relatively small chip size compared to EPROM and EEPROM, which enables high capacity and the ability to immediately update information on a system.

Flash memory is classified into NOR type and NAND type according to the cell configuration. In the NAND type flash memory configuration, 8 or 16 cells are connected to one string. Each string has a string select line (SSL) connected to a bit line and a ground select line (GSL) connected to a common source line (CSL).

1 is a cross-sectional view showing a problem of CSL formation in a conventional flash memory.

A gate oxide film, a floating gate electrode film, an interlayer insulating film, a control gate electrode film, and a gate mask film 112, 116, 118, 120, and 122 are deposited on the semiconductor substrate 110. Word line and ground select line (GSL) gate patterning is performed through a photo process. At this time, the space between the GSL and the GSL should be reserved for subsequent CSL formation. After the insulating film 126 is deposited on the entire surface of the semiconductor substrate 110, the semiconductor substrate 110 is flattened and etched through a chemical mechanical polishing (CMP) process. Through the photo process, the space between the GSL and the GSL is etched until the semiconductor substrate 110 is exposed to form a groove for the CSL pattern. Polysilicon 128 is deposited on the entire surface of the semiconductor substrate to fill the groove for the CSL pattern. Next, the polysilicon 128 is planarized by chemical mechanical polishing or etch back until the insulating layer 126 is exposed to form a CSL 128 between the GSL and the GSL. However, the CSL formed through such a process step is about 2000 ms higher than the word line and the GSL gate layer, which makes it difficult to form subsequent bit lines. In addition, this structure increases the thickness of the subsequent interlayer insulating film, so that the contact etching having a high step is required when forming a direct contact (DC), thereby making it difficult to align. As a result, a short occurs between the bit line and the CSL.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CSL formation method in a NAND type flash memory which simultaneously forms CSL when forming a gate layer.

1 is a cross-sectional view showing a problem of CSL formation in a conventional NAND type flash memory; And

2A through 2D are cross-sectional views sequentially illustrating a CSL forming method in a NAND type flash memory according to the present invention.

* Explanation of symbols for the main parts of the drawings

210: semiconductor substrate 212: gate oxide film

214: floating gate electrode film 216: interlayer insulating film

218: control gate electrode film 220: groove

222 conductive film 224 metal film

226: gate mask film

According to the present invention for achieving the above object, in the NAND type flash memory, the CSL forming method deposits a gate oxide film, a floating gate electrode film, an interlayer insulating film, and a control gate electrode film on a semiconductor substrate in sequence. Through the photo process, the control gate electrode film, the interlayer insulating film, the floating gate electrode film, and the gate oxide film are sequentially etched to form grooves. A conductive film is deposited on the entire surface of the substrate to fill the grooves. An insulating film is deposited on the conductive film. The insulating film, the conductive film, the control gate electrode film, the interlayer insulating film, and the floating gate electrode film are gate patterned to expose the gate oxide film through a photolithography process.

In a preferred embodiment of the method, the method further includes the step of implanting N-type ions after forming the grooves.

(Example)

An embodiment of the present invention will be described in detail with reference to FIGS. 2A-2D.

In the novel NAND-type flash memory of the present invention, the CSL formation method forms a CSL pattern after the gate electrode layer is formed, thereby gate patterning, thereby forming CSL at the same time.

2A through 2D are cross-sectional views sequentially illustrating a CSL forming method in a NAND type flash memory according to an embodiment of the present invention.

Referring to FIG. 2A, a gate oxide film 212 is deposited on the semiconductor substrate 210. A floating gate electrode film 214 is deposited on the gate oxide film 212. The floating gate electrode layer 214 may be made of polysilicon or doped polysilicon. An interlayer insulating layer 216 is deposited on the floating gate electrode layer 214. The interlayer insulating layer 216 preferably has an oxide-nitride-oxide (ONO) structure. A control gate electrode film 218 is deposited on the interlayer insulating film 216. The control gate electrode film 218 is formed of polysilicon or doped polysilicon. The control gate electrode film 218 may be formed only to a thickness sufficient to serve as a mask in a subsequent patterning process. The control gate electrode film, the interlayer insulating film, the floating gate electrode film, and the gate oxide films 218, 216, 214, and 212 are etched by setting a predetermined region through a photo process to form the groove 220. Next, N-type ions are implanted into the grooves 220 through an ion implantation process. When ion implantation is performed after the subsequent gate patterning, the gate pattern may overlap with the CSL so that a conductive path may not be formed between the CSL and the GSL. However, if the N-type ions are implanted into the semiconductor substrate 220 at the bottom after the groove 220 is formed, it is diffused by a subsequent thermal process to form a conductive path between the subsequent CSL and the GSL, thereby lowering the resistance. .

Referring to FIG. 2B, a conductive film 222 is deposited on the entire surface of the semiconductor substrate to fill the groove 220. The conductive layer 222 may be polysilicon or doped polysilicon. Accordingly, the conductive film 222 filled in the groove 220 becomes the electrode 222a of the CSL, and the conductive film 222 deposited on the control gate electrode film 218 is the control gate electrode film 218. The same function as the control gate.

Referring to FIG. 2C, the conductive layer 222 is flattened and etched to a predetermined thickness. A metal film 224 is deposited on the conductive film 222. When the metal film 224 is formed of tungsten silicide or tungsten, tungsten silicide is preferably used. A gate mask layer 226 is deposited on the metal layer 224. The gate mask layer 226 is formed by selecting one of a Plasma Enhanced (PE) oxide film, an Undoped Silicate Glass (USG) film, and a silicon nitride film.

Referring to FIG. 2D, the words 226, 224, 222, 218, 216, and 214 are gate patterned on the gate oxide layer 212 until the gate oxide layer 212 is exposed through a photolithography process. And CSL is formed. In this case, as shown in FIG. 2D, when the gate patterning is performed, the region in which the CSL electrode 222a is formed is patterned to be included in one gate pattern, so that the CSL electrode 222a overlaps the gate pattern, thereby forming a CSL pattern. .

As such, the CSL pattern is set to the same height as the surrounding gate pattern, so that the thickness of the subsequent interlayer insulating layer can be reduced, thereby preventing contact area not-open problems and misalignment problems generated during contact etching during subsequent DC formation. can do. In addition, it is possible to prevent a short circuit between a subsequent bit line and the gate pattern.

The present invention has the effect of solving the difficulty of the subsequent process by forming the height of the CSL the same as the gate layer.

In addition, since the present invention forms the CSL at the same time as the gate layer is formed, there is an effect that can simplify the process.

Claims (3)

Depositing a gate oxide film, a floating gate electrode film, an interlayer insulating film, and a control gate electrode film 212, 214, 216, and 218 on the semiconductor substrate 210 in sequence; The groove 222 is formed by sequentially etching the control gate electrode film, the interlayer insulating film, the floating gate electrode film, and the gate oxide films 218, 216, 214, and 212 until the semiconductor substrate 210 is exposed through a photolithography process. Doing; Implanting N-type ions into the semiconductor substrate 210 at the bottom of the groove 222 through an ion implantation process; Depositing a conductive film (222) on the entire surface of the substrate (210) to fill the groove (220); Depositing an insulating film 226 on the conductive film 222; And Gate patterning the insulating film, the conductive film, the control gate electrode film, the interlayer insulating film, and the floating gate electrode film 226, 222, 218, 216, and 214 to expose the gate oxide film 212 through a photolithography process. Common source line formation method in NAND flash memory. The method of claim 1, A method of forming a common source line in a NAND flash memory for patterning a region in which the groove 220 is formed in a gate pattern during the gate patterning step. The method of claim 1, And forming a metal film (224) between the conductive film (222) and the insulating film (226).