US5510282A - Method for manufacturing a nonvolatile semiconductor memory device using a residual sidewall film - Google Patents
Method for manufacturing a nonvolatile semiconductor memory device using a residual sidewall film Download PDFInfo
- Publication number
- US5510282A US5510282A US08/318,390 US31839094A US5510282A US 5510282 A US5510282 A US 5510282A US 31839094 A US31839094 A US 31839094A US 5510282 A US5510282 A US 5510282A
- Authority
- US
- United States
- Prior art keywords
- gate
- films
- insulating films
- insulating film
- gate structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Definitions
- the present invention relates to a method for manufacturing a nonvolatile semiconductor memory device and, more particularly, to a method for manufacturing an electrically erasable programmable read only memory (EEPROM).
- EEPROM electrically erasable programmable read only memory
- Nonvolatile semiconductor memory devices retain data written thereto even when their power is turned off. Active research has been conducted to develop nonvolatile semiconductor memory devices.
- FIG. 1 is a schematic plan view showing a memory device having self aligned sources disclosed in the publication as mentioned above.
- FIGS. 7A, 7B and 7C are cross-sectional views of the semiconductor memory device of FIG. 1 for showing consecutive steps of a manufacturing process of the prior art.
- FIGS. 2A-7A show cross-sections taken along line A--A' in FIG. 1
- FIGS. 2B-7B show cross-sections taken along line B--B'
- FIGS. 2C-7C show cross-sections taken along line C--C' in FIG. 1.
- first insulating films or field oxide films 2 each having a thickness of 3000-8000 angstroms are formed on a P-type silicon substrate 1 by using a known LOCOS technique, the field oxide films extending in a first direction (horizontal direction as viewed in FIG. 1) and in parallel to each other. Subsequently, as shown in FIGS. 2A, 2B and 2C (hereinafter also referred to as FIGS. 2A-2C), first insulating films or field oxide films 2 each having a thickness of 3000-8000 angstroms are formed on a P-type silicon substrate 1 by using a known LOCOS technique, the field oxide films extending in a first direction (horizontal direction as viewed in FIG. 1) and in parallel to each other. Subsequently, as shown in FIGS.
- second insulating films or first gate insulating films 4 are formed between two of the field oxide films, following which a first polysilicon layer having a thickness of 1000-3000 angstroms is formed on the entire surface by chemical vapor deposition (CVD). Then, patterning is performed on the first polysilicon layer to form floating gate layers 3 each extending in the first direction on the first gate insulating film 4 and the edge portions of the field oxide films 2 (FIGS. 3A-3C).
- a third insulating film is formed on the entire surface as an ONO-laminate having a thickness of 100-300 angstroms and three layers including a silicon oxide film, a silicon nitride film, and another silicon oxide film.
- a second polysilicon layer having a thickness of 2000-4000 angstroms is formed by CVD on the entire surface. Then, by using a known anisotropic etching technique, patterning is performed on the second polysilicon layer to make control gates 5 extending in a second direction perpendicular to the first direction. Patterning is also performed on the second gate insulating film 6 and floating gate layers 3 using each of the control gates 5 as a mask to obtain gate structures as shown in FIGS. 4A-4C.
- a photoresist pattern 7 is formed, in which openings 13 thereof have edges on the central portions of the control gates 5, as shown in FIGS. 5A-5C.
- anisotropic etching is performed on the field oxide films 2 to selectively expose portions of the semiconductor substrate 1 in which source regions are to be formed.
- N-type impurity ions such as phosphorus (P) ions are implanted to the exposed portions of the semiconductor substrate 1 to form source regions extending in the second direction, i.e. vertical direction as viewed in FIG. 1.
- N-type impurity ions such as arsenic (As) ions are selectively introduced to the substrate regions including the source regions 8b and other portions opposite to the source regions 8b with respect to the gate structures, thereby obtaining N-type source regions 8b and N-type drain regions 8a, as shown in FIGS. 6A-6C.
- the source regions 8b extend in the vertical direction as viewed in FIG. 1 while the drain regions 8a are separated from each other by the field oxide films 2 in the vertical direction as viewed in FIG. 1.
- contact holes 10 are formed in the interlayer insulating films 11 and the first gate insulating film 4 for exposing portions of the drain regions 8a by using a known photolithographic technique. Then, an aluminum layer is deposited on the entire surface, and patterning is performed thereon to obtain aluminum interconnection 9.
- an interlayer insulating film 11 made of a silicon oxide film containing, for example, boron (B) or phosphorus (P)
- contact holes 10 are formed in the interlayer insulating films 11 and the first gate insulating film 4 for exposing portions of the drain regions 8a by using a known photolithographic technique.
- an aluminum layer is deposited on the entire surface, and patterning is performed thereon to obtain aluminum interconnection 9.
- the conventional method for manufacturing a nonvolatile semiconductor memory device as described above is employed primarily for manufacturing flash memories in which erasing of data is performed from the source regions by applying a high voltage, e.g. 12 volts, to the source regions. Since the method allows source regions to be formed in a self aligned structure, it is not necessary to provide an alignment margin between the source regions and the gate electrode layers. Accordingly, the conventional method is suited for a finer patterning of memory cells in flash memories.
- nonvolatile semiconductor memory devices have more reliable characteristics and be manufactured in a higher integration and in a higher yield.
- EEPROM nonvolatile semiconductor memory device
- an improved method for manufacturing a semiconductor memory device having floating gates and control gates includes steps of: forming a plurality of first insulating films extending in a first direction and in parallel to each other on a semiconductor substrate; forming a plurality of second insulating films each extending on the semiconductor substrate between adjacent two of the first insulating films; forming on each of the second insulating films a plurality of gate structures each including consecutive layers of a floating gate, a third insulating film and a control gate; forming a fourth insulating film at least on the gate structures; selectively dry-etching the fourth insulating film to leave residual side wall films at a first side of each of the gate structures; after said dry-etching, selectively introducing impurity ions of a second conductivity type to first regions of the semiconductor substrate adjacent to the first side of each of the gate structures; and selectively introducing impurity ions to second regions of the semiconductor substrate adjacent to a second side of each of the gate structures opposite to
- the fourth insulating film is etched to form residual side walls for the gate structure thereby protecting the gate structure, especially first gate insulating film thereof, from a plasma damage during dry-etching and ion-implantation, resistance for breakdown due to a high voltage can be improved. Moreover, the residual side walls produce an LDD structure in the source regions, so that reliability of the memory device can be further improved.
- FIG. 1 is a schematic plan view showing a nonvolatile semiconductor memory device fabricated by a conventional method
- FIGS. 2A, 2B and 2C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a first step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIGS. 3A, 3B and 3C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a second step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIGS. 4A, 4B and 4C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a third step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIGS. 5A, 5B and 5C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a fourth step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIGS. 6A, 6B and 6C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a fifth step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIGS. 7A, 7B and 7C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 1, respectively, for showing a final step in manufacturing the nonvolatile semiconductor memory device of FIG. 1;
- FIG. 8 is a graph showing the dependency of cumulative defective rates (%) of memory devices on a count of repetition of rewriting, for comparing nonvolatile semiconductor memory devices obtained by a conventional manufacturing method and by a manufacturing method of an embodiment of the present invention
- FIG. 9 is a schematic plan view showing a semiconductor memory device manufactured by a method according to a first embodiment of the present invention.
- FIGS. 10A, 10B and 10C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 9, respectively, for showing a first step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 11A, 11B and 11C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a second step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 12A, 12B and 12C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a third step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 13A, 13B and 13C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a fourth step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 14A, 14B and 14C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a fifth step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 15A, 15B and 15C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a sixth step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIGS. 16A, 16B and 16C are cross-sectional views, taken along lines A--A' B--B' and C--C' in FIG. 9, respectively, for showing a final step in manufacturing the nonvolatile semiconductor memory device of FIG. 9;
- FIG. 17 is a schematic plan view showing a semiconductor memory device manufactured by a method according to a second embodiment of the present invention.
- FIGS. 18A, 18B and 18C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a first step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 19A, 19B and 19C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a second step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 20A, 20B and 20C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a third step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 21A, 21B and 21C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a fourth step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 22A, 22B and 22C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a fifth step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 23A, 23B and 23C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a sixth step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 24A, 24B and 24C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a seventh step in manufacturing the nonvolatile semiconductor memory device of FIG. 17;
- FIGS. 25A, 25B and 25C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing a final step in manufacturing the nonvolatile semiconductor memory device of FIG. 17.
- first gate insulating film 4 in order to make a thinner oxide film in a flash memory for further scaling up thereof, it is desirable to make a first gate insulating film 4 as thin as about 100 angstroms or less.
- the thin first gate insulating film 4 may break-down during applying a high voltage to the source regions for erasing of data, resulting from a damage by exposure to plasma ions during anisotropic etching for forming source regions. This decreases the maximum count of rewriting for the flash memories (hereinafter referred to as "rewritable count").
- FIG. 8 exemplarily shows relationship between the count of repeated rewriting operations for memory cells and the cumulative defective rate (%) observed in semiconductor memory devices manufactured by the conventional method and by a method of the present invention.
- the rewritable count does not exceed even a 10 2 order, resulting from a poor characteristic due to a plasma damage.
- the anisotropic ion-etching degrades electric characteristics of a memory cell.
- variations in the impurity concentration in a source regions affects erasing speed and writing speed of the memory cell, producing variations in electric characteristics of the semiconductor memory devices. Such variations in characteristics decreases the yield of semiconductor memory devices.
- FIG. 9 shows a semiconductor memory device manufactured by a method according to a first embodiment of the present invention
- FIGS. 10A-10C through FIGS. 16A-16C show consecutive steps for the method according to the first embodiment.
- a plurality of thick field oxide films (first insulating films) 2 each having a thickness of 3000-8000 angstroms are formed on a P-type silicon substrate 1 by using a LOCOS technique.
- the field oxide films 2 extend in a first direction, i.e., the horizontal direction as viewed in FIG. 9 and in parallel to each other.
- first gate insulating films (second insulating films) 4 are formed on the semiconductor substrate 1 between two of the field oxide films 2 as thermal oxide films having a thickness of 100-200 angstroms.
- first polysilicon layer having a thickness of 1000-3000 angstroms is formed by chemical vapor deposition (CVD) on the entire surface, then selectively removed from central portions of the field oxide films 2 by patterning to form floating gate layers 3 extending in a fist direction and in parallel to each other.
- a second polysilicon layer having a thickness of 2000-4000 angstroms is deposited by CVD on tile entire surface of the third insulating film.
- patterning is performed on the second polysilicon layer to form control gates 5 extending in a second direction perpendicular to the first direction.
- Patterning is also performed on the third insulating film and the floating gate layers 3 using the gate electrodes as a mask to form second gate insulating films 6 and separate floating gates 3.
- gate structures each including a floating gate 3, a second gate insulating film 6 and control gate 5 is formed on the first gate insulating film 4, as shown in FIGS. 12A-12C.
- the control gate 5 and second gate insulating film 6 extend perpendicularly to the field oxide films 2 over the plurality of gate structures, while the floating gates 3 are separated from each other by the field oxide films 4.
- N-type impurity ions such as arsenic (As) ions are selectively implanted to the semiconductor substrate through first gate insulating films 4 to form N-type drains 8a.
- a fourth insulating film 12 made of silicon oxide is deposited on the entire surface by CVD.
- a photoresist pattern 7 is formed as having openings 13 at areas between two adjacent gate structures where source regions are to be formed.
- the openings 13 have edges on the adjacent two of control gates 5 at central portions thereof as viewed in the first direction.
- anisotropic etching is performed on the field oxide films 2 and the fourth insulating film 12, with the photoresist pattern 7 and the control gates 5 used as a mask, to expose substrate portions or the portions of the first insulating films 4.
- parts of the fourth insulating film 12 and parts of the field oxide films 2 remain as residual side walls 12a and 2a, respectively, along peripheral edge portions of the area where source regions are to be formed.
- N-type impurity ions such as phosphorus (P) ions are introduced to form source regions 8b, as shown in FIGS. 15A-15C.
- an interlayer insulating film 11 made of a silicon oxide containing, for example, boron (B) or phosphorus (P)
- contact holes 10 are formed therein by using a known photolithographic technique.
- aluminum is sputtered to deposit on the entire substrate, and patterning is performed thereon to obtain an aluminum interconnection layer 9 as shown in FIGS. 16A-16C.
- one of side walls of the gate structure adjacent to the sources 8b is protected by the fourth insulating films 12 or residual side walls 12a while anisotropic ion-etching is performed to form a self aligned source, so that plasma damage to the gate structure, especially to the very thin first gate insulating film (tunnel film) 4, is substantially avoided.
- plasma damage to the semiconductor substrate can be reduced by the residual side walls 12a of the insulating films 12, thereby reducing variations and deterioration in electric characteristics of the nonvolatile semiconductor memory device.
- the anisotropic ion-etching is finished, residual side walls 12a and 2a remains along peripheral edge portions of the source regions to be formed.
- the peripheral portions of the source regions adjacent to the gate structures are formed in a lightly doped drain (LDD) structure, since the impurity ions are introduced to the peripheral portions through the residual side walls 12a and 2a.
- LDD lightly doped drain
- FIG. 17 is a schematic plan view showing a semiconductor memory device manufactured by a method according to a second embodiment of the present invention.
- FIGS. 18A-18C to FIGS. 25A-25C are cross-sectional views, taken along lines A--A', B--B' and C--C' in FIG. 17, respectively, for showing consecutive steps in the method of the present embodiment.
- a plurality of thick field oxide films 2 (first insulating films) extending in a first direction and in parallel to each other are formed on a P-type silicon substrate by using a LOCOS technique.
- the field oxide films 2 have a thickness of 3000-8000 angstroms.
- first gate insulating films (second insulating films) 4 having a thickness of 100-200 angstroms, each made of thermal oxide, are formed between adjacent two of the field oxide films 2.
- first polysilicon layer having a thickness of 1000-3000 angstroms is formed by chemical vapor deposition (CVD) on the entire surface.
- patterning is performed thereto to selectively remove the polysilicon layer on the central portions of the field oxide films 2, thereby forming floating gate layers 3 which cover the first gate insulating layers 4 and edge portions of the field oxide films 2 and extending in parallel to each other.
- FIGS. 19A-19C is obtained.
- a third insulating film to be formed as second gate insulating films 6 is deposited in a thickness of 100-300 angstroms on the entire surface, the third insulating film having a three-layers structure including a silicon oxide film, a silicon nitride film and another silicon oxide film.
- second gate insulating films 6 can be formed separately from each other on the respective floating gate layers 3 by oxidation thereof.
- a second polysilicon layer having a thickness of 2000-4000 angstroms is deposited by CVD on the entire surface.
- control gates 5 extending in a second direction perpendicular to the first direction.
- Patterning is also performed on the third insulating film to form second gate insulating layer 6 and separate floating gates 3 both aligned with the control gate 5.
- gate structures each including a control gate 5, a second gate insulating film 6 and a floating gate 3 is formed on the first gate insulating film 4, as shown in FIGS. 20A-20C.
- N-type impurity ions such as arsenic (As) ions are selectively introduced to the silicon substrate 1 to form drain regions 8a.
- a fourth insulating film 12 made of silicon oxide is deposited by CVD on the entire surface to obtain the structure shown in FIGS. 21A-21C.
- the fourth insulating 12 is removed by anisotropic etching to leave the side wall insulating films 12 at both the side walls of each of the gate structures, as shown in FIGS. 22A-22C.
- a photoresist pattern 7 is formed as having openings 13 at areas between two of the gate structures where source regions are to be formed.
- FIGS. 23A-23C anisotropic etching is performed on the field oxide films 2 and the side wall insulating films 12, with the photoresist pattern 7 and the control gates 5 used as a mask, thereby obtaining the structure shown in FIGS. 23A-23C.
- the side wall insulating films 12 and field oxide films 2 are etched to form residual side walls 12a and 2a, at the peripheral portions of the area where the source regions are to be formed.
- N-type impurity ions such as phosphorus (P) ions are selectively introduced to form source regions, following which N-type impurity ions such as arsenic (As) ions are introduced thereinto.
- N-type source regions 8b are formed, as shown in FIGS. 24A-24C.
- contact holes 10 are formed therein by using a known etching technique to expose central portions of the drain regions 8a.
- An aluminum layer is deposited by CVD and patterning is conducted thereto to form an aluminum interconnection layer 9 and drain electrodes, as shown in FIGS. 25A-25C.
- an additional advantage can be obtained in which, if a side wall structure is employed in a peripheral circuit in the memory device, side wall insulating films for the gate structure in the memory cell can be formed concurrently with the side wall films of the transistors in the peripheral circuit. Accordingly, it is not necessary to employ an independent step for forming the side wall insulating films for memory cells.
- both the drain regions and source regions can be securely formed in an LDD structure.
- the memory device is suited for applications of high voltages, so that a wide use of the memory devices can be obtained.
- nonvolatile semiconductor memory devices can reduce deterioration in the first gate oxide films caused by plasma damage, so that it is possible to improve a rewritable count of the semiconductor memory device.
- nonvolatile semiconductor memory device manufactured according to the method of the present invention improve a rewritable count substantially by 3 digits as compared to that manufactured by the conventional method.
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5-251552 | 1993-01-07 | ||
JP5251552A JP2982580B2 (en) | 1993-10-07 | 1993-10-07 | Manufacturing method of nonvolatile semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US5510282A true US5510282A (en) | 1996-04-23 |
Family
ID=17224530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/318,390 Expired - Lifetime US5510282A (en) | 1993-01-07 | 1994-10-05 | Method for manufacturing a nonvolatile semiconductor memory device using a residual sidewall film |
Country Status (2)
Country | Link |
---|---|
US (1) | US5510282A (en) |
JP (1) | JP2982580B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0893820A2 (en) * | 1997-07-14 | 1999-01-27 | Texas Instruments Incorporated | Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices |
US5966602A (en) * | 1996-09-04 | 1999-10-12 | Oki Electric Industry Co., Ltd. | Nonvolatile semiconductor memory and fabricating method thereof |
US6277723B1 (en) * | 1999-10-14 | 2001-08-21 | Taiwan Semiconductor Manufacturing Company | Plasma damage protection cell using floating N/P/N and P/N/P structure |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100295149B1 (en) * | 1998-03-26 | 2001-07-12 | 윤종용 | Method for fabricating non-volatile memory device using self-aligned source process |
KR100295136B1 (en) * | 1998-04-13 | 2001-09-17 | 윤종용 | Nonvolatile memory device and method for manufacturing the same |
KR100600330B1 (en) * | 1999-06-23 | 2006-07-14 | 주식회사 하이닉스반도체 | Method of forming well pick up in a flash memory cell |
US6794764B1 (en) * | 2003-03-05 | 2004-09-21 | Advanced Micro Devices, Inc. | Charge-trapping memory arrays resistant to damage from contact hole information |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019527A (en) * | 1989-08-11 | 1991-05-28 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed |
US5366913A (en) * | 1991-10-25 | 1994-11-22 | Rohm Co., Ltd. | Method of manufacturing semiconductor device employing oxide sidewalls |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6469054A (en) * | 1987-09-10 | 1989-03-15 | Matsushita Electronics Corp | Manufacture of mis type transistor |
JPH01143358A (en) * | 1987-11-30 | 1989-06-05 | Nec Corp | Manufacture of mos semiconductor integrated circuit device |
JP3100759B2 (en) * | 1992-06-05 | 2000-10-23 | 株式会社東芝 | Manufacturing method of nonvolatile semiconductor memory device |
-
1993
- 1993-10-07 JP JP5251552A patent/JP2982580B2/en not_active Expired - Lifetime
-
1994
- 1994-10-05 US US08/318,390 patent/US5510282A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019527A (en) * | 1989-08-11 | 1991-05-28 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed |
US5366913A (en) * | 1991-10-25 | 1994-11-22 | Rohm Co., Ltd. | Method of manufacturing semiconductor device employing oxide sidewalls |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5966602A (en) * | 1996-09-04 | 1999-10-12 | Oki Electric Industry Co., Ltd. | Nonvolatile semiconductor memory and fabricating method thereof |
DE19708031B4 (en) * | 1996-09-04 | 2008-04-30 | Oki Electric Industry Co., Ltd. | Non-volatile semiconductor memory and method for its production |
EP0893820A2 (en) * | 1997-07-14 | 1999-01-27 | Texas Instruments Incorporated | Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices |
EP0893820A3 (en) * | 1997-07-14 | 2003-10-29 | Texas Instruments Incorporated | Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices |
US6277723B1 (en) * | 1999-10-14 | 2001-08-21 | Taiwan Semiconductor Manufacturing Company | Plasma damage protection cell using floating N/P/N and P/N/P structure |
Also Published As
Publication number | Publication date |
---|---|
JPH07106441A (en) | 1995-04-21 |
JP2982580B2 (en) | 1999-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100474472B1 (en) | Integrated circuit and method of manufacturing thereof | |
US6940120B2 (en) | Non-volatile semiconductor memory device and method of fabricating thereof | |
US20070034929A1 (en) | Flash memory device and method of manufacturing the same | |
US6103574A (en) | Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer | |
US6784039B2 (en) | Method to form self-aligned split gate flash with L-shaped wordline spacers | |
US8952536B2 (en) | Semiconductor device and method of fabrication | |
JP3389112B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
US6441426B1 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
US7439577B2 (en) | Semiconductor memory and method for manufacturing the same | |
US5736765A (en) | EEPROM cell having improved topology and reduced leakage current | |
JP2734433B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
JP2819975B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
US5510282A (en) | Method for manufacturing a nonvolatile semiconductor memory device using a residual sidewall film | |
US7358139B2 (en) | Method of forming a field effect transistor including depositing and removing insulative material effective to expose transistor gate conductive material but not transistor gate semiconductor material | |
US6818505B2 (en) | Non-volatile semiconductor memory device and manufacturing method thereof | |
CN1832134B (en) | Method of forming a gate electrode pattern in semiconductor device | |
US6472259B1 (en) | Method of manufacturing semiconductor device | |
US8552523B2 (en) | Semiconductor device and method for manufacturing | |
US6242773B1 (en) | Self-aligning poly 1 ono dielectric for non-volatile memory | |
US7060627B2 (en) | Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays | |
US6580119B1 (en) | Stacked gate field effect transistor (FET) device | |
US7049195B2 (en) | Methods of fabricating non-volatile memory devices | |
EP0112078A2 (en) | A semiconductor memory element and a method for manufacturing it | |
KR20010054267A (en) | Method of forming a common source line in nand type flash memory | |
KR100279001B1 (en) | Manufacturing Method of Flash Memory Cell |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARA, HIDEKI;REEL/FRAME:007239/0539 Effective date: 19940926 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013798/0626 Effective date: 20021101 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025149/0840 Effective date: 20100401 |