KR20090014016A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20090014016A
KR20090014016A KR1020070078226A KR20070078226A KR20090014016A KR 20090014016 A KR20090014016 A KR 20090014016A KR 1020070078226 A KR1020070078226 A KR 1020070078226A KR 20070078226 A KR20070078226 A KR 20070078226A KR 20090014016 A KR20090014016 A KR 20090014016A
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KR
South Korea
Prior art keywords
film
insulating layer
contact hole
etching
forming
Prior art date
Application number
KR1020070078226A
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Korean (ko)
Inventor
오승철
Original Assignee
주식회사 하이닉스반도체
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Publication date
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Priority to KR1020070078226A priority Critical patent/KR20090014016A/en
Publication of KR20090014016A publication Critical patent/KR20090014016A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Method of manufacturing semiconductor device is provided to increase the character and reliability of the device by improving the resistance of a bit line contact. A first insulating layer(202) and a second insulating layer(204) are successively laminated on a semiconductor substrate(200). The photosensitive pattern is formed on the second insulating layer, and a groove is formed on the second insulating layer by performing a fist etching of the second insulating layer using the photosensitive pattern as the etching mask. A polymer is generated on the side wall of the photosensitive pattern. A contact hole(C) is formed by performing a second etching of a first insulating layer around the groove using the photosensitive pattern including polymer as the etching mask. The Polymer and photosensitive pattern are removed, and a barrier film(210) is formed on the bottom surface and side of the contact hole including groove. The conductive film(212) is formed on the barrier film and the contact hole is filled.

Description

Method of manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can improve the device characteristics and reliability by improving the resistance of the bit line contact.

With the advance of semiconductor technology, the speed and integration of semiconductor devices are progressing rapidly. As a result, there is an increasing demand for miniaturization of patterns and high precision of pattern dimensions, and the storage capacity of charges required for capacitors for storing information is increasing. As the height of the capacitor is gradually increased to satisfy this, the aspect ratio of the contact hole formed after the capacitor process is rapidly increased. Accordingly, various ideas and actual process development researches for improving the buried characteristics when the contact hole is buried are actively conducted. It's going on.

As is well known, a conventional technique for filling the contact hole is a method of depositing tungsten (W) having excellent step coverage. According to the method described above, a barrier film is formed on the semiconductor substrate on which the contact hole is formed by using a Ti film and a TiN film for securing low contact resistance and adhesion to the oxide film, and a contact hole is formed by depositing tungsten on the barrier film. Landfill.

Hereinafter, a method of manufacturing a semiconductor device including a conventional contact hole filling process will be described with reference to FIGS. 1A to 1D.

Referring to FIG. 1A, a first insulating layer 102 and a second insulating layer 104 are sequentially formed on a semiconductor substrate 100 having a contact hole forming region, and then contact holes are formed on the second insulating layer 104. The photosensitive film pattern 106 which exposes an area | region is formed. Here, the first insulating layer 102 is formed of a boro-phospho silicate glass (BPSG) film, and the second insulating layer 104 is formed of a high density plasma (HDP) film.

Referring to FIG. 1B, a portion of the second insulating layer 104 and the first insulating layer 102 exposed by the photoresist pattern 106 is etched to form a contact hole C. Referring to FIG.

Referring to FIG. 1C, after removing the photoresist pattern, the semiconductor substrate 100 on which the contact hole C is formed is pre-cleaned. At this time, during the pre-cleaning, the portion of the first insulating layer 102 made of the BPSG layer is more etched so that the lower portion of the contact hole C is convex.

Referring to FIG. 1D, after the barrier film 108 is formed on the first and second insulating films 102 and 104 including the surface of the contact hole C by using a Ti film or a TiN film, the barrier film 108 may be formed. The tungsten film 110 is formed to fill the contact hole C on the 108 to form a bit line contact.

Subsequently, although not shown, a series of known subsequent processes are sequentially performed to manufacture the semiconductor device.

However, in the above-described conventional technique, when pre-cleaning, the sidewall of the first insulating layer 102 is more etched inward so that the lower portion of the contact hole C has a convex shape, and thus, the barrier layer 108 ) Is deposited without completely filling the lost portion A of the first insulating film 102.

As a result, the resistance of the bit line contact is lowered, so that the yield is reduced in a subsequent probe test process, and device characteristics and reliability are poor.

The present invention provides a method for manufacturing a semiconductor device that can improve the resistance of the bit line contacts.

In addition, the present invention provides a method for manufacturing a semiconductor device that can increase the yield in the subsequent probe test process.

In addition, the present invention provides a method for manufacturing a semiconductor device capable of improving device characteristics and reliability.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first insulating film and a second insulating film sequentially on a semiconductor substrate; Forming a photoresist pattern on the second insulating layer; Forming a groove by first etching the second insulating layer until the first insulating layer is exposed using the photoresist pattern as an etching mask; Generating a polymer on sidewalls of the photoresist pattern; Forming a contact hole by second etching the portion of the first insulating layer on the bottom of the groove by using the photoresist pattern including the polymer as an etching mask; Removing the polymer and the photoresist pattern; Forming a barrier film on the bottom and side surfaces of the contact hole including the groove; And forming a conductive film to fill the contact hole on the barrier film.

Here, the first insulating film is formed of a BPSG film.

The second insulating film is formed of a laminated film of an HTO film and an HDP film.

The polymer is formed to a thickness of 300 to 500 kPa.

The secondary etching is performed by dry etching.

The secondary etching is performed such that the first insulating layer is etched with a slope that becomes narrower toward the bottom of the contact hole.

The contact hole may be formed to have a narrower width in the first insulating film portion than in the second insulating film portion.

The barrier film is formed of any one of a Ti film and a TiN film.

In addition, according to another embodiment of the present invention, a method of manufacturing a semiconductor device includes: sequentially forming a first insulating film and a second insulating film on a semiconductor substrate; Forming a groove by first etching the second insulating layer until the first insulating layer is exposed; Forming a spacer on the second insulating layer on the sidewalls of the groove; Forming a contact hole by second etching the first insulating layer exposed to the bottom surface of the groove until the semiconductor substrate is exposed; Forming a barrier layer on the bottom and side and the spacer of the contact hole including the groove; And forming a conductive film to fill the contact hole on the barrier film.

Here, the first insulating film is formed of a BPSG film.

The second insulating film is formed of a laminated film of an HTO film and an HDP film.

The spacer is formed of a nitride film.

The secondary etching is performed by dry etching.

The barrier film is formed of any one of a Ti film and a TiN film.

The present invention provides a method for manufacturing a semiconductor device by forming a contact hole by etching a first and a second insulating film in two steps. First, after the first etching of the second insulating film using a photosensitive film pattern as an etching mask, the photosensitive film pattern A polymer is formed on the sidewalls of the first insulating layer, and then the second insulating layer is etched using the photoresist pattern including the polymer as an etching mask to form a contact hole.

In this case, during the second etching of the first insulating layer, not only the first insulating layer is etched to have a narrower width than the second insulating layer by the polymer formed on the sidewalls of the photoresist pattern, and the first insulating layer is the contact. A width thereof decreases toward the bottom of the hole to be etched to be inclined so that the barrier layer may be properly deposited on the first and second insulating layers of the contact hole sidewalls. Through this, the present invention can improve the bit line contact resistance, and can improve device characteristics and reliability.

2A to 2G are cross-sectional views for each process for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a first insulating layer 202 and a second insulating layer 204 are sequentially formed on a semiconductor substrate 200 having a contact hole forming region. The first insulating layer 202 is formed of a boro-phospho silicate glass (BPSG) film, and the second insulating layer 204 is formed of a laminated film of a high temperature oxidation (HTO) film and a high density plasma (HDP) film.

Referring to FIG. 2B, a photoresist pattern 206 exposing a contact hole forming region is formed on the second insulating layer 204.

Referring to FIG. 2C, the second insulating layer 204 is first etched until the first insulating layer 202 is exposed using the photoresist pattern 206 as an etching mask to form a groove H. As shown in FIG.

Referring to FIG. 2D, a polymer 208 is formed on sidewalls of the photoresist pattern 206. The polymer 208 is formed to a thickness of 300 to 500 kPa.

Referring to FIG. 2E, the contact hole C is formed by second etching the portion of the first insulating layer 202 on the bottom of the groove using the photoresist pattern 206 including the polymer 208 as an etching mask. The secondary etching may be performed by dry etching, and the first insulating layer 202 may be etched while having a slope that becomes narrower toward the lower portion of the contact hole C.

In this case, during the second etching, the contact hole C may be etched more than the second insulating layer 204 by the first insulating layer 202, so that the lower portion of the contact hole C has a narrower width than the upper portion thereof. Have

As a result, the lower portion of the contact hole C has a concave shape unlike the prior art in the sidewall portion of the first insulating layer 202 due to the polymer 208 during the secondary etching.

Referring to FIG. 2F, after the polymer and the photoresist pattern are removed, pre-cleaning is performed.

Here, in the present invention, since the sidewall portion of the first insulating layer 202 is etched to have a concave shape unlike the prior art due to the polymer 208, the lower portion of the contact hole C becomes convex during the pre-cleaning. Can be suppressed.

Referring to FIG. 2G, the barrier layer 210 is formed on the bottom and side surfaces of the contact hole C including the groove H. The barrier film 210 may be formed of any one of a Ti film and a TiN film, and may be uniformly formed on the entire surface of the concave contact hole C along the profile of the concave contact hole C.

Referring to FIG. 2H, a conductive film 212 is formed on the barrier film 210 to fill the contact hole C. Referring to FIG. The conductive film 212 is formed of a tungsten film.

Subsequently, although not shown, the conductive film 212 and the barrier film 210 are formed by CMP to form a bit line contact, and a subsequent series of well-known processes are sequentially performed to complete a semiconductor device according to an embodiment of the present invention. do.

According to an exemplary embodiment of the present invention, a polymer is formed on a sidewall of a photoresist pattern, and then a contact hole is formed by etching the first insulating layer using the photoresist pattern including the polymer as an etching mask, so that the lower portion of the contact hole may have a concave shape.

Accordingly, the present invention can uniformly deposit the barrier film on the entire surface of the contact hole along the profile of the concave contact hole, thereby improving the bit line contact resistance.

On the other hand, in the above-described embodiment of the present invention, the bit line contact resistance is improved by generating a polymer on the sidewall of the photoresist pattern, but as another embodiment of the present invention, the spacer nitride film is formed on the sidewall of the second insulating layer. The same effect as in one embodiment can be obtained.

3A to 3G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 3A, a first insulating layer 302 and a second insulating layer 304 are sequentially formed on the semiconductor substrate 300 in the contact hole forming region. The first insulating film 302 is formed of a BPSG film, and the second insulating film 304 is formed of a laminated film of an HTO film and an HDP film.

Referring to FIG. 3B, a photoresist pattern 306 exposing a contact hole forming region is formed on the second insulating layer 304.

Referring to FIG. 3C, a groove H is formed by first etching the second insulating layer 304 until the first insulating layer 302 is exposed using the photoresist pattern as an etching mask. Then, the photoresist pattern is removed.

Referring to FIG. 3D, a spacer 308 is formed on the second insulating layer 304 on the sidewall of the groove H. The spacer 308 is formed of a nitride film.

Referring to FIG. 3E, a portion of the first insulating layer 302 on the bottom surface of the groove H is secondly etched until the semiconductor substrate 300 is exposed to form a contact hole C. Referring to FIG. The secondary etching is performed by dry etching.

Referring to FIG. 3F, a barrier layer 310 is formed on the bottom and side surfaces of the contact hole C including the groove H and the spacer 308. The barrier film 310 is formed of any one of a Ti film and a TiN film.

Referring to FIG. 3G, a conductive film 312 is formed on the barrier film 310 to fill the contact hole C. Referring to FIG. The conductive film 312 is formed of a tungsten film. At this time, the barrier film 310 and the tungsten film for filling the contact hole C are smoothly deposited.

Subsequently, although not shown, the conductive film 312 and the barrier film 310 are formed by CMP to form a bit line contact, and then a known subsequent process is performed to complete a semiconductor device according to another embodiment of the present invention.

According to the present invention, after forming the spacer nitride film on the sidewall of the second insulating film, the contact hole is formed by etching the first insulating film below the second insulating film, thereby preventing the lower portion of the contact hole from being convex.

As a result, the barrier film may be uniformly deposited on the entire contact hole along the profile of the contact hole, thereby improving bit line contact resistance.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device according to the related art.

2A through 2H are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

200, 300: semiconductor substrate 202, 302: first insulating film

204 and 304: second insulating film 206 and 306: photosensitive film pattern

208 polymer C contact hole

210, 310: barrier film 212, 312: conductive film

308: spacer H: groove

Claims (14)

Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate; Forming a photoresist pattern on the second insulating layer; Forming a groove by first etching the second insulating layer until the first insulating layer is exposed using the photoresist pattern as an etching mask; Generating a polymer on sidewalls of the photoresist pattern; Forming a contact hole by second etching the portion of the first insulating layer on the bottom of the groove using the photoresist pattern including the polymer as an etching mask; Removing the polymer and the photoresist pattern; Forming a barrier film on the bottom and side surfaces of the contact hole including the groove; And Forming a conductive film to fill the contact hole on the barrier film; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the first insulating film is formed of a BPSG film. The method of claim 1, And the second insulating film is formed of a laminated film of an HTO film and an HDP film. The method of claim 1, The polymer is a method of manufacturing a semiconductor device, characterized in that formed to a thickness of 300 to 500 kPa. The method of claim 1, The secondary etching is a method of manufacturing a semiconductor device, characterized in that performed by dry etching. The method of claim 1, And the second etching is performed such that the first insulating layer is etched while having a slope that becomes narrower toward the bottom of the contact hole. The method of claim 1, And the contact hole is formed to have a narrower width in the first insulating film portion than in the second insulating film portion. The method of claim 1, The barrier film is a semiconductor device manufacturing method, characterized in that formed of any one of a Ti film or a TiN film. Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate; Forming a groove by first etching the second insulating layer until the first insulating layer is exposed; Forming a spacer on the second insulating layer on the sidewalls of the groove; Forming a contact hole by second etching the first insulating layer exposed to the bottom surface of the groove until the semiconductor substrate is exposed; Forming a barrier layer on the bottom and side and the spacer of the contact hole including the groove; And Forming a conductive film to fill the contact hole on the barrier film; Method of manufacturing a semiconductor device comprising a. The method of claim 9, And the first insulating film is formed of a BPSG film. The method of claim 9, And the second insulating film is formed of a laminated film of an HTO film and an HDP film. The method of claim 9, The spacer is a method of manufacturing a semiconductor device, characterized in that formed by a nitride film. The method of claim 9, The secondary etching is a method of manufacturing a semiconductor device, characterized in that performed by dry etching. The method of claim 9, The barrier film is a semiconductor device manufacturing method, characterized in that formed of any one of a Ti film or a TiN film.
KR1020070078226A 2007-08-03 2007-08-03 Method of manufacturing semiconductor device KR20090014016A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148250B2 (en) 2009-03-10 2012-04-03 Hynix Semiconductor Inc. Method for manufacturing semiconductor device for preventing occurrence of short circuit between bit line contact plug and storage node contact plug

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148250B2 (en) 2009-03-10 2012-04-03 Hynix Semiconductor Inc. Method for manufacturing semiconductor device for preventing occurrence of short circuit between bit line contact plug and storage node contact plug

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