KR20070122037A - Method for forming a via hole and a capacitor in semiconductor device - Google Patents

Abstract

A method of forming a via hole in a semiconductor device and a method of forming a capacitor are provided to prevent collapse of a bottom electrode of the capacitor by increasing critical dimension of an opening towards a lower portion of a sacrificial layer. A nitride layer(11) is formed on a substrate(10) including a semiconductor structure layer having a storage node contact plug. A first insulating layer(12) is formed on the nitride as a lowermost layer of a sacrificial layer(15). A second insulating layer(13) is formed on the first insulating layer as an intermediate layer of the sacrificial, the second insulating layer having concentration lower than the first insulating layer. A third insulating layer(14) is formed on the second insulating layer as an uppermost layer of the sacrificial layer, the third insulating layer having concentration lower the second insulating layer.

Description

Via hole formation method and capacitor formation method of a semiconductor device {METHOD FOR FORMING A VIA HOLE AND A CAPACITOR IN SEMICONDUCTOR DEVICE}

1 is a photograph taken using X-SEM (Scanning Electron Microscope) to explain the via hole manufactured by the method for forming a via hole of a semiconductor device according to the prior art.

FIG. 2 is a photograph taken using X-SEM to explain a problem occurring in a capacitor manufactured by a method of forming a capacitor of a semiconductor device according to the prior art.

3A to 3G are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: lower electrode 10: substrate

11 nitride film 12 first insulating film

13: 2nd insulating film 14: 3rd insulating film

15: sacrificial layer 16: hard mask

17 photosensitive film 18: via hole

12A: first nitride film pattern 13A: second nitride film pattern

14A: third nitride film pattern 15A: sacrificial layer pattern

16A: hard mask pattern 17A: photoresist pattern

18A: Sacrificial Layer Pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method of forming a via hole of a semiconductor device, and more particularly, a method of forming a capacitor of a semiconductor device.

As the integration of semiconductor devices increases, design rules continue to decrease. Accordingly, the area occupied by the unit cells is also gradually decreasing. In particular, in a DRAM (Dynamic Random Access Memory) device, since a unit cell is composed of one transistor and one capacitor, it is difficult to control the process when the design rule decreases.

In general, a capacitor of a DRAM device has a widely used concave structure to increase an area. Since the concave structure is formed as a hole, even if the lower electrode, the dielectric film, and the upper electrode are deposited by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process with good step coverage, the coverage is high. There is a limit to this, and the thickness of each material must be reduced to obtain the desired capacitance. In addition, since the oxide layer for the storage node pattern, which is a lower electrode of the capacitor, is deposited very thick, many difficulties are involved in the etching process, and it is not easy to obtain a vertical profile after the etching process.

Therefore, in recent years, a cylinder structure has been proposed as part of increasing the capacity of the capacitor, reducing the difficulty of the etching process and improving the etching profile. However, in the cylinder structure, the lower electrode collapses or adheres to the adjacent lower electrode during the oxide layer etching process for the storage node pattern, which is the lower electrode of the capacitor, and the oxide film removing process using the etching solution after the lower electrode deposition process. .

These phenomena are expected to be closely related to the bottom dimension of the via holes that are formed after the oxide layer etching process for the storage node pattern. Moreover, these phenomena place many constraints on increasing the height of the lower electrode, which in turn leads to many constraints on increasing the capacitance of the capacitor. Furthermore, while reducing the reliability of the device, it is a cause of lowering the yield of the device.

Specifically, an example will be described.

Figure 1 (a) is a method of forming a capacitor according to the prior art, by etching the oxide layer for the storage node pattern to form a via hole, after depositing a polysilicon layer (polysilicon layer) for SEM (Scanning Electron Microscope) imaging X -The picture was taken using SEM. Figure 1 (b) is an X-SEM photograph showing an enlarged 'A' portion shown in (a). As shown in (a) of FIG. 1, it can be seen that the dimension becomes smaller from the top to the bottom of the via hole (CD1> CD2), and as shown in (b), the oxide layer interface of the two-layer structure is enlarged. As can be seen here, it can be seen that the dimension increases at the boundary of the oxide film (CD2 <CD3).

FIG. 2 is an X-SEM photograph taken after the oxide layer etching process and the lower electrode deposition process for the storage node pattern are sequentially performed and the oxide layer is removed. It can be seen that the lower electrode 1 is inclined, as shown in FIG. 2, as 'B' and 'C'. As shown in (a) of FIG. 2, a leaning phenomenon in which neighboring lower electrodes adhere to each other is generated, and a collapse phenomenon in which the lower electrode falls as illustrated in (b) of FIG. 2 is generated. .

As described above, in the case of forming the capacitor using the capacitor forming method according to the prior art, an oxide film removal process using a etching solution after the lower electrode deposition, a dip-out process, or a fall phenomenon of the lower electrode during the dip-out process, etc. This is generated to lower the reliability and yield of the device.

Accordingly, the present invention has been made to solve the above problems of the prior art, has the following objectives.

First, it is an object of the present invention to provide a method for forming a via hole of a semiconductor device capable of increasing a critical dimension of a bottom portion.

Second, another object of the present invention is to provide a method of forming a capacitor of a semiconductor memory device capable of preventing the capacitor lower electrode from falling or tilting.

Third, another object of the present invention is to provide a method of forming a capacitor of a semiconductor memory device capable of increasing the capacity of the capacitor.

According to an aspect of the present invention, there is provided a method including providing a substrate on which an underlayer is formed, and forming an insulating layer including at least two layers of oxide films having different concentrations on the underlayer; And etching the insulating layer to expose the underlayer.

According to another aspect of the present invention, there is provided a substrate on which a storage node contact plug is formed, and at least two layers of oxide layers having different concentrations are stacked on the storage node contact plug. Forming a layer, etching the sacrificial layer to expose the storage node contact plug, forming a storage pattern, and forming a lower electrode along an upper surface of the entire structure including the storage pattern; And separating the neighboring lower electrodes to expose the storage pattern, removing the exposed storage pattern, and forming a dielectric film and an upper electrode on the lower electrode. Provided are a method of forming a capacitor of an element.

According to the present invention, after forming an interlayer insulating film with a multi-layered oxide film having different concentrations, a via hole is formed through an etching process to increase the critical dimension toward the bottom of the via hole. In addition, the present invention is to form a sacrificial layer for the storage node pattern of a multi-layer oxide film having a different concentration in the capacitor formation process of the semiconductor memory device, but the via hole is formed through the sacrificial layer etching process by forming a high-density film toward the bottom layer The bottom dimension may be increased to prevent falling and tilting of the lower electrode formed through a subsequent process.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

3A to 3G are cross-sectional views illustrating a method of forming a capacitor of a semiconductor memory device according to an embodiment of the present invention. For convenience of description, the semiconductor structure layer including the storage node contact plug formed on the substrate is not shown.

First, as illustrated in FIG. 3A, a nitride film 11 is deposited on a substrate 10 on which a semiconductor structure layer including a storage node contact plug is formed. In this case, the nitride layer 11 functions as an etch stop layer during the subsequent etching process of the sacrificial layer 12 for the storage node pattern.

Subsequently, as shown in FIG. 3B, an insulating film 12 (hereinafter referred to as a first insulating film) is formed over the nitride film 11. In this case, the first insulating layer 12 is formed as the highest concentration oxide film having the highest concentration among the insulating layers forming the sacrificial layer 15 as the lowermost layer of the sacrificial layer 15.

Subsequently, as illustrated in FIG. 3C, a second insulating layer 13 is formed on the first insulating layer 12. In this case, the second insulating layer 13 is formed of an oxide layer having a lower concentration than the first insulating layer 12 as an intermediate layer of the sacrificial layer 15.

Next, a third insulating film 14 is formed on the second insulating film 13. At this time, the third insulating film 13 is formed of an oxide film having a lower concentration than the second insulating film 13 as the uppermost layer of the sacrificial layer 15.

In the above, the concentration difference between the first and third insulating films 12, 13, and 14, respectively, with the lower film should be set in consideration of the etching process and the critical dimension. In other words, when the concentration difference is large, the etching process becomes difficult during the etching process of the sacrificial layer 15, and when the concentration difference is small, the critical dimension at the boundary surface of each layer cannot be large. Therefore, in the embodiment of the present invention is formed to be at least 2wt% or more, preferably 2wt% ~ 10wt%.

The thicknesses of the first and second insulating films 12 and 13 are formed to be 500 to 3000 kPa. This is because the dimension of the opening decreases linearly from the top to the bottom during the etching process of the sacrificial layer 15. The dimension at the bottom of the opening is considered in consideration of the size of the opening decreasing linearly from the top to the bottom. To take as large as possible.

Subsequently, a hard mask 16 is formed on the sacrificial layer 15. Here, the hard mask 16 is formed to compensate for the thickness limit of the photoresist pattern to be formed through a subsequent photo process. The hard mask 16 is formed of a nitride film-based material.

Subsequently, a BARC (Bottom Anti-Reflective Coating) film (not shown) is applied on the hard mask 16.

Next, the photosensitive film 17 is apply | coated on BARC film.

Subsequently, as illustrated in FIG. 3D, an exposure process and a development process using a photo mask are sequentially performed on the photosensitive film 17 to form the photosensitive film pattern 17A.

Subsequently, an etching process using the photosensitive film pattern 17A as an etching mask is performed to etch the BARC film and the hard mask 16. As a result, the hard mask pattern 16A is formed.

Subsequently, as illustrated in FIG. 3E, an etching process using the photoresist pattern 17A and the hard mask pattern 16A as an etching mask is performed to form the third insulating film 14 (see FIG. 3D) and the second insulating film 13 (FIG. Etch sequentially). As a result, the third insulating film pattern 14A and the second insulating film pattern 13A are formed. At this time, since the second insulating film 13 is made of a higher concentration oxide film than the third insulating film 14, the second insulating film 13 is faster than the third insulating film 14. Accordingly, the critical dimension of the opening in the second insulating film 13 is formed to be larger (CD2> CD1).

Next, as shown in FIG. 3F, in the same chamber as the process shown in FIG. 3E, an etching process using the photoresist pattern 17A as an etching mask is successively performed, thereby performing the first insulating film 12 (see FIG. 3E). Selectively etch the bay. At this time, the etching process is performed using the nitride film 11 as an etching stop film. As a result, the first insulating film pattern 12A is formed. Here, since the first insulating film 12 is made of a higher concentration oxide film than the second insulating film 13 (see FIG. 3D), the first insulating film 12 is faster than the second insulating film 13. Accordingly, the critical dimension of the opening in the first insulating film 12 is larger than that in the second insulating film 13 (CD3> CD2).

In addition, '15A', which is not described in FIG. 3F, is a sacrificial layer pattern.

Meanwhile, the etching gas used in the etching process of the first to third insulating layers 12, 13, and 14 described with reference to FIGS. 3E and 3F is an additive gas such as Ar and O ₂ to a source gas based on fluorine. It is carried out using. Also, each etching process is overetched by about 10 ~ 30%.

Next, as illustrated in FIG. 3G, an etching process using the photosensitive film pattern 17A as an etching mask is performed to etch the nitride film 11 (see FIG. 3F). As a result, a nitride film pattern 11A through which the storage node contact plug is exposed is formed. At this time, the critical dimension between the nitride film patterns 11A is increased corresponding to the size of the critical dimension of the first insulating film pattern 12A.

Subsequently, the photoresist pattern 17A is removed by a strip process, and then the hard mask pattern 16A is removed to complete the formation of the sacrificial layer pattern 15A. As a result, the via hole 18 for the storage node is formed.

Subsequently, although not shown, a lower electrode is formed along a step of the upper surface of the entire structure including the via hole 18. At this time, the lower electrode is formed to a thickness of about 100 ~ 1000Å in a polysilicon film or Ti / TiN laminated structure.

Subsequently, the lower electrode is etched to separate the neighboring capacitors to expose the sacrificial layer pattern 15A.

Subsequently, the exposed sacrificial layer pattern 15A is removed using an etching solution based on HF. In this case, the sacrificial layer pattern 15A may be removed by a wet dip out process.

Subsequently, a dielectric film and an upper electrode are sequentially formed on the lower electrode to complete the capacitor.

On the other hand, the above method for different concentration between the insulating film is as follows.

For example, in the case of forming the sacrificial layer 15 in the PSG (Phosphorus Silicate Glass) film, PSG film, a source gas of TEPo (Tri Ethyl Phosphate), TEOS (Tetra Ethyle Ortho Silicate) and O ₃ increase the flow rate of the TEPo gas of By doing so, it is possible to implement a high concentration oxide film. That is, the higher the flow rate of the gas of TEPo, the higher the concentration of the oxide film. On the other hand, when the sacrificial layer 15 is formed of a BPSG (Boron Phosphorus Silicate Glass) film, similar to the PSG, it is possible to control the concentration of TEB (Tri Ethyl Borate) to bring the concentration difference.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the sacrificial layer of the capacitor lower electrode or the inclination is formed by forming the sacrificial layer for the storage node pattern as a multilayer oxide film having different concentrations and increasing the critical dimension of the opening toward the lower portion of the sacrificial layer. The phenomenon can be prevented. In addition, it is possible to increase the capacity of the capacitor by increasing the critical dimension of the opening.

Claims (7)

Providing a substrate on which an underlayer is formed; Forming an insulating film in which at least two layers of oxide films having different concentrations are stacked on the base layer; And Etching the insulating layer to expose the underlayer Via hole forming method of a semiconductor device comprising a. The method of claim 1, The insulating layer is a via hole forming method of a semiconductor device consisting of an oxide film having a higher concentration toward the bottom. The method of claim 2, The difference in concentration between the oxide film is a method for forming a via hole of a semiconductor device 2 ~ 10wt%. Providing a substrate having a storage node contact plug formed thereon; Forming a sacrificial layer including at least two layers of oxide films having different concentrations on the storage node contact plugs; Etching the sacrificial layer to expose the storage node contact plug to form a storage pattern; Forming a lower electrode along an upper surface of the entire structure including the storage pattern; Separating the adjacent lower electrodes such that the storage pattern is exposed; Removing the exposed pattern for storage; And Forming a dielectric film and an upper electrode on the lower electrode Capacitor formation method of a semiconductor device comprising a. The method of claim 4, wherein The method of claim 1, wherein the sacrificial layer is formed of an oxide film having a higher concentration toward the bottom. The method of claim 5, The concentration difference between the oxide film is a method of forming a capacitor of the semiconductor device 2 ~ 10wt%. The method of claim 4, wherein Before forming the sacrificial layer, forming an etch stop layer on the storage node contact plug.

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