KR20090006019A - Method of forming micropattern - Google Patents

Abstract

The pattern formation method is provided to form the micro-patterns like holes. The resist pattern is formed by patterning the resist layer formed on the process target substrate. The melting process is performed on the resist film remaining in the space part of the resist pattern. The liquid is supplied to the remaining resist film to remove the remaining resist film. The resist defect remaining in the space part(space pattern) formed in the resist film of the first resist pattern is removed. The space part is small and narrow.

Description

Micro pattern formation method {METHOD OF FORMING MICROPATTERN}

Cross Reference of Related Application

This invention claims priority based on Japanese Patent Application No. 2007-181318 for which it applied on July 10, 2007, and uses the whole content here as a reference.

The present invention relates to a pattern formation method for a lithography step for forming a semiconductor device, and to a pattern formation method enabling fine pattern formation.

Various pattern forming techniques have been proposed to form a pattern in a desired shape in the lithography step. In particular, as the miniaturization and integration of various electronic devices including semiconductor devices and liquid crystal devices have increased considerably, a pattern forming technology capable of forming finer patterns in desired shapes has recently been required. For example, by using an ultraviolet light source (UV), a deep ultraviolet light (DUV), an extreme ultraviolet light (EUV), or an electron beam (EB), fine patterns exceeding the critical resolution of the exposure apparatus can be formed into a desired shape. Pattern formation techniques were needed.

Thus, for example, a pattern forming technique called a narrow space forming technique has been proposed, which uses any of the above-described light sources to form the pattern into a desired shape more finely than the critical resolution of the exposure apparatus. An example of a narrow space formation technique is briefly described.

First, a resist pattern is formed on the resist film using any of the above-described light sources, and a complementary film which interacts with the resist film is formed on the resist film based on the selected process. Subsequently, a kind of crosslinked mixed layer is formed between the resist film and the complementary film, for example, by a baking process. A part of the uncombined complementary film is removed from the resist film to form a narrower space portion narrower than the space portion in the resist film constituting the resist pattern. This narrow space formation technique enables the formation of via plugs that are finer than the critical resolution of an exposure apparatus using any of the light sources described above, and interconnections whose line width is smaller than the critical resolution.

As a type of narrow space formation technique, a technique called Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS ™) has been proposed. For example, as disclosed in the web feature article "Semiconductor 0.1-μm hole pattern formation technique RELACS" provided by Mitsubishi Electric Corporation, this technique firstly comprises a hole formed in the resist film by coating, as part of the resist pattern. The upper layer is formed on the same spatial pattern. Subsequently, heat treatment is performed on the resist film and the top coating film to add an acidic component to the resist film so as to interact with the top coating film to form a thermosetting layer at the interface portion between the films. Next, rinsing with pure water removes the upper coating film except for the portion corresponding to the thermal curing layer. Thus, a finer spatial pattern is formed than the holes or the like formed in the resist film.

However, this technique may not sufficiently remove the top coating layer except for the portion corresponding to the thermosetting layer. Therefore, a fine spatial pattern such as a hole may not be formed.

Moreover, techniques for forming thin deposits and finer spaces on resists are described on the Internet homepage Lam Research (2300 motif) and in Proc. of SPIE Vol. 6519 (2007). This technique is effective to further reduce patterns having a size close to the critical resolution.

However, an open pattern with a size close to the critical resolution may be at footing condition or due to slight fluctuations in lithographic processing, for example fluctuations in exposure dose or baking temperature, or fluctuations in cleaning conditions during development. Half can be opened. Under these conditions, applying the above-described RELACS or 2300MOTIF, an inappropriate pattern such as an unopened pattern may be formed.

According to one aspect of the invention, patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; And forming a moisture containing film on the front surface of the process target substrate in the space portion of the resist pattern, irradiating light to the moisture containing film, and supplying liquid containing moisture to the moisture containing film. A method is provided.

According to another aspect of the invention, patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; Performing a dissolution process on the resist film remaining in the space portion of the resist pattern; Supplying a liquid for removing the resist film to remove the resist film remaining in the space portion of the resist pattern; Introducing a material for the pattern forming complementary film formed in the film through interaction with the resist film, into the space portion of the resist pattern; Selectively forming a pattern forming complementary film on an inner surface of the space portion by causing a material for the pattern forming complementary film to interact with the resist film; And removing a portion of the pattern forming complementary material, which is not formed in the film, from the inside of the spaced portion, while exposing the remaining portion of the patterned complementary film to the spaced portion, thereby exposing a portion of the bottom surface of the spaced portion. A pattern forming method comprising the steps is provided.

According to another aspect of the invention, patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; Performing a dissolution process on the resist film remaining in the space portion of the resist pattern; Supplying a liquid for removing the resist film, the liquid comprising a pattern forming complementary material formed into a film through interaction with the resist film; Selectively forming the pattern forming complementary film on the inner surface of the space portion by causing the pattern forming complementary material to interact with the resist film; And removing a portion of the pattern forming complementary material which is not formed in the film from the inside of the space portion, while remaining the portion of the patterned complementary film in the space portion, thereby removing a portion of the bottom surface of the space portion. A pattern forming method is provided that includes exposing.

According to the present invention, a pattern forming method for forming a fine pattern can be provided.

(First embodiment)

First, the pattern forming method according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, and 5C. . In the present embodiment, a technique for forming a narrow space by making the pattern forming complementary film act as a resist pattern will mainly be described. In addition to enabling the formation of a narrow space, the narrow space formation technique according to the present embodiment reduces defects in the space portion.

For example, the resist defect remaining in the space portion (space pattern) of the first resist pattern formed in the resist film is removed while the space portion is narrowed. Next, based on the narrowed spatial pattern, hole patterns for plug formation such as via plugs or contact plugs or trench patterns forming interconnects are formed. The second resist pattern having the narrow space pattern formed according to the present embodiment is a micropattern with almost no defects. Therefore, applying the present embodiment improves the reliability of various electronic devices such as semiconductor devices and liquid crystal devices. That is, the pattern forming technique according to the present embodiment is applicable to a method of manufacturing an electronic device such as a method of manufacturing a semiconductor device and a liquid crystal device. The present embodiment will be described in detail below.

First, as shown in FIGS. 1 and 2A, an interlayer insulating film 2 composed of SiO ₂ , for example, is a kind of process target on one main surface (front surface) of the semiconductor substrate 1 as a process target substrate. It is formed as a film. This is shown as step 1 (S-1) in the flowchart of FIG. Subsequently, an antireflection film 3 for ArF light is formed on the interlayer insulating film 2 by the spin coating method as a kind of process target film. This is shown as step 2 (S-2) in the flowchart of FIG. Subsequently, a chemically amplified resist film 4 that is photosensitive to AfF light is formed on the antireflection film by spin coating. This is shown as step 3 (S-3) in the flowchart of FIG.

Next, a latent image is formed on the resist film 4 using the spinning or charged particle lines. In this case, although aligned to the interconnection pattern (not shown) to be formed on the semiconductor substrate 1, the pattern 5a described below is exposed using an ArF exposure apparatus (not shown). This is shown in step 4 (S-4) in the flow chart of FIG. In this ArF exposure step, although not shown in the figure, a mask pattern including a hole pattern formed in an exposure mask provided on the ArF exposure apparatus is projected onto the resist film 4 on the semiconductor substrate 1 so as to be reduced. In the ArF exposure step, the exposure mask and the semiconductor substrate 1 are moved relative to each other to expose the mask pattern and to transfer the mask pattern to the front surface of the resist mask 4 during mask pattern alignment.

Subsequently, a heating process is performed at least at approximately 75 ° C. on the entire semiconductor substrate 1 including the resist film 4 to which the mask pattern is exposed and transferred. This is shown in step 5 (S-5) in the flowchart of FIG. The temperature at which the post exposure baking process is performed needs to be set to a value at which an acid diffusion reaction effectively occurs in the resist film 4. In this case, the post-exposure bake process is performed at approximately 120 ° C. where the dimensional uniformity of the developed resist pattern falls within an acceptable range. Next, the whole semiconductor substrate 1 to which the post-exposure baking process is performed is cooled to room temperature.

Next, the region of the resist film 4 in which the latent image is formed or the region of the resist film in which the latent image is not formed is selectively removed to form the first resist pattern 5. In this case, the development process is performed on the cooled resist film 4 to form the first resist pattern 5 including the hole pattern 5a in a space pattern (space portion) on the resist film 4. . This is shown in step 6 (S-6) in the flow chart of FIG. In this case, the diameter of the formed first hole pattern 5a is approximately 100 nm. In addition, after completion of the development process step, the inventors inspected the resulting structure for defects using a DUV optical defect inspection apparatus having a resolution of approximately 60 nm. An unopened first hole pattern 5a was not observed on the front surface of the first resist pattern 5. However, an unwanted resist film 4a remained inside the first hole pattern 5a as a residue.

As shown in Figs. 1 and 2B, an anisotropic etching process, a kind of dry etching, is performed on the first resist pattern 5a to remove the residue 4a from inside the first hole pattern 5a. This is shown in step 7 (S-7) in the flow chart of FIG. In this case, the semiconductor substrate 1 on which the first resist pattern 5 is formed is provided in the dry etching apparatus. Next, the address first hole pattern 5a is dry etched by the oxygen plasma. At this time, dry etching conditions are set so that the etching rate in the direction perpendicular to the front surface 1a of the semiconductor substrate 1 is higher than the etching rate in the other direction. More specifically, the dry etching may be performed at an etching rate at which the residue 4a in the first hole pattern 5a can be crushed and removed from above according to the size or amount of the residue 4a. . In this case, dry etching is performed at an etching rate at which the residue 4a having a thickness (height) of approximately 5 nm can be crushed and removed from above. Even for the first hole pattern 5a that appears to be free of residues 4a, the process is effective to remove organic contaminants from the front surface of the spatial pattern.

The residue removal process is not limited to dry etching. Any other process corresponding to the method of reducing the size of the residue may be used to remove the residue 4a from inside the first hole pattern 5a or to avoid possible pattern defects. However, in the residue removal process, as the width of the spatial pattern is increased, the subsequent hole reduction effect is degraded. Therefore, the residue removal process is preferably performed by anisotropic etching so that the etching rate in the direction perpendicular to the front surface 1a of the semiconductor substrate 1 is higher than the etching rate in the other direction.

Next, as shown in FIGS. 1 and 3A, the material for the pattern forming complementary film 7 is provided on the first resist pattern 5 (resist film 4) by the spin coating method. The residue 4a is filled in the removed hole pattern 5a; The material 6 is formed in the pattern forming complementary film 7 by interaction with the resist film 4. This is shown in step 8 (S-8) in the flow chart of FIG. The material 6 of the pattern forming complementary film 7 is called RELACS ™ (Resolution Enhancement Lithography Assisted by Chemical Shrink) material.

Next, as shown in FIGS. 1 and 3B, the RELACS ™ material 6 and the resist film 4 interact with each other in the RELACS ™ material 6 and the resist film 4 so that the first resist pattern ( 5) A heating process (baking process) is performed to form the pattern forming complementary film 7 on the front surface of the (resist film 4). This is shown in step 9 (S-9) in the flowchart of FIG. In particular, the pattern forming complementary film 7 is formed by performing a baking process to thermally crosslink the mixed layer where RELACS ™ and the resist film 4 are mixed. Therefore, the pattern forming complementary film 7 is not formed to fill the entire inside of the first hole pattern 5a. The pattern forming complementary film 7 is formed by selectively growing at the edge of the bottom surface of the hole pattern 5a to cover the inner surface of the first hole pattern 5a. The pattern forming complementary film 7 is hereinafter referred to as RELACS ™ film. Subsequently, the entire semiconductor substrate 1 on which the RELACS ™ film 7 is formed is cooled.

Next, as shown in FIGS. 1 and 4A, the cooled entire semiconductor substrate 1 is washed with, for example, pure water, from the inside of the first hole pattern 5a and the first resist pattern 5. Remove the RELACS ™ material 6 not yet formed in the film from the front surface of the < RTI ID = 0.0 > Thus, only the RELACS ™ film 7 remains on the inner side surface of the first hole pattern 5a and on the front surface of the first resist pattern 5. This is shown in step 10 (S-10) in the flow chart of FIG. As a result, the first hole pattern 5a is reduced by partially exposing, that is, exposing the entire area of the first hole pattern 5a except the edge of the bottom surface. In this case, the first hole pattern 5a is reduced such that the diameter of the pattern 5a is reduced from about 100 nm to about 80 nm described above. The narrow space pattern in which the first hole pattern 5a is reduced is referred to as a second hole pattern 8a. The resist pattern including the second hole pattern 8a and composed of the first resist pattern 5 and the RELACS ™ film 7 is referred to as a second resist pattern 8. After completing the cleaning process steps, we examined the resulting semiconductor substrate for defects using DUV light with a resolution of approximately 60 nm. Next, the ratio of the unopened second hole pattern 8a to the open second hole pattern 8a was approximately 1 to 100 million (100 million). Thus, the main steps of the pattern forming method according to the present embodiment are completed.

Next, as shown in FIGS. 1 and 4B, the anti-reflection film 3 is processed through the second resist pattern 8 as a mask to apply the anti-reflection film 3 so as to communicate with the second hole pattern 8a. The first through hole 9 penetrates is formed. In this case, the first through hole 9 is an anisotropic etching process on the antireflection film 3 such that the etching rate in the direction perpendicular to the front surface 1a of the semiconductor substrate 1 is higher than the etching rate in the other direction. It is formed using an oxygen plasma to apply (dry etching process). Subsequently, the interlayer insulating film 2 is processed through the antireflection film 3 and the first resist pattern 8 on which the first through hole 9 is formed as a mask to communicate with the first through hole 9. The second through hole 10 penetrating the insulating film 2 is formed. In this case, the second through hole 10 is formed by performing a dry etching process on the interlayer insulating film 2 under the same conditions as those under which the first through hole 9 is formed using a fluorocarbon containing gas. The plug formation hole pattern 10 is fine and has a diameter of approximately 80 nm similar to the second hole pattern 8a.

Next, as shown in Fig. 5A, the resist film 4 and the anti-reflection film 3 are removed from the front surface of the interlayer insulating film on which the plug formation hole pattern 10 is formed. Subsequently, as shown in FIG. 5B, the barrier metal film 11 and the conductor 12 constituting the contact plug (via plug) are placed inside the second through hole 10 and on the front surface of the interlayer insulating film 2. Laminated sequentially. Next, as shown in Fig. 5C, the conductor 12 and the barrier metal film 11 are filled in the plug formation hole pattern 10 by, for example, the CMP method. Thus, a fine contact plug 12 having a diameter of approximately 80 nm is formed inside the interlayer insulating film 2 so that the side and bottom surfaces of the plug 12 are covered with the barrier metal film 11. Therefore, the main steps of the manufacturing method of the electronic device according to the present embodiment are completed.

Now, a comparative example of this embodiment will be described.

The inventors experimentally formed the RELACS ™ film without performing the anisotropic etching step (residue removal process step) described above with reference to FIG. 2B and corresponding to step 7 (S-7) in the flowchart of FIG. 1. That is, it is formed by selectively growing on the sidewall surface and the upper surface of the first resist pattern without removing residue from the inside of the first hole pattern. Thus, the diameter of the first hole pattern is reduced from about 100 nm to about 80 nm to form the second hole pattern.

The inventors used the same DUV light defect inspection apparatus as used in this example, in which the second hole pattern had a resolution of approximately 60 nm to inspect for defects the entire front surface of the resist film formed by the above-described steps. . The ratio of the unopened second hole pattern to the open second hole pattern was approximately 1 to 10000. The cross-sectional shape of the unopened second hole pattern was also examined to find a large residue consisting of a residue of the resist film and a RELACS ™ film deposited on the residue. More specifically, the inventors found that a residue composed of a resist film and a RELACS ™ film was formed on the bottom surface and the inner surface of the second hole pattern; The residue was formed as a result of the growth of the resist film and the RELACS ™ film through the interaction between the resist film and the RELACS ™ material, and the width was approximately 70 nm. Such residue is thought to have been formed by an incomplete developing process due to the difficulty of substitution of the developer inside the first hole pattern at the stage of the developing process (step 6). Thus, it was found that a residue composed of a resist film and a RELACS ™ film formed an unopened second hole pattern and was detected as a defect pattern.

Thus, unlike the case of this embodiment, in the comparative example in which the RELACS ™ film is formed without omitting the residue removal process step (step 7) after the developing step (step 6), an unwanted resist film may remain inside the first hole pattern. . When the resist film is left inside the first hole pattern, a RELACS ™ film is formed on the residue. Thus, the residue grows more and the holes can be blocked. That is, the first hole pattern may not be formed to have a desired open shape, and thus may be a defect. The defect pattern tends to cause defects in the plug formation pattern or the interconnect formation pattern formed based on the defect pattern. When filled with a defective plug or interconnect formation pattern, the conductor has difficulty in ensuring sufficient contact. As a result, the performance, quality, reliability, durability, and the like of the electronic device deteriorate.

The present inventors experimentally formed the plug formation pattern based on the first and second hole patterns formed by the pattern formation method according to the comparative example described above. As a result of the experiment, it was found that the ratio of the unopened plug formation pattern to the acceptable plug formation pattern was approximately 1 to 3,000. That is, as a result, the occurrence rate of the defect pattern at the time of formation of the plug formation pattern was at least three times higher than that of the defect pattern at the time of formation of the second hole pattern. It has been found that such defective openings are the result of a number of defects due to the aforementioned residues when the first hole pattern is reduced to the second hole pattern. In addition, the plug formation pattern with such a defect opening is formed by not fully etching the SiO ₂ film constituting the interlayer insulating film or stopping the etching of the SiO ₂ film during the process. In addition, after etching the SiO 2 film, the result after hole reduction showed an increase in the defect pattern occurrence rate. This is because the size of the plug was less than the detection sensitivity because not only the RELACS ™ film but also a large number of plug formation patterns in which the residue was grown remain on the residue of the resist film.

In contrast, in this embodiment, the probability of occurrence of the unopened plug formation pattern 10 after formation of the plug formation pattern 10 corresponds to a ratio of approximately 1 to 100 million as described above. That is, in this embodiment, the residue removing process step (step 7) is performed after the developing step (step 6) to remove the residue 4a of the resist film 4 from inside the first hole pattern 5a and , A RELACS ™ film 7 is formed for hole reduction. Therefore, the defect pattern incidence rate did not increase after the SiO ₂ film etching step. Accordingly, the present invention significantly improves the probability of occurrence of the unopened plug formation pattern 10 after the formation of the plug formation pattern 10 as compared with the comparative example described above.

As described above, even for the fine narrow space pattern 8a exceeding the limit of the resolution of the exposure apparatus, the first embodiment allows such a plurality of narrow space patterns 8a to be formed in a desired shape, while The defect occurrence rate of the pattern 8a can be reduced. Further, by forming the contact plug 12 or the like based on the narrow space pattern 8a, various electronic devices such as semiconductor devices and liquid crystal devices can be miniaturized without deteriorating the performance, quality, reliability, durability, etc. of the device. It can be manufactured to be integrated. In addition, when fine contacts or via plugs are typically formed, a technique called double vias can be used that forms two contact or via plugs for each interconnect as a remedy for defects such as improper electrical conductance. However, this technique needs to form two plugs, and thus can increase the number of steps required to reduce manufacturing efficiency. In contrast, this embodiment allows fine contacts or via plugs to be formed with almost no defects. As a result, it is sufficient to form one contact or via for each interconnect. Therefore, the present embodiment can improve the manufacturing efficiency of the electronic device and reduce the manufacturing cost.

In this embodiment, ArF exposure is applied to the method described above. However, the present invention is not limited to this aspect. For example, by using KrF light as an exposure light source instead of ArF light and applying this embodiment to an exposure process using KrF chemical amplification resist instead of ArF chemical amplification resist 4, the effect similar to that described above is obtained. Can be exercised. Alternatively, the effect similar to that described above applies the invention to an EUV exposure treatment which exposes a fine hole pattern or an exposure treatment using an I line from a mercury lamp which exposes a relatively large pattern compared to the EUV exposure treatment. Can be exerted. In addition, of course, effects similar to those described above require very high processing accuracy, for example, when many holes are not opened, and nano-imprints in which the tip of the pillar pattern is broken or touched. It can be exercised by applying the present invention to what is called a lithography process.

This embodiment performs a process to reduce the diameter of the first hole pattern to about 100 nm to about 80 nm. However, the size of the first hole pattern 5a or the second hole pattern 8a is not limited to this aspect. This embodiment is of course applicable to the step of reducing the width of the hole pattern or the spatial pattern to a size close to the threshold resolution determined by the illumination condition and the NA condition for the exposure apparatus, for example. In addition, the amount of reduction (the amount of holes narrowing) from the first hole pattern 5a to the second hole pattern 8a is about 20 nm. However, the reduction is not limited to this aspect. In general, the defect pattern occurrence rate increases consistently with the shrinkage amount. Thus, of course, increasing the amount of shrinkage during the narrow space pattern forming process makes the applicability of the present invention more convenient.

Moreover, the conventional antireflection film 3 may contain an acid. The acid may react with the RELACS ^™ material 6 to form a RELACS ^™ film 7 over the bottom surface of the first hole pattern 5a. Therefore, in this embodiment, the temperature at which the antireflection film 3 is formed is increased to the temperature at which the acid in the antireflection film is deactivated. This suppresses that the RELACS ^™ film 7 is formed on the antireflection film 3 to form the bottom surface of the first hole pattern 5a.

In contrast, if the temperature at which the antireflection film 3 is formed is lower than the temperature at which the acid in the antireflection film is deactivated, the acid continues to exist in the antireflection film 3. Thus, when formed on the antireflective film 3 is a low temperature, a portion of the RELACS ^TM film 7 RELACS ^TM film 7, a part formed on the front surface of the resist pattern 5 (resist film 4) of the Although not as thick as this, the RELACS ^™ film 7 may be formed on a portion of the antireflective film 3 exposed from the bottom surface of the first hole pattern 5a. However, since a part of the RELACS ^™ film 7 formed on the antireflection film 3 is very thin, this part is scraped when the first through hole 9 is formed in the antireflection film 3. In this case, therefore, an effect similar to that described above can be exerted.

(2nd Example)

Now, a pattern forming method according to a second embodiment of the present invention will be described with reference to FIGS. 6, 7A, 7B, 8A, 8B, 9A, and 9B. Components of the second embodiment that are identical to those of the first embodiment are denoted by the same reference numerals and will not be described in detail. Unlike the first embodiment, this embodiment uses a hard mask layer instead of the antireflection film. In addition, upon exposure of the resist pattern, soft X-rays (ultra-short wavelength ultraviolet light; extreme ultraviolet (EUV)) are used as the exposure light source instead of ArF light. In addition, instead of the anisotropic etching, a liquid is used to remove the residue from inside the hole pattern. The pattern forming method according to this embodiment will be described in detail.

First, as shown in FIGS. 6 and 7A, the hard mask layer 21, a kind of process target film, is formed by spin coating on the interlayer insulating film 2 formed on the front surface 1a of the semiconductor substrate 1. . In this case, the hard mask layer 21 was manufactured by sequentially forming a carbon-containing coating film and a spin on glass coating film. This is shown as step 11 (S-11) in the flowchart of FIG. Subsequently, a chemically amplified resist film 22 sensitive to soft X-rays (EUV) is formed on the hard mask layer 21 by spin coating. This is shown as step 12 (S-12) in the flowchart of FIG.

Then, as in the case of step 4 (S-4) according to the first embodiment, a latent image (not shown) is selectively formed on the resist film 22. However, unlike the case of the first embodiment, in this embodiment, the resist film 22 is exposed to the latent image using an EUV exposure apparatus (not shown) instead of the ArF exposure apparatus. This is shown as step 13 (S-13) in the flowchart of FIG.

Next, as in the case of step 5 (S-5) according to the first embodiment, the entire semiconductor substrate 1 including the resist film 22 on which the latent image is formed is heated at about 75 ° C. The entire semiconductor substrate 1 after exposure is cooled to room temperature.

Then, as in the case of step 6 (S-6) according to the first embodiment, the first resist pattern 23 including the first hole pattern 23a is formed on the resist film 22. However, this embodiment forms the first hole pattern 5a having a diameter of 45 nm instead of the first hole pattern having a diameter of 100 nm as in the case of the first embodiment. As in the case of the first hole pattern 5a according to the first embodiment, an unwanted resist film 22a is left inside the first hole pattern 23a.

Next, as in the case of step 7 (S-7) according to the first embodiment, the residue 22a is removed from the first hole pattern 23a. However, unlike the first embodiment, this embodiment does not use anisotropic etching to remove the residue 22a. In this embodiment, first, a dissolution process is performed on the resist pattern 23, which is applied to the liquid used to remove the residue 22a in which the resist film 22 is left inside the first hole pattern 23a. It is intended to be easily dissolved. Next, the removal liquid is used to remove the residue 22a. This process will be described in more detail below.

First, a water dissolution process is performed on the entire front layer portion of the first resist pattern 23 and the entire residue 22a so that the front surface of the resist film 22 is easily dissolved in an aqueous solution. In this case, the front surface of the resist film 22 (first resist pattern 23) is washed with water. Next, the resist film 22 is spin dried while appropriately adjusting the drying time. This causes the front surface of the resist film 22 to adsorb moisture (water vapor) to form a thin moisture-containing film. This adsorption process is not limited to the method described above. Although not shown in the figure, a thin moisture film 24 may also be formed on the front surface of the resist film as follows. Due to the water film formed on the front surface of the resist film 22, the semiconductor substrate 1 is cooled to at most 0 ° C. to form an ice layer on the front surface of the resist film 22. The unfrozen water film is quickly removed from the front surface of the resist film 22 to form an ice film having a thickness of about 1 탆 on the front surface of the resist film 22. Alternatively, the thin moisture film 24 may be formed on the front surface of the resist film 22 in a high humidity region by cooling the semiconductor substrate 1 or causing condensation water on the semiconductor substrate 1.

Next, as shown in FIG. 6 and FIG. 7B, a resist film 22 having a water containing film 24 formed on the front surface in order to absorb moisture from the water containing film 24 to generate radicals. (First resist pattern 23) is irradiated with light having a wavelength? Of about 200 nm or less. Therefore, moisture adsorbed on the first resist pattern 23 is radicalized by adding hydroxyl groups (OH groups) to the front surface of the first resist pattern 23, which is a hydrophobic resin layer. As a result, the front layer portion of the first resist pattern 23 is turned into the hydrophilic layer 25. Although not shown, an excimer lamp is an example of a simple device capable of irradiating the resist film 22 with light having a wavelength? Of about 200 nm or less. Preferably, the exposure light source for an excimer lamp is, for example, an Xe ₂ light source having a wavelength λ of 172 nm, a Kr ₂ light source having a wavelength λ of 146 nm, or an Ar ₂ light source having a wavelength λ of 126 nm. The results of our experiments show that the reduced wavelength of the irradiated light emitted to the resist film 22 makes it possible to suppress the promotion of the irradiated light at the film surface. This makes it possible to easily prevent dishing of the resist pattern 23 during the cleaning step with water described above.

Of course, the water dissolution process, which has been described above and consists of an adsorption process and a light irradiation process, is similarly performed for the residue 22a in the first hole pattern 23a. Thus, residue 22a is converted to hydrophilic residue 25 because it reacts similar to that described above.

Next, as shown in FIGS. 6 and 8A, cleaning is performed on the front surface of the first resist pattern 23 having the front layer portion and the hydrophilic layer 25 formed on the hydrophilic residue 25. Thus, the first resist pattern 23 (the front layer portion of the resist film 22 is dissolved by about 3 nm.) A hydrophilic residue (resist defect) 25 having a width of about 30 nm left in the first hole pattern 23a. ) Is removed by dissolving in water The aforementioned water dissolving process and water washing process are shown as step 14 (S-14) in the flowchart of Fig. 6. The water dissolving process and the water washing process shown in step I4 are wet etching processes. It can be considered a kind of preprocess and wet etching process.

Next, as shown in Figs. 6 and 8B, as in the case of step 8 (S-8) according to the first embodiment, the aqueous solution 26 including the RELACS ^TM film 7 is formed into a first resist pattern. (23) (resist film 22), the aqueous solution 26 is filled in the first hole pattern 23a from which the residue 25 has been removed.

Next, as shown in FIGS. 6 and 9A, the water soluble RELACS ^™ material 26 is spin dried. Thus, almost all moisture contained in the water-soluble RELACS ^™ material 26 will evaporate and the RELACS ^™ material 26 will turn into a dry spin coating film 27.

Next, as shown in FIGS. 6 and 9B, as in the case of step 9 (S-9) according to the first embodiment, the spin coating film 27 and the resist film (including the RELACS ^TM material 26) For 22) a baking process is performed. The RELACS ^™ material of this spin coating film 27 interacts with the resist film 22 to form a RELACS ^™ film 28 on the front surface of the first resist pattern 23 (resist film 22). Next, the entire semiconductor substrate 1 on which the RELACS ^™ film 28 is formed is cooled.

Next, although not shown in the figure, as in the case of step 10 (S-10) according to the first embodiment, the entire cooled semiconductor substrate 1 is washed with water to form the interior of the first hole pattern 23a. From and from the front surface of the first resist pattern 23, the water soluble spin coating film 27 that is not changed to the RELACS ^™ film 28 is removed. Thus, only the RELACS ^™ film 28 is left on the inner surface of the first hole pattern 23a and the front surface of the first resist pattern 23. As a result, the first hole pattern 23a is reduced by partially exposing, that is, reduced by exposing the entire area of the first hole pattern 23a except the edge of the bottom surface. In this case, the first hole pattern 23a is reduced so that the diameter of the pattern 23a is reduced from about 45 nm to about 30 nm. The narrow space pattern in which the first hole pattern 23a is reduced constitutes the second hole pattern. The resist pattern including the second hole pattern and consisting of the first resist pattern 23 and the RELACS ^™ film 28 constitutes the second resist pattern. In step 10, that is, in the water washing step, when the aqueous solution is used as a wash fluid instead of water, the aqueous solution can be used for washing. Thus, the main steps of the pattern forming method according to this embodiment have been completed.

Next, although not shown in the figures, steps similar to those described in the first embodiment with reference to FIGS. 4B and 5A to 5C are covered with a barrier metal film on the side and bottom surfaces inside the interlayer insulating film 2. To form a fine contact plug 12 having a diameter of about 45 nm. Thus, the main steps of the method of manufacturing the electronic device according to the present embodiment have been completed.

The present inventors have contact holes in which contact plugs are formed in the interlayer insulating film 2 based on a second hole pattern for a defect hole generation rate using a voltage contrast method utilizing a charge up phenomenon based on the irradiation of an electron beam. The pattern was tested. As a result, the ratio of unopened contact hole pattern to acceptable contact hole pattern was 100 to 100 million. That is, the experimental results indicate that, according to the present embodiment, the incidence of defects in the contact hole patterns in which the fine contact plugs are formed is very low as in the case of the first embodiment. Thus, this embodiment significantly improves the defect incidence rate as compared with the case where no residue removal process is performed.

Now, a comparative example of this embodiment will be described. We formed a RELACS ^™ membrane with the residue removal process step omitted; This residue removal process step consists of a water dissolving step and a water washing step, corresponding to step 14 (S-14) of the flowchart of FIG. 6 and described above with reference to FIGS. 7A, 7B and 8A. That is, as in the case of the comparative example of the first embodiment described above, without removing the residue of the resist film left in the first hole pattern, the RELACS ^™ film is selectively grown and formed on the top surface and sidewall surfaces of the first resist pattern. It became. Thus, the diameter of the first hole pattern was reduced from about 45 nm to about 30 nm to form a second hole pattern.

Then, based on the second hole pattern formed in the above steps, the contact hole pattern in which the contact plug was formed was formed in the interlayer insulating film. The contact hole pattern was then tested for defective hole incidence using the voltage contrast method described above. As a result, the ratio of unopened contact hole pattern to acceptable contact hole pattern was about 10 to 10,000. The defect hole occurrence rate of this contact hole pattern is much higher than that according to the present invention described above, that is, about 100,000 times higher than that according to the present embodiment.

In addition, the inventors of the present invention examined the cross-sectional shape of the unopened second hole pattern and found that a residue of the resist film having a width of about 30 nm was formed in the unopened second hole pattern. The residue of this resist film interacts with the RELACS ™ material to grow the residue, thereby substantially filling the bottom of the second hole pattern substantially completely. As a result, the ratio of the defect hole pattern to the allowable hole pattern is about 10 to 10000. The mechanism of occurrence of such a defect is as described in the first embodiment and will not be described later.

As described above, the second embodiment can have an effect similar to that of the first embodiment described above. Unlike the first embodiment, in which the residue removal process is performed by the dry etching process, the present embodiment performs the residue removal process by the wet etching process. In general, the wet etching process has higher etching efficiency than the dry etching process and makes the construction of the etching apparatus simpler. Therefore, this embodiment is more efficient than the first embodiment and requires less manufacturing cost.

This embodiment uses EUV exposure as described above. However, the present invention is not limited to this aspect. As a result of the experiments of the present inventors, as in the case of the first embodiment, an exposure process using KrF chemical amplification resist instead of EUV chemical amplification resist 22 and KrF light instead of EUV light as an exposure light source is shown in this embodiment. By application, it is shown that effects similar to those described above can also be obtained. Similarly, in the present embodiment, it has been found that effects similar to those described above can be obtained even when an ArF exposure process or an exposure process using an I line from a mercury lamp is applied.

This embodiment performs a process of reducing the diameter of the first hole pattern 23a of about 45 nm to about 30 nm. However, the size of the first hole pattern 23a or the second hole pattern is not limited to this aspect. Similar to the first embodiment, this embodiment is of course also applicable to a process of reducing the width of a hole or space pattern to a size close to the critical resolution determined by, for example, an illumination condition and an NA condition for an exposure apparatus. Do. In addition, the amount of reduction (the amount by which the hole is narrowed) from the first hole pattern 23a to the second hole pattern is about 15 nm. However, this reduction amount is not limited to this aspect. As in the case of the first embodiment, an increase in the amount of reduction during the narrow space pattern forming process makes the applicability of the present embodiment more advantageous.

Further, even if the first pattern 23a, such as the space portion or the hole portion, does not need to be shrunk, in the case where the first space pattern 23a exhibits high defect occurrence after the formation of the resist pattern, the process is of course effectively applicable. . Furthermore, as in the case of the first embodiment, the application of this embodiment is not limited to the process of forming a fine spatial pattern at a size close to the limit of the resolution of the exposure apparatus. In this embodiment, for example, in the water dissolving process and the water washing process shown in the process 14 of FIG. 6 described above, the first resist pattern 23 (resist film 22) is dissolved in water or an aqueous solution, Applicable in the case of extending into one spatial pattern 23a, the present embodiment then adjusts the expanded first spatial pattern 23a. In this embodiment, the amount of the RELACS ™ film 28 corresponding to the expansion of the first spatial pattern 23a may be formed to narrow the first spatial pattern 23a. Therefore, even if a spatial pattern of normal size is formed using general ultraviolet light as the exposure light, the present embodiment can form the pattern in a desired shape while drastically lowering the defect occurrence rate.

In addition, as described above, in this embodiment, the process of forming the first resist pattern 23 that is easy to dissolve corresponds to the process of forming the first resist pattern 23 that is soluble in water. This embodiment is characterized in that water or an aqueous solution is used as an etchant for removing the residue 22a from inside the first hole pattern 23a. In order to allow the hydrophobic residue 22a to be removed using water or an aqueous solution, this embodiment forms a water-containing film 24 on the front surface of the hydrophobic first resist pattern 23 and the residue 22a. Next, the first resist pattern 23 is irradiated with ultraviolet light. Thus, hydroxyl radicals (OH radicals) are produced on the front surfaces of the first resist pattern 23 and the residue 22a, so that the front surfaces of the first resist pattern 23 and the residue 22a are combined with the hydroxyl radicals. Allow it to respond. This increases the number of hydroxyl groups on the front surface of the first resist pattern 23 and the residue 22a that reacted with the hydroxyl radicals. Accordingly, the hydrophobic first resist pattern 23 and the residue 22a exhibit high solubility in water or in aqueous solution.

However, this principle is not limited to the manner in which the front surface of the first resist pattern 23 allows water to be absorbed to form the moisture containing film 24. Similar effects can be obtained by allowing the front surfaces of the first resist pattern 23 and the residue 22a to absorb hydrogen peroxide, for example instead of water. When the front surfaces of the first resist pattern 23 and the residue 22a absorb hydrogen peroxide, the front surfaces of the first resist pattern 23 and the residue 22a have a wavelength of up to about 250 nm. It will be irradiated with light having a wavelength that can be absorbed by hydrogen peroxide. Thus, the pattern forming process can be implemented similarly to the process according to the present embodiment as described above. That is, the light emitted to the first resist pattern 23 and the residue 22a is not limited to the excimer ray described above. A pattern forming process similar to the process according to this embodiment described above uses light having a wavelength that can be absorbed by water or hydrogen peroxide absorbed on the front surface of the first resist pattern 23 and the residue 22a. Can be implemented.

Further, in order to remove the unwanted resist film (residue) 22a remaining in the first hole pattern (space portion) 23a after the formation of the resist pattern 23, the above-described method is performed on the resist pattern 23. The dissolution process is performed to form a resist film that can be easily dissolved in a liquid, and then the removal process is performed using the liquid. However, the application of this method is not limited to the process of reducing the spatial pattern after the removal process as in the case of this embodiment. The method used in this embodiment is, of course, also applicable to the process of removing the unwanted resist film remaining in the space portion where the process proceeds directly to the processing process. In this case, it is preferable that the space pattern for which the dissolution process has not yet been performed is narrowed in advance by the space width in which the resist pattern is expanded as a result of the dissolution process and the removal process.

(Third Embodiment)

Now, the pattern forming method according to the third embodiment of the present invention will be described with reference to FIGS. 10, 11A and 11B. Components in the third embodiment that are identical to those in the first and second embodiments are denoted by the same reference numerals and will not be described in detail. This embodiment is substantially similar to the first embodiment except for the process of removing residue from inside the hole pattern. The third embodiment will be described later in detail.

First, as shown in FIGS. 10 and 11A, as in the case of the processes 1 (S-1) to 6 (S-6) according to the first embodiment, the first hole pattern 5a having a diameter of about 100 nm. A first resist pattern 5 including is formed on the resist film 4 provided on the front surface 1a of the semiconductor substrate 1. Undesired resist film 4a remains in the first hole pattern as a residue.

Subsequently, as in the case of step 7 (S-7) of the first embodiment, the unwanted resist film 4a is removed from inside the first hole pattern 5a. However, unlike the first embodiment, this embodiment does not use anisotropic etching to remove the residue 22a. In this embodiment, first, as in the case of step 14 (S-14) according to the second embodiment, in order to remove the unwanted resist film 4a remaining in the first hole pattern 5a, a dissolution process Is performed on the resist pattern 5 so that the resist film 4 is easily dissolved in the liquid. Subsequently, the removal liquid is used to perform the process of removing the unwanted resist film 4a. However, unlike the second embodiment, this embodiment performs a process of removing the unwanted resist film 4a by using an alkaline solution instead of water. This embodiment will be described below in more detail.

First, a dissolution process is performed on the entire first resist pattern 5 and the residue 4a of the resist film 4 so that the front surface of the resist film 4 is easily dissolved in the alkaline solution. Although not shown, the front surfaces of the resist film 4 and the first resist pattern 5 forming the residue 4a are entirely irradiated with ArF light having a wavelength of 193 nm. Thus, as shown in FIG. 11A, an acid is generated on the entire residue 4a composed of the resist film 4 and on the front surface layer portion of the first resist pattern 5, so that the first resist pattern 5 is formed. The front surface layer part and the entire residue 4a of the first layer part are changed into an easily soluble film 31 which can be easily dissolved in the alkaline solution. In this case, when the residue 4a is removed using an alkaline solution having a pH value of about 12 as the corrosion solution, the amount of ArF light is dissolved by about 5 nm by dissolving the front surface layer portion of the resist film 4. It is set to satisfy the condition for generating dishing.

Next, as shown in FIGS. 10 and 11B, the inside of the first hole pattern 5a has a pH of about 12 generated by diluting a tetramethyl ammonium hydroxide (TMAH) developer with pure water as a washing solution. It is washed with an alkaline solution having a value. Residues 31 (4a) remaining in the first hole pattern 5a as resist defects were already exposed during patterning. Thus, the residues 31 and 4a can be more dissolved in an alkaline solution having a pH value of about 12 than the resist pattern portion (resist film 4) not exposed during patterning. As a result, even with a size of about 20 nm, the residues 31 and 4a can be substantially completely removed from inside the first hole pattern 5a. However, the front surface layer portion of the resist film 4 is dissolved in an alkaline solution by about 5 nm to generate dishing. The above-mentioned dissolution process (light irradiation process) and washing process are shown as process 21 (S-21) in the flowchart of FIG.

Subsequently, although not shown, as in the case of processes 8 (S-8) to 10 (S-10) according to the first embodiment, the RELACS ™ film 7 has a bottom surface of the first hole pattern 5a. It is selectively formed over the edge of and over the inner surface of the first hole pattern 5a. As a result, a second hole pattern 8a having a diameter of about 80 nm is formed. After the process of forming the second hole pattern 8a is completed, the inventors of the present invention perform defect inspection using a DUV optical defect inspection apparatus having a resolution of about 60 nm, as in the case of the first embodiment. Then, the ratio of the unopened second hole pattern 8a to the acceptable second hole pattern 8a is about 1 to 100,000,000 as in the case of the first embodiment. Thereby, the main process of the pattern formation method which concerns on a present Example is completed.

Then, although not shown, a process similar to the process described in the first embodiment with reference to FIGS. 4B and 5A to 5C is performed to coat the barrier metal film on the side and bottom surfaces inside the interlayer insulating film 2. Fine contact plugs 12 having a diameter of about 80 nm are formed. As a result, the main process of the electronic device manufacturing method according to the present embodiment is completed.

As described above, the third embodiment can exert effects similar to those of the first and second embodiments described above. In addition, if the material 6 of the RELACS ™ film 7 is an aqueous alkaline solution having a pH value of about 12, the process of removing the residue 4a may be combined with the process of forming the RELACS ™ film 7. . This will be described later in the fifth embodiment. The pH value of the wash (corrosive) does not necessarily need to be set to about 12. The pH value of the washing liquid can be appropriately changed so that the residue 4a can be properly removed depending on the size of the residue 4a and the like.

This embodiment performs a process of reducing the diameter of the first hole pattern 5a from about 100 nm to about 80 nm. However, the size of the first hole pattern 5a and the second hole pattern 8a is not limited to this aspect. Like the first embodiment, this embodiment is of course also applicable to the process of reducing the width of the hole or spatial pattern to a size close to the critical resolution determined by, for example, the illumination condition and the NA condition for the exposure apparatus. Further, in this embodiment, the amount of reduction from the first hole pattern 5a to the second hole pattern 8a is about 20 nm (about 30 nm after the alkali cleaning process), as in the case of the first embodiment. . However, this reduction amount is not limited to this aspect. As in the case of the first embodiment, an increase in the amount of reduction during the narrow space pattern forming process makes the applicability of the present embodiment more advantageous.

As described above, in the present embodiment, the process of forming the front surface layer portion of the first resist pattern 5 which is easy to dissolve generates acid on the front surface layer portion of the first resist pattern 5, thereby producing the acid. Corresponds to the process in which the front surface layer portion is readily soluble in alkaline solution. This embodiment is characterized in that an alkaline solution is used as a washing liquid (corrosion liquid) for removing the residue 4a in the first hole pattern 5a. In addition, in order to generate an acid on the front surface layer portion of the first resist pattern 5, the present embodiment irradiates the front surface of the resist film 4 with light in which the resist film 4 has a sensitive wavelength. . The intensity of the light emitted on the front surface is sufficient when the residue 4a (resist defect) remaining in the first hole pattern 5a can be dissolved by this light, and the first resist pattern (such as dishing) It is preferable that the deterioration of 5) be set so as to fall within an acceptable range.

In addition, the alkaline washing solution is not limited to the dilute solution of the TMAH developer described above. A similar effect to this example can be obtained by using an organic alkaline solution such as choline or an inorganic alkaline solution such as KOH as a washing solution instead of a dilute solution of the TMAH developer. That is, any variety of solutions in which the concentration and pH value of the solution are set to dissolve the residue 4a of the resist film 4 without substantially dissolving the resist film 4 forming the first resist pattern 5. Type alkaline solutions can be used as washing liquid.

(Example 4)

Now, the pattern forming method according to the fourth embodiment of the present invention will be described with reference to FIGS. 12 and 13. Elements of the fourth embodiment that are identical to those of the first to third embodiments are denoted by the same reference numerals and will not be described in detail. This example is substantially similar to the second example except that an aqueous solution comprising RELACS ^™ material is used as a wash (corrosive) to remove residue. The fourth embodiment will be described in more detail below.

First, as shown in FIGS. 12 and 13, the first resist pattern 23 including the first hole pattern 23a having a diameter of about 45 nm is formed in step 1 (S-1) according to the first embodiment. ) Is formed on the resist film 22 provided on the front surface 1a of the semiconductor substrate 1 as in step 6 (S-6). Although not shown in the figure, the unnecessary resist film 22a remains as a residue inside the first hole pattern 23a.

Then, although not shown in the figure, a dissolution process (water dissolution process) is performed on the entire residue 22 and the front surface layer portion of the first resist pattern 23 so that the front surface of the resist film 22 is RELACS ^™. It is easy to dissolve in an aqueous solution containing the membrane (7). In this case, the front surface of the resist film 22, FIG. 6, 7a and see 7b in the as described in the second embodiment, RELACS by water dissolution processes comprising the adsorption process and the emission process ^TM material (6 It can be made easy to melt | dissolve in the aqueous solution 26 containing). This is shown in step 31 (S-31) of the flowchart of FIG.

Then, as shown in Figs. 12 and 13, a step similar to step 8 (S-8) according to the second embodiment is performed to dissolve the water dissolved in the water of the first resist pattern 23 (resist film 22). An aqueous solution comprising RELACS ^™ material 6 is provided on the surface and inside the first hole pattern 23a. Thus, the residue 22a dissolved in water in the first hole pattern 23a is dissolved in the aqueous solution 26 and washed (etched).

Thereafter, although not shown in the figure, as in the case of steps 9 (S-9) and 10 (S-10) according to the second embodiment, the aqueous solution 26 not formed of the RELACS ^TM film is formed in the first hole. It is removed from the inside of the pattern 23a and from the front surface of the first resist pattern 23. At this time, the residue 22a dissolved in the aqueous solution is removed from the inside of the first hole pattern 23a together with the aqueous solution 26 which is not formed of the RELACS ^™ film 28. Thus, as in the second embodiment, the RELACS ^™ film 28 is selectively left over the edge of the bottom surface of the first hole pattern 23a and the inner surface of the first hole pattern 23a so that it is about 30 nm. A second hole pattern of diameter is formed. The main step of the pattern forming method according to the present embodiment is thus completed.

Thereafter, although not shown in the figures, steps similar to those described in the first embodiment with reference to FIGS. 4B and 5A-5C are performed to coat the barrier metal film on the side and bottom surfaces inside the interlayer insulating film 2. And form a fine contact plug 12 having a diameter of about 30 nm. Thus, the main steps of the manufacturing method of the electronic device according to the present embodiment are completed.

As described above, the fourth embodiment can produce effects similar to those of the first to third embodiments. In addition, an aqueous solution 26 comprising RELACS ^™ material 6 may be used as the cleaning liquid for removing the residue 22a from the inside of the first hole pattern 23a. Therefore, this embodiment can reduce the number of pattern forming steps and electronic device manufacturing steps necessary for simplicity, in comparison with the second embodiment. This makes it possible to increase the efficiency in the pattern forming step and the electronic device manufacturing step and further reduce the cost of the pattern forming step and the electronic device manufacturing step.

(Example 5)

Now, a pattern forming method according to the fifth embodiment of the present invention will be described with reference to FIGS. 14, 15A and 15B. The same components as those of the first to third embodiments are denoted by the same reference numerals and will not be described in detail. This example is substantially the same as the third example except that an alkaline solution comprising a RELACS ^™ material is used as a wash (corrosive) to remove residues. The fifth embodiment will be described in detail below.

First, as shown in FIGS. 14 and 15A, the first resist pattern 5 including the first hole pattern 5a having a diameter of about 100 nm is obtained by step 1 (S-1) according to the third embodiment. ), As in the case of Step 6 (S-6), is formed on the resist film 4 provided on the front surface 1a of the semiconductor substrate 1. Although not shown in the figure, an unnecessary resist film 4a remains as a residue inside the first hole pattern 5a.

Subsequently, a dissolution process (water dissolution process) is performed on the entire residue 4a and the front surface layer portion of the first resist pattern 5 so that the front surface of the resist film 4 includes an alkaline solution containing RELACS ^™ material 6. It is easy to dissolve in (41). In this case, by performing the dissolution process consisting of the light emitting process as described in the third embodiment with reference to FIGS. 10 and 11A, the front surface of the resist film 4 is subjected to the alkaline solution containing the RELACS ^™ material 6. Make it easy to dissolve. This is shown in step 41 (S-41) of the flowchart of FIG.

Thereafter, as shown in Figs. 14 and 15A, as in step 8 (S-8) of the third embodiment, an alkaline solution comprising RELACS ^™ material 6 is dissolved in the front of the first resist pattern 5. It is provided on the surface (resist film 4) and inside the first hole pattern 5a. Thus, the dissolved residues 31 and 4a in the first hole pattern 23a are dissolved in the aqueous solution 26 and washed (etched).

Thereafter, although not shown in the figure, as in the case of Step 9 (S-9) and Step 10 (S-10) according to the third embodiment, an alkali solution 41 not formed in the RELACS ^TM film 7 is provided. The inside of the first hole pattern 5a and the front surface of the first resist pattern 5 are removed. At this time, the residue 31 dissolved in the alkaline solution 41 is removed inside the first hole pattern 5a together with the alkaline solution 26 which is not formed in the RELACS ^™ film 7. Thus, as in the third embodiment, the RELACS ^™ film 7 is selectively left on the edge of the bottom surface of the first hole pattern 5a and on the inner surface of the first hole pattern 5a to be about 80 nm. To form a second hole pattern having a diameter. The main step of the pattern forming method according to the present embodiment is thus completed.

Thereafter, although not shown in the figures, a similar step to that described in the first embodiment with reference to FIGS. 4B, 5A to 5C is performed, so that about 80 nm inside the interlayer insulating film 2, on the side and bottom surfaces thereof. The fine contact plug 12 coated with a barrier metal film having a diameter of 9 is formed. The main steps of the electronic device manufacturing method according to the present embodiment are thus completed.

As described above, the fifth embodiment can obtain effects similar to those in the first to fourth embodiments. In addition, the alkaline solution 41 including the RELACS ^™ material 6 may also be used as a cleaning liquid for removing the residues 31 and 4a from inside the first hole pattern 5a. As described above, the present embodiment can reduce the number of pattern forming steps and electronic device manufacturing steps necessary for simplicity when compared with the third embodiment. This makes it possible to increase the efficiency of the pattern forming step and the electronic device manufacturing step and further reduce the cost in the pattern forming step and the electronic device manufacturing step.

(Example 6)

Now, a sixth embodiment of the present invention will be described with reference to FIGS. 16, 17a, 17b, 18a, 18b, 19a, 19b and 20. FIG.

The sixth embodiment corresponds to the manufacturing steps according to the first to fifth embodiments described above, wherein the width (space upper dimension) of the bottom space of the resist pattern (reference pattern) is the width (space bottom dimension) of the top of the resist pattern. Significantly smaller than), indicating the possibility that the resist pattern will not open, and the pattern is corrected such that the width of the bottom space of the resist pattern is close to the width of the top space of the resist pattern.

For a micropattern having a size close to the critical resolution, as shown in FIG. 17A, if not, a resist pattern 52 opened on the process target film 51 may be formed (for example, by exposure or baking temperature). Due to slight variations in the lithography process, such as changes, or changes in cleaning conditions during development, may be a footing condition as shown in FIG. 18A or a half-opening condition as shown in FIG. 19A. There will be. In this condition, the above-described RELACS or 2300MOTIF is applied to form the deposition film 53, the space deposition film is removed as shown in FIG. 17B, and the pattern may not be opened as shown in FIGS. 18B and 19B. will be.

Thus, when the resist pattern is not opened, after the resist pattern is formed as described above, the pattern is corrected so that the bottom space width approaches the upper space width.

Now, pattern correction will be described in more detail.

20 shows a process flow according to the sixth embodiment. First, a process target substrate is prepared. Thereafter, a resist film is formed on the process target film of the substrate. A hole pattern in which interconnect vias of 100 nm in diameter are formed is formed by exposure and development (step S-51). The inventors observed the entire front surface of the substrate from above with respect to the pattern shape using the SEM (S-52) and found that the width of the bottom space of some patterns was very small.

Therefore, the substrate is transferred to the vacuum chamber (S-53). Oxygen gas flows into the vacuum chamber to form an oxygen plasma for anisotropic etching (S-54). The resist remaining at the bottom of the pattern is mainly due to inadequate cleaning during development. The remaining resist is a resist pattern, i.e., a film having more voids than the reference pattern. Thus, by optimizing the control factors including the anisotropy of the accelerating voltage, the electric field, the magnetic field, and the processing speed, the bottom space width can be made substantially equal to the upper space width while maintaining the pattern shape substantially.

Thereafter, the gas type in the same chamber in which the substrate is placed is exchanged with the fluorinated carbon gas containing CF ₄ (S-55). The treatment is performed under the condition that the fluorinated carbon is decomposed and deposited on the resist pattern, thereby forming a deposited film of carbon fluoride on the front surface of the resist pattern (S-56). The gas species is then exchanged for coral and carbon fluoride (eg, C ₄ F ₆ containing gas) (S-57). The deposition film in the reference pattern space portion is further etched to expose the process target film (S-58).

Subsequently, the substrate is transported out of the vacuum chamber (S-59). The newly formed pattern has a diameter of 75 nm, which is 25 nm smaller than the original pattern. The process target film is etched using the new pattern as a mask (S-60). Thereafter, metal is deposited on the process target film (S-61). Excess metal is removed by CMP (S-62). Interconnect vias are formed (S-63).

According to the above-described manufacturing method, when the width of the bottom space of the resist pattern is considerably smaller than the width of the top space of the resist pattern, it indicates the possibility that the resist pattern is not opened, and the width of the bottom space of the resist pattern is the top of the resist pattern. The pattern is corrected to approximate the width of the space. This enables a significant reduction in the number of defects, i.e., unopened patterns, when compared to the case where the present invention is not used. The inventors have confirmed through defect inspection that the number of defects, i.e., unopened patterns, can be reduced by up to 1/10.

In this example, formation of fine vias is illustrated. However, this embodiment is also applicable to the formation of fine buried interconnect (microglobe) patterns. In addition, the present embodiment is also applicable to pattern types having a size close to the critical resolution and difficult to provide sufficient process margin, thereby improving the miniaturization of the pattern having a size providing sufficient margin for resolution, and improving manufacturing yield. Let's do it.

In addition, microholes equivalent to those described above can be formed by the following steps. The hard mask is preformed under the resist film. The resist is patterned and the substrate is transferred to a vacuum chamber. The lower width of the resist is subjected to an opening process and the hard mask is processed. Thereafter, a deposited film is formed on the hard mask pattern using carbon fluoride. The deposition film is removed from the recessed portion of the hard mask. Process target masks are also processed.

As described above, the pattern forming method according to the sixth embodiment of the present invention increases the width of the bottom space of the reference pattern by preparing the process target substrate, and the width of the bottom space of the reference pattern to the width of the top space of the reference pattern. A bottom space width increasing step and a sidewall film increasing step of adjoining. The sidewall film increasing step includes depositing a deposited film on the front surface of the reference pattern, and removing a deposited film on the bottom space of the reference pattern by anisotropic etching to expose a portion of the floor space that is narrower than the bottom space of the reference pattern. It includes.

Preferably, the sidewall film increasing step is performed a plurality of times. In addition, the anisotropic etching is preferably controlled so that the deposition film is formed on the front surface of the reference pattern so that the etching rate for the deposition film on the bottom space of the reference pattern is higher than the etching rate for the deposition film on the sidewall portion of the reference pattern. .

In the case where the reference pattern needs to prevent reflection, an antireflection film is formed on the process target film, and a resist film is formed on the antireflection film. Thereafter, an exposure apparatus is used to form a latent image on the resist in an exposure disc or beam scanning unit. If necessary, amplifying a latent image such as heating is performed. In addition, a developing step and a cleaning step are performed to generate a pattern.

Alternatively, the reference pattern may be formed of an oxide film, a nitride film or an organic film having a high carbon content obtained by treating the process target film by the above-described resist pattern as a mark.

When the pattern is lowered due to changes in process conditions or the like with respect to the opening of the bottom space width, a possible cause is low intensity exposure light or insufficient reaction despite the exposure of the opening. Therefore, the correction is performed such that the etching selectivity is appropriately set by balancing the gas conditions or by changing the acceleration voltage, thereby increasing the bottom space width. If the object is a resist, the calibration can be performed by changing the activity of the alkaline solution (eg by changing the concentration of the alkaline solution or adding functional water). In the case where the object is an oxide film, the correction may be performed by increasing the bottom space width by using fluoric acid or the like to change the concentration of the alkaline solution.

The sixth embodiment can provide a method of manufacturing a semiconductor device in which fine vias or trenches are formed on a processing target substrate using fine holes or grooves formed by a pattern forming method.

The sixth embodiment can also provide a method of manufacturing a semiconductor device for forming fine interconnections using sidewall deposited film patterns formed by a pattern forming method.

The pattern forming method according to the present invention is not limited to the first to sixth embodiments described above. For example, the first to sixth embodiments are performed using the RELACS ^™ material disclosed in the web feature article “Semiconductor 0.1-μm hole pattern forming technique RELACS” provided by Mitsubishi Electric Corporation. However, RELACS ^™ materials need not necessarily be used. According to the experimental results of the present inventors, for example, a conventional coating film which does not interact with the resist pattern may be used in place of the RELACS ^™ material. A coating film is provided in the first hole pattern 5a or 23a and the first resist pattern 5 or 23 is heated so that the coating film is embedded in the resist, thereby enabling a reduction in the diameter of the first hole pattern 5a or 23a. do. In addition, the experimental results show that this technique shows an effect similar to that of the first to sixth embodiments.

Further, in the description of the first to sixth embodiments, the technique according to these embodiments is a first hole having a size close to the critical resolution of the exposure apparatus, such as the space portion 5 or 23a of the first resist pattern 5 or 23. The pattern 5a or 23a is formed. However, the present invention is not limited to this aspect. The experimental results of the present inventors show that the technique according to the first to sixth embodiments is applied by applying the present technology to reduce the space width of the spatial pattern formed under the usual design rule, and to form the interconnect material by filling the interlayer insulating film. Applicable to the pattern as well, in which case the defect density of the interconnect pattern is significantly reduced.

In addition, the diameter of the first hole pattern 5a or 23a and the diameter of the second hole pattern 8a to which the pattern forming method according to the embodiment of the present invention affects are not limited to the above-described dimensions. The pattern forming method according to the present invention can achieve an effect similar to the above-described effect, for example, on the assumption that the dimension of the diameter of the hole pattern to be formed is at most about 100 nm. Also, similar effects to those described above can be obtained, for example, on the assumption that the hole pattern to be formed has an aspect ratio of at least one. Alternatively, the pattern forming method according to the embodiment of the present invention, for example, on the assumption that the spatial pattern of the line-and-space pattern to be formed is formed to have a width of up to about 50 nm A similar effect can be obtained. In addition, the pattern forming method according to the embodiment of the present invention can achieve an effect similar to that described above, on the assumption that the spatial pattern of the L / S pattern to be formed, for example, has an aspect ratio of at least 2.

As described above, according to one aspect of the present invention, a pattern forming method for allowing a fine pattern to be formed may be provided.

Additional advantages and modifications will be readily apparent to those skilled in the art. Accordingly, the invention in its broader aspects is not limited to the details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the invention as defined by the claims and their equivalents.

1 is a flowchart showing a pattern forming method according to a first embodiment of the present invention.

Fig. 2A is a sectional view showing the first step of the pattern forming method according to the first embodiment of the present invention.

Fig. 2B is a sectional view showing the second step of the pattern forming method according to the first embodiment of the present invention.

3A is a sectional view showing a third step of the pattern forming method according to the first embodiment of the present invention.

Fig. 3B is a sectional view showing the fourth step of the pattern forming method according to the first embodiment of the present invention.

4A is a sectional view showing a fifth step of the pattern forming method according to the first embodiment of the present invention.

Fig. 4B is a sectional view showing the sixth step of the pattern forming method according to the first embodiment of the present invention.

Fig. 5A is a sectional view showing a first step of the method for manufacturing an electronic device according to the first embodiment of the present invention.

5B is a sectional view showing a second step of the method for manufacturing an electronic device according to the first embodiment of the present invention;

Fig. 5C is a sectional view showing a third step of the method for manufacturing an electronic device according to the first embodiment of the present invention.

6 is a flowchart showing a pattern forming method according to the second embodiment of the present invention.

Fig. 7A is a sectional view showing a first step of the pattern forming method according to the second embodiment of the present invention.

7B is a sectional view showing a second step of the pattern forming method according to the second embodiment of the present invention.

8A is a sectional view showing a third step of the pattern forming method according to the second embodiment of the present invention;

8B is a sectional view showing a fourth step of the pattern forming method according to the second embodiment of the present invention;

Fig. 9A is a sectional view showing a fifth step of the pattern forming method according to the second embodiment of the present invention.

Fig. 9B is a sectional view showing the sixth step of the pattern forming method according to the second embodiment of the present invention.

Fig. 10 is a flowchart showing a pattern forming method according to the third embodiment of the present invention.

Fig. 11A is a sectional view showing the first step of the pattern forming method according to the third embodiment of the present invention.

Fig. 11B is a sectional view showing the second step of the pattern forming method according to the third embodiment of the present invention.

12 is a flowchart showing a pattern forming method according to the fourth embodiment of the present invention.

Fig. 13 is a stage view showing steps of the pattern forming method according to the fourth embodiment of the present invention.

Fig. 14 is a flowchart showing a pattern forming method according to the fifth embodiment of the present invention.

Fig. 15A is a sectional view showing a step of the pattern forming method according to the fifth embodiment of the present invention.

Fig. 15B is a sectional view showing a step of the pattern forming method according to the fifth embodiment of the present invention.

16 is a cross-sectional view showing pattern correction in the pattern formation method according to the sixth embodiment of the present invention.

17A is a cross sectional view showing a pattern formation method according to a sixth embodiment of the present invention, showing that the opening pattern is normal;

Fig. 17B is a cross sectional view showing a pattern forming method according to a sixth embodiment of the present invention, showing that the open pattern is normal and a normal pattern is formed.

FIG. 18A illustrates a pattern forming method according to a sixth embodiment of the present invention, showing that the open pattern is in a footing condition; FIG.

18B illustrates a pattern formation method according to a sixth embodiment of the present invention, showing that an open pattern is in a putting condition and therefore that the pattern is open;

Fig. 19A is a cross sectional view showing a pattern formation method according to a sixth embodiment of the present invention, showing that the opening pattern is half-open;

Fig. 19B is a sectional view showing a pattern forming method according to the sixth embodiment of the present invention, showing that the open pattern is half open and therefore the pattern is unopened.

Fig. 20 is a flowchart showing a pattern forming method according to the sixth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: semiconductor substrate

2: interlayer insulation film

3: antireflection film

4: resist film

4a: residue

5: resist pattern

6: hole pattern

Claims (20)

As a pattern formation method, Patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; And Forming a moisture containing film on the front surface of the process target substrate in the space portion of the resist pattern, irradiating light to the moisture containing film, and supplying liquid containing moisture to the moisture containing film; Pattern forming method comprising a. The method of claim 1, And the process target film comprises a semiconductor substrate, an interlayer insulating film formed on one main surface of the semiconductor substrate, and an antireflection film formed on the interlayer insulating film. The method of claim 1, And the process target film comprises a semiconductor substrate, an interlayer insulating film formed on one main surface of the semiconductor substrate, and a hard mask layer formed on the interlayer insulating film. The method of claim 1, The resist pattern forming step includes forming a resist film on the process target substrate, exposing the resist film to form a latent image, and forming a hole pattern in the resist film. The method of claim 4, wherein And removing a residue remaining in the hole pattern. The method of claim 5, Removing the residue comprises: performing a dissolution process on the resist pattern so that the resist film is readily soluble in a liquid for removing residue remaining in the hole pattern and using the liquid And performing a removal process. The method of claim 1, Irradiating the water-containing film with light and providing the water-containing liquid to the water-containing film comprises changing the front layer portion of the resist pattern to a hydrophilicized layer. The method of claim 7, wherein The wavelength of the light is 200 nm or less, and the moisture absorbed in the resist pattern is radicalized to add hydroxyl groups to the front surface of the resist pattern. The method of claim 1, After forming the resist pattern, if the bottom dimension of the space portion of the resist pattern is smaller than the top dimension of the space portion, correcting the pattern to make the bottom space width close to the top space width. . The method of claim 9, Correcting the pattern includes increasing the bottom space width such that the bottom space width is close to the top space width, and increasing the film thickness of the sidewalls, Increasing the film thickness of the sidewalls includes forming a deposited film on the front surface of the resist pattern, followed by forming the deposited film, and then removing the deposited film from the front surface of the bottom space of the resist pattern by anisotropic etching. Exposing a portion of the floor space that is narrower than the floor space. As a pattern formation method, Patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; Performing a dissolution process on the resist film remaining in the space portion of the resist pattern; Supplying a liquid for removing the resist film to remove the resist film remaining in the space portion of the resist pattern; Introducing a material for the pattern forming complementary film formed in the film through interaction with the resist film, into the space portion of the resist pattern; Selectively forming a pattern forming complementary film on an inner surface of the space portion by causing a material for the pattern forming complementary film to interact with the resist film; And Removing a portion of the pattern forming complementary material which is not formed in the film from the inside of the space part, while exposing the remaining portion of the pattern forming complementary film to the space part, exposing a part of the bottom surface of the space part. Pattern forming method comprising a. The method of claim 11, And the interaction between the pattern forming complementary film material and the resist film includes performing a baking process to form a crosslinked mixed layer between the resist film and the pattern forming complementary film material. The method of claim 11, After partially exposing the bottom surface of the space portion, processing the process target substrate using the resist pattern and the remaining portions of the pattern forming complementary film as masks. The method of claim 11, After forming the resist pattern, if the bottom dimension of the space portion of the resist pattern is smaller than the top dimension of the space portion, correcting the pattern to make the bottom space width close to the top space width. . The method of claim 14, Correcting the pattern includes increasing the bottom space width such that the bottom space width is close to the top space width, and increasing the film thickness of the sidewalls, Increasing the film thickness of the sidewalls includes forming a deposited film on the front surface of the resist pattern, followed by forming the deposited film, and then removing the deposited film from the front surface of the bottom space of the resist pattern by anisotropic etching. Exposing a portion of the floor space that is narrower than the floor space. As a pattern formation method, Patterning a resist film provided on one main surface of the process target substrate to form a resist pattern; Performing a dissolution process on the resist film remaining in the space portion of the resist pattern; Supplying a liquid for removing the resist film, the liquid comprising a pattern forming complementary material formed into a film through interaction with the resist film; Selectively forming the pattern forming complementary film on the inner surface of the space portion by causing the pattern forming complementary material to interact with the resist film; And Removing the portion of the pattern forming complementary material which is not formed in the film from the inside of the space portion, while exposing the remaining portion of the pattern forming complementary film to the space portion, thereby exposing a portion of the bottom portion of the space portion. step Pattern forming method comprising a. The method of claim 16, And the interaction between the pattern forming complementary film material and the resist film comprises baking to form a crosslinked mixed layer between the resist film and the pattern forming complementary film material. The method of claim 16, After partially exposing the bottom surface of the space portion, processing the process target substrate using the resist pattern and the remaining portions of the pattern forming complementary film as masks. The method of claim 16, After forming the resist pattern, if the bottom dimension of the space portion of the resist pattern is smaller than the top dimension of the space portion, correcting the pattern to make the bottom space width close to the top space width. . The method of claim 19, Correcting the pattern includes increasing the bottom space width such that the bottom space width is close to the top space width, and increasing the film thickness of the sidewalls, Increasing the film thickness of the sidewalls may be achieved by forming a deposited film on the front surface of the resist pattern, followed by forming the deposited film, and then removing the deposited film from the front surface of the bottom space of the resist pattern by anisotropic etching. Exposing a portion of the floor space that is narrower than an existing floor space.

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