KR100691934B1 - method for forming contact hole semiconductor device - Google Patents

method for forming contact hole semiconductor device Download PDF

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KR100691934B1
KR100691934B1 KR1020000079625A KR20000079625A KR100691934B1 KR 100691934 B1 KR100691934 B1 KR 100691934B1 KR 1020000079625 A KR1020000079625 A KR 1020000079625A KR 20000079625 A KR20000079625 A KR 20000079625A KR 100691934 B1 KR100691934 B1 KR 100691934B1
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contact hole
insulating film
forming
semiconductor device
film
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KR1020000079625A
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Korean (ko)
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KR20020050474A (en
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이동호
김연수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

Abstract

본 발명은 콘택홀을 형성한 후 폴리머성 잔류물을 제거하여 소자의 불량을 방지함으로서 소자의 수율을 향상시키도록 한 반도체 소자의 콘택홀 형성방법에 관한 것으로서, 반도체 기판 상에 절연막을 형성하는 단계, 상기 절연막 상에 감광막을 도포한 후 패터닝하여 콘택 영역을 정의하는 단계, 상기 패터닝된 감광막을 마스크로 이용하여 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계, 상기 감광막을 제거하는 단계, 상기 절연막의 표면 및 콘택홀 내부에 자외선을 조사하여 소수성인 상기 절연막 및 콘택홀의 내벽을 친수성으로 변화시키는 단계 및 상기 반도체 기판에 세정 공정을 실시하여 폴리머성 잔류물을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for forming a contact hole of a semiconductor device to improve the yield of the device by preventing the defect of the device by removing the polymer residue after forming the contact hole, forming an insulating film on the semiconductor substrate And forming a contact hole by applying a photoresist film on the insulating film and patterning the patterned contact layer, selectively removing the insulating film using the patterned photoresist film as a mask, and removing the photoresist film. Irradiating the surface of the insulating film and the inside of the contact hole with ultraviolet rays to change the hydrophobic inner walls of the insulating film and the contact hole to be hydrophilic; and performing a cleaning process on the semiconductor substrate to remove polymeric residues. do.

콘택홀, 폴리머, 인(P)이온, UV 램프Contact Hole, Polymer, Phosphorus Ion, UV Lamp

Description

반도체 소자의 콘택홀 형성방법{method for forming contact hole semiconductor device}Method for forming contact hole semiconductor device

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도1A through 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 산화막21 semiconductor substrate 22 oxide film

23 : 감광막 24 : 콘택홀23: photosensitive film 24: contact hole

25 : 잔류물25 residue

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 소자의 수율(yield)을 향상시키는데 적당한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device suitable for improving the yield of the device.

일반적으로 반도체 장치 제조 공정에서는 소자와 소자간을 연결시키거나 패드(Pad)의 연결 등을 위해서 게이트 전극 상부 및 소오스/드레인 영역 상부 등에 사진 식각 공정에 의해서 콘택홀(Contact hole)을 형성하고 있다.In general, in the semiconductor device manufacturing process, contact holes are formed in the upper part of the gate electrode and the upper part of the source / drain region by a photolithography process in order to connect the elements with the elements or to connect the pads.

또한, 반도체 장치가 고집적화, 소형화됨에 따라 단위 셀들이 적층되는 다층구조를 선택함에 따라 다층구조 상의 하부전극과 상부전극을 연결시키기 위하여, 내부회로와 외부회로를 연결시키기 위하여 사진 식각 공정에 의해서 콘택홀을 형성하고 있다.In addition, as a semiconductor device is highly integrated and miniaturized, a contact hole is formed by a photolithography process in order to connect an internal circuit and an external circuit in order to connect a lower electrode and an upper electrode on the multilayer structure as a multilayer structure in which unit cells are stacked. To form.

그런데, 상기 사진 식각 공정에 의해서 콘택홀이 형성됨에 따라 식각된 영역과 외부의 산소(O2)성분이 화학반응을 일으켜 콘택홀 저면에 자연 산화막을 형성시켰다. However, as the contact hole was formed by the photolithography process, the etched region and the external oxygen (O 2 ) component caused a chemical reaction to form a natural oxide film on the bottom of the contact hole.

상기 자연 산화막은 후속되는 반도체장치 제조 공정에 의해서 완성된 반도체 장치를 동작시킬 때, 반도체 장치의 전기적 특성을 저하시키는 원인으로 작용한다.The natural oxide film acts as a cause of lowering the electrical characteristics of the semiconductor device when operating the semiconductor device completed by a subsequent semiconductor device manufacturing process.

그리고, 일반적으로 상기 식각 공정은 이방성 식각 특성이 우수한 반응가스를 이용한 건식 식각 공정을 이용함에 따라 상기 포토레지스트 패턴의 탄소(C)성분과 반응가스가 반응하여 폴리머(Polymer)를 발생하였다. In general, as the etching process uses a dry etching process using a reaction gas having excellent anisotropic etching characteristics, the carbon (C) component of the photoresist pattern reacts with the reaction gas to generate a polymer.

상기 폴리머는 콘택홀 측벽에 흡착되어 완성된 반도체 장치를 동작시킬 때, 반도체 장치의 전기적 특성을 저하시키는 원인으로 작용한다.The polymer acts as a cause of lowering the electrical characteristics of the semiconductor device when the semiconductor device is adsorbed on the contact hole sidewalls to operate the completed semiconductor device.

이에 따라, 상기 자연 산화막 및 폴리머 등의 불순물을 제거하기 위하여 콘택홀을 형성한 후에 세정(cleaning)하였다.Accordingly, in order to remove impurities such as the natural oxide film and the polymer, a contact hole was formed and then cleaned.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택홀 형성방법을 설명하면 다음과 같다. Hereinafter, a method for forming a contact hole in a conventional semiconductor device will be described with reference to the accompanying drawings.                         

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 1a에 도시한 바와 같이, 반도체 기판(11)상에 산화막(12)을 형성하고, 상기 산화막(12)상에 감광막(13)을 도포한 후, 노광 및 현상공정으로 감광막(13)을 패터닝하여 콘택 영역을 정의한다.As shown in FIG. 1A, an oxide film 12 is formed on a semiconductor substrate 11, a photosensitive film 13 is coated on the oxide film 12, and then the photosensitive film 13 is patterned by an exposure and development process. To define the contact area.

도 1b에 도시한 바와 같이, 상기 패터닝된 감광막(13)을 마스크로 이용하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 산화막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.As shown in FIG. 1B, by using the patterned photoresist 13 as a mask, the oxide layer 12 is selectively removed to expose a predetermined portion of the surface of the semiconductor substrate 11 to form a contact hole 14. do.

도 1c에 도시한 바와 같이, 상기 감광막(13)을 제거하고, BN 세정 또는 NF 세정 등으로 세정공정을 실시하여 상기 콘택홀(14) 주위의 자연 산화막 및 폴리머(polymer) 등을 제거한다.As shown in FIG. 1C, the photoresist layer 13 is removed, and a natural oxide film, a polymer, and the like around the contact hole 14 are removed by a cleaning process such as BN cleaning or NF cleaning.

여기서 상기 감광막(13)을 제거할 때 산화막(12)의 표면 및 콘택홀(14)의 내부에는 폴리머성의 잔류물(15)이 잔류되는데, 이와 같은 잔류물(15)은 산화막(12)의 표면이 소수성이기 때문에 이후 실시되는 BN 세정 및 NF 세정 공정에 의해서도 쉽게 제거되지 않는다. Here, when the photoresist film 13 is removed, a polymer residue 15 remains on the surface of the oxide film 12 and inside the contact hole 14, and the residue 15 is formed on the surface of the oxide film 12. Since it is hydrophobic, it is not easy to remove even by the following BN washing | cleaning and NF washing process performed.

그러나 상기와 같은 종래의 반도체 소자의 콘택홀 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact hole in a semiconductor device has the following problems.

첫째, 폴리머성 잔류물이 그대로 잔류된 상태에서 콘택홀을 통해 도전층간의 접속이 이루어지는 경우, 도전층간의 접촉저항이 증가되거나 단락이 발생된다. First, when the connection between the conductive layers is made through the contact hole while the polymeric residue remains as it is, the contact resistance between the conductive layers is increased or a short circuit occurs.                         

둘째, 반도체 소자의 고집적화에 따른 콘택홀의 단차 증가에 따라 심하게 발생되는데, 심한 경우 잔류물에 의해 콘택홀이 막히는 현상도 발생된다. Second, as the contact hole increases due to high integration of semiconductor devices, the contact hole is clogged by residues.

셋째, 잔류물이 잔류되지 않도록 하기 위하여 콘택홀 형성시 과도 식각을 실시하는 경우에는 상기 콘택홀 내벽이 과도 식각되어 콘택홀의 모양이 불량해지고, 하부 도전층과의 거리가 단축되어 소자의 동작시 누설전류가 발생된다. Third, in the case of performing excessive etching during the formation of the contact hole so that no residue remains, the inner wall of the contact hole is excessively etched to deteriorate the shape of the contact hole, and the distance to the lower conductive layer is shortened, so that leakage occurs during operation of the device. Current is generated.

넷째, 최근에 반도체 소자가 고집적화 됨에 따라 콘택홀의 크기가 더욱 작아짐에 따라 세정액이 콘택홀 저면까지 충분히 유입되지 못하여 콘택홀의 세정효과가 떨어진다.Fourth, in recent years, as semiconductor devices have been highly integrated, the size of contact holes has become smaller, and as a result, the cleaning solution does not sufficiently flow to the bottom of the contact holes, thereby degrading the cleaning effect of the contact holes.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 콘택홀을 형성한 후 폴리머성 잔류물을 제거하여 소자의 불량을 방지함으로서 소자의 수율을 향상시키도록 한 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The method for forming a contact hole of a semiconductor device to improve the yield of the device by forming a contact hole and then removing a polymer residue to prevent a defect of the device. The purpose is to provide.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택홀 형성방법은, 반도체 기판 상에 절연막을 형성하는 단계, 상기 절연막 상에 감광막을 도포한 후 패터닝하여 콘택 영역을 정의하는 단계, 상기 패터닝된 감광막을 마스크로 이용하여 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계, 상기 감광막을 제거하는 단계, 상기 절연막의 표면 및 콘택홀 내부에 자외선을 조사하여 소수성인 상기 절연막 및 콘택홀의 내벽을 친수성으로 변화시키는 단계 및 상기 반도체 기판에 세정 공정을 실시하여 폴리머성 잔류물을 제거하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming an insulating film on a semiconductor substrate, applying a photosensitive film to the insulating film, and then patterning the contact region to define a contact region; Selectively removing the insulating film using a patterned photosensitive film as a mask to form a contact hole, removing the photosensitive film, irradiating ultraviolet rays to the surface of the insulating film and the inside of the contact hole to form a hydrophobic layer of the insulating film and the contact hole It is characterized in that it comprises the step of changing to hydrophilic and the step of performing a cleaning process on the semiconductor substrate to remove the polymeric residue.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이, 반도체 기판(21)상에 산화막(22)을 형성하고, 상기 산화막(22)상에 감광막(23)을 도포한 후, 노광 및 현상공정으로 감광막(23)을 패터닝하여 콘택 영역을 정의한다.As shown in FIG. 2A, the oxide film 22 is formed on the semiconductor substrate 21, the photosensitive film 23 is coated on the oxide film 22, and then the photosensitive film 23 is patterned by an exposure and development process. To define the contact area.

도 2b에 도시한 바와 같이, 상기 패터닝된 감광막(23)을 마스크로 이용하여 상기 반도체 기판(21)의 표면이 소정부분 노출되도록 상기 산화막(22)을 선택적으로 제거하여 콘택홀(24)을 형성한다.As shown in FIG. 2B, using the patterned photoresist 23 as a mask, a contact hole 24 is formed by selectively removing the oxide layer 22 to expose a predetermined portion of the surface of the semiconductor substrate 21. do.

도 2c에 도시한 바와 같이, 상기 감광막(23)을 제거한다.As shown in Fig. 2C, the photosensitive film 23 is removed.

여기서 상기 감광막(23)을 제거할 때 상기 산화막(22)의 표면 및 콘택홀(24)의 내부에 폴리머성의 잔류물(25)이 잔류된다.When the photosensitive layer 23 is removed, a polymeric residue 25 remains on the surface of the oxide layer 22 and inside the contact hole 24.

도 2d에 도시한 바와 같이, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 인(Phosphrus) 이온을 10 ~ 40°의 경사각과 15 ~ 40°의 회전각으로 주입한다.As illustrated in FIG. 2D, Phosphrus ions are implanted into the front surface of the semiconductor substrate 21 including the contact hole 24 at an inclination angle of 10 to 40 degrees and a rotation angle of 15 to 40 degrees.

여기서 상기 인 이온에 의해 산화막(22)의 표면 및 콘택홀(24)의 내벽을 소수성에서 친수성으로 변화시킨다.The phosphorus ions change the surface of the oxide film 22 and the inner wall of the contact hole 24 from hydrophobic to hydrophilic.

한편, 상기 인 이온은 20KeV 미만의 저에너지 이온 주입기로 1.0E13 ~ 5E14dose/㎠로 공정 시간을 짧게 하여 주입한다.On the other hand, the phosphorus ion is implanted with a low energy ion implanter of less than 20 KeV in a short process time at 1.0E13 ~ 5E14dose / ㎠.

여기서 상기 P 이온을 10 ~ 40°의 경사로 주입하는 이유는 Vt의 변화를 방지하기 위해서이고, 15 ~ 40°의 회전각으로 주입하는 이유는 Vt의 성능을 향상시키기 위해서이다.The reason for implanting the P ions at an inclination of 10 to 40 ° is to prevent the change of Vt, and the reason for implanting at a rotation angle of 15 to 40 ° is to improve the performance of Vt.

또한, 다른 실시예로 인 이온을 주입하지 않고, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 UV 램프를 이용하여 200 ~ 450㎚의 파장으로 약 30초미만 자외선을 조사하여 상기 산화막(22) 및 콘택홀(24)의 내벽을 소수성에서 친수성으로 변화시킨다.Further, in another embodiment, UV is irradiated for less than about 30 seconds at a wavelength of 200 to 450 nm using a UV lamp on the entire surface of the semiconductor substrate 21 including the contact hole 24 without implanting phosphorus ions. The inner walls of the oxide film 22 and the contact hole 24 are changed from hydrophobic to hydrophilic.

도 2e에 도시한 바와 같이, 상기 P 이온 주입 또는 UV 램프로 조사된 반도체 기판(21)에 BN 세정 또는 NF 세정 등을 이용한 세정공정을 실시하여 상기 콘택홀(24) 및 산화막(22) 주위의 폴리머성 잔류물(25)을 제거한다. As shown in FIG. 2E, the semiconductor substrate 21 irradiated with the P ion implantation or the UV lamp is subjected to a cleaning process using BN cleaning or NF cleaning, and the like, around the contact hole 24 and the oxide film 22. The polymeric residue 25 is removed.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택홀 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact hole in a semiconductor device according to the present invention has the following effects.

첫째, 감광막을 제거한 후 이온 주입 공정 또는 UV 램프를 이용한 자외선 조사를 실시하여 산화막의 표면 및 콘택홀의 내벽을 소수성에서 친수성으로 변화시킨 후 세정 공정을 실시함으로서 폴리머성의 잔류물을 완전히 제거한다. First, after removing the photoresist, an ion implantation process or UV irradiation using a UV lamp is performed to change the surface of the oxide film and the inner wall of the contact hole from hydrophobicity to hydrophilicity and then perform a cleaning process to completely remove the polymeric residue.

따라서 잔류물로 인한 콘택홀의 막힘 또는 도전층간의 접속불량이 방지되어 소자의 전기적 특성 저하가 방지된다. Therefore, clogging of the contact hole due to the residue or poor connection between the conductive layers is prevented, thereby reducing the electrical characteristics of the device.

둘째, 콘택홀을 형성한 후 CD(Critical Dimension) SEM(Scanning Electron Microscopy) 장비를 이용하여 상기 콘택홀의 크기를 측정할 때 잔류물에 의해 발생되는 노이즈(Noise)성의 신호가 발생되지 않아 콘택홀의 정확한 크기 측정이 가능해 진다.Second, after forming the contact hole, when measuring the size of the contact hole using CD (Critical Dimension) SEM (Scanning Electron Microscopy) equipment, the signal of noise generated by the residue is not generated so that the accurate contact hole Size measurement becomes possible.

셋째, 잔류물이 잔류되지 않도록 하기 위하여 콘택홀 형성시 과도 식각을 실시하지 않아도 되기 때문에 콘택홀 내벽이 과도 식각되어 콘택홀의 모양이 불량해지고, 하부 도전층과의 거리가 단축되어 소자의 동작시 누설전류가 발생하는 것을 방지할 수 있다. Third, in order to prevent the residue from remaining, excessive etching is not necessary during the formation of the contact hole. Therefore, the inner wall of the contact hole is excessively etched and the shape of the contact hole is poor, and the distance from the lower conductive layer is shortened. Generation of current can be prevented.

Claims (6)

삭제delete 삭제delete 삭제delete 삭제delete 반도체 기판 상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 절연막 상에 감광막을 도포한 후 패터닝하여 콘택 영역을 정의하는 단계;Applying a photoresist film on the insulating film and then patterning the contact area to define a contact region; 상기 패터닝된 감광막을 마스크로 이용하여 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;Selectively removing the insulating layer by using the patterned photoresist as a mask to form a contact hole; 상기 감광막을 제거하는 단계;Removing the photosensitive film; 상기 절연막의 표면 및 콘택홀 내부에 자외선을 조사하여 소수성인 상기 절연막 및 콘택홀의 내벽을 친수성으로 변화시키는 단계; 및Irradiating ultraviolet rays on the surface of the insulating film and the inside of the contact hole to change the hydrophobic inner walls of the insulating film and the contact hole to be hydrophilic; And 상기 반도체 기판에 세정 공정을 실시하여 폴리머성 잔류물을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And removing a polymeric residue by performing a cleaning process on the semiconductor substrate. 제 5 항에 있어서, 상기 자외선은 UV 램프를 이용하여 200 ~ 450㎚의 파장으로 30초미만 조사하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 5, wherein the ultraviolet light is irradiated for less than 30 seconds at a wavelength of 200 to 450 nm using a UV lamp.
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KR19980078155A (en) * 1997-04-25 1998-11-16 김영환 Contact hole formation method of semiconductor device
KR0176195B1 (en) * 1996-02-21 1999-04-15 김광호 Method for forming wiring of semiconductor device
KR20000004232A (en) * 1998-06-30 2000-01-25 김영환 Method for forming contact hole of semiconductor device

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KR0176195B1 (en) * 1996-02-21 1999-04-15 김광호 Method for forming wiring of semiconductor device
KR19980078155A (en) * 1997-04-25 1998-11-16 김영환 Contact hole formation method of semiconductor device
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