KR20090003719A

KR20090003719A - Method for fabricating semiconductor device

Info

Publication number: KR20090003719A
Application number: KR1020070066626A
Authority: KR
Inventors: 이대명
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-07-03
Filing date: 2007-07-03
Publication date: 2009-01-12

Abstract

The method of manufacturing the semiconductor device is provided to prevent the hump without the use of the boron implantation process and to solve the breakdown voltage drop. The gate insulating layer(21) is formed on the field area and the active area (20A) of the substrate(20). The anti oxidation layer is formed on the gate insulating layer of the active area. The birds beak is formed on the gate insulating layer by using the anti oxidation layer as the barrier. The anti oxidation layer is removed. The gate insulating layer of the field area and a part of substrate are etched and the trench is generated. The element isolation film(26) is formed in the trench. The anti oxidation layer is formed with the nitride film.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device for preventing a hump.

Hump generation in semiconductor devices, particularly low voltage NMOS transistors, is problematic because of the increase in standby current and the inefficiency of the device.

1A to 1B are cross-sectional views illustrating a method of manufacturing a general semiconductor device.

First, as shown in FIG. 1A, boron is injected into the substrate 10 having the field region and the active region to adjust the threshold voltage to form the threshold voltage adjusting ion implantation layer 100.

Subsequently, the gate insulating film 11 and the hard mask film 12 are sequentially formed on the substrate 10, and after the hard mask film 12 is patterned to remain on the active region, the patterned hard mask film 12 is formed. The trench 13 is formed by etching the gate insulating film 11 and the substrate 10 in the field region using the mask to define the active region 10A.

Subsequently, as shown in FIG. 1B, an insulating film is deposited on the entire structure to fill the trench 13, and then a planarization process is performed to expose the hard mask film 12 to form the device isolation film 14.

Subsequently, although not shown, a gate electrode is formed on the gate insulating film 11.

However, when the process proceeds as described above, a large amount of boron diffuses toward the device isolation film 14 at the edge portion of the threshold voltage control ion implantation layer 100 by the heat of the insulating film deposition process used as the device isolation film 14. Boron segregation, which is isolated in the device isolation layer 14, is generated, which causes a hump in which a threshold voltage of the edge portion of the active region 10A is lowered.

Transistors having such hump characteristics are easily deteriorated under stress due to subsequent thermal and oxidation processes, resulting in an increase in standby current, resulting in poor product quality.

Accordingly, a method of compensating the amount of boron lost due to boron segmentation has been proposed by injecting boron into the outer wall of the trench 13 after forming the trench 13.

As such, when boron is injected into the outer wall of the trench 13, the hump can be prevented. However, in the case of a transistor having a narrow width, boron is injected not only at the edge portion of the threshold voltage control ion implantation layer 100 but also at the center portion thereof, thereby increasing the threshold voltage of the transistor.

In addition, damage is generated in the substrate 20 during the boron injection, and the breakdown voltage of the high voltage transistor is reduced due to the injection of boron into the high voltage transistor as well as the low voltage transistor.

The present invention has been proposed to solve the above problems of the prior art, by preventing the hump without using the boron injection process used to prevent the hump, problems caused by using the boron injection process SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of solving the problem of increasing the threshold voltage of a transistor, damage to a substrate, and a breakdown voltage of a high voltage transistor.

According to an aspect of the present invention, there is provided a method including forming a gate insulating film on a field region and an active region of a substrate, forming an oxide film on the gate insulating layer on the active region, and Growing the gate insulating film by using an oxide barrier as a barrier to form a burj beak in the gate insulating film at an edge portion of the active region, removing the antioxidant film, and forming a portion of the gate insulating film and the substrate in the field region. Forming a trench by etching the trench, and forming a device isolation layer in the trench.

According to the present invention, the following effects are obtained.

First, since the threshold voltage of the active region edge portion can be increased by forming a buzz beak in the gate insulating layer of the active region edge portion, the boron of the threshold voltage control ion implantation layer formed on the edge portion of the active region during the insulating layer deposition process for filling the trench This loss can prevent the hump by compensating the threshold voltage of the lower portion of the active region edge.

Second, since humps can be prevented by forming a burj beak in the gate insulating film at the edge portion of the active region, the boron implantation process previously performed to prevent the humps can be omitted. Therefore, problems caused by the boron implantation process (increase in narrow transistor threshold voltage, substrate damage, breakdown voltage of the high voltage transistor) can be prevented.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A through 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 2A, boron is injected into the active region and the field region of the substrate 20 to form the threshold voltage control ion implantation layer 200.

Subsequently, the gate insulating film 21, the antioxidant film 22, and the cap insulating film 23 are sequentially formed on the substrate 20. The gate insulating film 21 and the cap insulating film 23 may be formed of an oxide film, and the antioxidant film 22 may be formed of a nitride film.

Subsequently, as shown in FIG. 2B, the cap insulating film 23 and the antioxidant film 22 are patterned to remain on the active region by a photolithography process, and then the cap insulating film 23 is removed.

Subsequently, as illustrated in FIG. 2C, an oxide film 22 is formed by a thermal oxidation process using the patterned antioxidant film 22 as a barrier, and the gate insulating film 21A in the exposed field region is grown. .

At this time, the gate insulating film 21A in the field region is grown to a thick thickness, and the gate insulating film 21 in the active region is only bent at the edge portion of the active region as oxidation is suppressed due to the anti-oxidation film 22 formed thereon. Grow in shape. That is, a bird's beak is formed in the gate insulating film 21 at the edge portion of the active region.

Subsequently, as shown in FIG. 2D, the antioxidant film 22 is removed and a cleaning process is performed.

Next, as shown in FIG. 2E, the hard mask layer 24 is formed on the gate insulating layer 21, and the hard mask layer 24 is patterned by a photolithography process so that the field region is opened. Here, the hard mask film 24 may be formed of a nitride film.

Subsequently, the trench 25 is formed by etching the gate insulating layer 21 and the substrate 20 in the field region using the patterned hard mask layer 24 as a mask. As a result, the active region 20A is limited.

Subsequently, as shown in FIG. 2F, an insulating film is formed on the entire surface to fill the trench 25, and the insulating film is planarized so that the hard mask film 24 is exposed to form the device isolation layer 26, and then the hard mask. The membrane 24 is removed.

It is preferable to use an HDP (High Density Plasma) oxide film having excellent embedding characteristics as the insulating film for filling the trench 25.

Subsequently, as shown in FIG. 2G, a conductive film is deposited on the entire surface including the gate insulating film 21 exposed by the removal of the hard mask film 24, and the conductive film is patterned so as to remain on the gate insulating film 21. 27).

In the semiconductor device formed as described above, a buzz beak is formed in the gate insulating film 21 at the edge portion of the active region 20A, so that the thickness of the gate insulating film 21 at the edge portion of the active region 20A is increased. (20A) The threshold voltage of the edge portion rises.

Therefore, the threshold voltage of the edge portion of the active region 20A lowered due to the loss of boron of the threshold voltage control ion implantation layer 200 at the edge portion of the active region 20A during the insulating film forming process for filling the trench 25 is reduced. Compensated, the hump is prevented.

Therefore, the boron injection process that was previously performed to prevent the hump can be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

20: substrate

20A: active area

200: threshold voltage control ion implantation layer

21, 21A: gate insulating film

22: antioxidant film

23: cap insulation film

24: hard mask

25: trench

26: device isolation film

27: gate electrode

Claims

Forming a gate insulating film on the field region and the active region of the substrate;

Forming an anti-oxidation film on the gate insulating film in the active region;

Growing the gate insulating film with the anti-oxidation film as a barrier to form a burj beak in the gate insulating film at an edge portion of the active region;

Removing the antioxidant film;

Etching a portion of the gate insulating layer and the substrate in the field region to form a trench;

Forming an isolation layer in the trench

Method of manufacturing a semiconductor device comprising a.

The method of claim 1,

A method of manufacturing a semiconductor device, wherein the antioxidant film is formed of a nitride film.

The method of claim 1,

And removing the antioxidant film and then performing a cleaning step.

The method of claim 1,

And forming a hard mask film on the substrate of the active region before forming the trench, and etching the gate insulating film and a portion of the substrate using the hard mask film as a barrier to form the trench.

The method of claim 4, wherein

A method for manufacturing a semiconductor device, wherein the hard mask film is formed of a nitride film.