KR20080113637A - Multi-semiconductor chip package and manufacturing method thereof - Google Patents

Multi-semiconductor chip package and manufacturing method thereof Download PDF

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KR20080113637A
KR20080113637A KR1020070062374A KR20070062374A KR20080113637A KR 20080113637 A KR20080113637 A KR 20080113637A KR 1020070062374 A KR1020070062374 A KR 1020070062374A KR 20070062374 A KR20070062374 A KR 20070062374A KR 20080113637 A KR20080113637 A KR 20080113637A
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metal plate
semiconductor chip
unit
bonding
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KR1020070062374A
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Korean (ko)
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조상귀
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A multi-chip package and a manufacturing method thereof are provided to interpose a metal spacer between a plurality of semiconductor chips and secure a wire loop gap and release the heat of semiconductor chips rapidly to outside in order to make the operation of the semiconductor chip smooth. A multi-chip package(100) comprises a metal plate(120), a plurality of semiconductor chips(130,140), and a spacer(150). The metal plate is formed according to each unit outer of a substrate. The semiconductor chip is laminated on the upper side of each unit. The spacer is interposed among a plurality of semiconductor chips. The spacer has a connection part(151) connected to the metal plate.

Description

멀티 칩 패키지 및 그 제조방법{Multi-semiconductor chip package and manufacturing method thereof}Multi-chip package and manufacturing method

도 1은 종래 멀티 칩 패키지를 보인 종단면도1 is a longitudinal cross-sectional view showing a conventional multi-chip package

도 2는 종래 다른 멀티 칩 패키지를 보인 종단면도Figure 2 is a longitudinal cross-sectional view showing another conventional multi-chip package

도 3은 본 발명의 일 실시 예에 따른 멀티 칩 패키지를 보인 종단면도Figure 3 is a longitudinal cross-sectional view showing a multi-chip package according to an embodiment of the present invention

도 4는 본 발명의 일 실시 예에 따른 멀티 칩 패키지를 보인 평면도4 is a plan view showing a multi-chip package according to an embodiment of the present invention

도 5는 본 발명에 따른 멀티 칩 패키지 제조방법을 설명하는 흐름도5 is a flowchart illustrating a method of manufacturing a multichip package according to the present invention.

도 6a-6d는 본 발명에 따른 멀티 칩 패키지 제조방법을 설명하는 평면도6A-6D are plan views illustrating a method of manufacturing a multichip package according to the present invention.

도 7은 본 발명의 다른 실시 예에 따른 멀티 칩 패키지를 보인 종단면도7 is a longitudinal cross-sectional view showing a multi-chip package according to another embodiment of the present invention

*주요부분에 대한 도면부호 * Drawing reference for the main part

100 : 멀티 칩 패키지100: multi chip package

110 : 기판110: substrate

120 : 금속판120: metal plate

130,140 : 반도체 칩130,140: Semiconductor Chip

150 : 금속 스페이서150: metal spacer

F : 본드핑거F: Bond Finger

151 : 연결부151: connection

본 발명은 멀티 칩 패키지 및 그 제조방법에 관한 것으로, 특히 반도체 칩들 사이에 금속 스페이서가 개재되어 와이어 본딩 루프 갭을 확보하고, 금속 스페이서가 기판의 외곽을 따라 형성된 금속판과 연결됨으로써 반도체 칩에서 발생하는 열을 신속하게 방열할 수 있는 멀티 칩 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package and a method of manufacturing the same. In particular, a metal spacer is interposed between the semiconductor chips to secure a wire bonding loop gap, and the metal spacer is connected to a metal plate formed along the periphery of the substrate. The present invention relates to a multi-chip package capable of dissipating heat quickly and a manufacturing method thereof.

최근 멀티 칩 패키지 내에 수용되는 반도체 칩의 수를 늘림으로써 고집적(high density) 멀티 칩 패키지를 구현하기 위한 연구가 활발하게 진행되고 있다.Recently, researches for implementing high density multi-chip packages by actively increasing the number of semiconductor chips accommodated in the multi-chip packages have been actively conducted.

본딩 와이어를 이용하여 칩 적층 시, 상부 칩과 하부 칩 사이에 와이어 본딩 루프를 위한 갭(높이) 확보를 필요로 한다. 갭 확보를 위해 사용하는 방법들로는 테이프, 에폭시 등의 물질을 사용하는 방법과, 베어 실리콘을 사용하는 방법이 사용되고 있다.When the chip is stacked using the bonding wire, it is necessary to secure a gap (height) for the wire bonding loop between the upper chip and the lower chip. As a method for securing a gap, a method of using a material such as a tape or an epoxy and a method of using a bare silicon are used.

도 1은 종래 멀티 칩 패키지를 보인 종단면도이다.1 is a longitudinal cross-sectional view showing a conventional multi-chip package.

도 1을 참조하면, 종래 멀티 칩 패키지(10)에 있어서는, 기판(11) 상에 반도체 칩들(12)(13)이 적층되며, 상기 반도체 칩(12)(13)과 기판(11)을 연결하는 본딩 와이어의 와이어 루프 갭을 확보하기 위해 반도체 칩들(12)(13) 사이에 실리콘 스페이서(14)가 개재되어 있다.Referring to FIG. 1, in the conventional multichip package 10, semiconductor chips 12 and 13 are stacked on a substrate 11, and the semiconductor chips 12 and 13 are connected to the substrate 11. In order to secure the wire loop gap of the bonding wire, the silicon spacers 14 are interposed between the semiconductor chips 12 and 13.

도 2는 종래 다른 멀티 칩 패키지를 보인 종단면도이다.Figure 2 is a longitudinal cross-sectional view showing another conventional multi-chip package.

도 2를 참조하면, 종래 다른 멀티 칩 패키지에 있어서는, 기판(21) 상에 반도체 칩(22)이 적층되며, 봉지재(23) 내부에는 그 상면으로 방열판(25)이 노출되게 위치되어 있다. Referring to FIG. 2, in another conventional multichip package, the semiconductor chip 22 is stacked on the substrate 21, and the heat dissipation plate 25 is exposed to the upper surface of the encapsulant 23.

그러나, 도 1에 도시된 종래 멀티 칩 패키지(10)에서는 실리콘 스페이서(14)가 본딩 와이어의 와이어 루프 갭을 확보하는 역할만을 하며, 반도체 칩(12)(13)의 열을 효율적으로 방열하지 못하는 기능상의 한계성이 있었다.However, in the conventional multi-chip package 10 shown in FIG. 1, the silicon spacer 14 only serves to secure a wire loop gap of the bonding wire, and does not efficiently dissipate heat of the semiconductor chips 12 and 13. There was a functional limitation.

도 2에 도시된 종래 멀티 칩 패키지(20)에서는 방열판(25)이 방열 기능만을 수행할 뿐 스페이서의 기능을 할 수 없는 한계성이 있었다.In the conventional multi-chip package 20 shown in FIG. 2, the heat sink 25 only performs a heat dissipation function, but has a limitation in that it cannot function as a spacer.

따라서, 본 발명은 이와 같은 문제점을 감안하여 고안된 것으로, 본 발명이 이루고자 하는 과제는 본딩 와이어의 와이어 루프 갭을 확보하는 스페이서의 기능은 물론이고, 방열 및 접지 기능도 가지는 멀티 칩 패키지 및 그 제조방법을 제공하는데에 있다.Accordingly, the present invention has been devised in view of the above problems, and an object of the present invention is to provide a multi-chip package having a heat dissipation and grounding function as well as a function of securing a wire loop gap of a bonding wire, and a method of manufacturing the same. In providing.

이와 같은 기술적 과제를 구현하기 위하여 본 발명에 따른 멀티 칩 패키지 는 기판의 각 유닛 외곽을 따라 형성되는 금속판; 상기 각 유닛의 상면에 적층된 복수 개의 반도체 칩; 및 상기 복수 개의 반도체 칩 사이에 개재되며, 상기 금속판과 연결되는 연결부를 갖는 금속 스페이서를 포함한다.In order to implement the above technical problem, the multi-chip package according to the present invention includes a metal plate formed along the periphery of each unit of the substrate; A plurality of semiconductor chips stacked on an upper surface of each unit; And a metal spacer interposed between the plurality of semiconductor chips and having a connection portion connected to the metal plate.

본딩 와이어에 의해 상기 반도체 칩의 본딩패드는 상기 유닛의 본드핑거에 전기적으로 연결될 수 있다.Bonding pads of the semiconductor chip may be electrically connected to bonding fingers of the unit by bonding wires.

상기 스페이서의 상면에는 다른 반도체 칩이 적층되고, 상기 다른 반도체 칩의 상면에는 다른 스페이서가 순차적으로 적층될 수 있다.Another semiconductor chip may be stacked on an upper surface of the spacer, and another spacer may be sequentially stacked on an upper surface of the other semiconductor chip.

본딩 와이어에 의해 상기 각 반도체 칩의 본딩패드가 상기 유닛의 본드핑거에 상호 연결되고, 상기 각 스페이서는 연결부에 의해 상기 금속판에 상호 연결될 수 있다.Bonding pads of the respective semiconductor chips may be interconnected to the bond fingers of the unit by bonding wires, and the spacers may be interconnected to the metal plate by connecting portions.

상기 금속판은 상기 유닛의 사면에 형성되고, 상기 금속판은 봉지재의 외 측면으로 노출되는 것이 바람직하다.The metal plate is formed on the slope of the unit, the metal plate is preferably exposed to the outer side of the encapsulant.

또, 본 발명에 따른 멀티 칩 패키지 제조방법은 기판의 각 유닛 외곽을 따라 금속판을 형성하고, 상기 각 유닛의 상면에 반도체 칩을 본딩하고, 상기 반도체 칩의 상면에 금속 스페이서를 본딩하고, 상기 금속 스페이서와 상기 금속판을 상호 연결한다.In addition, the method of manufacturing a multi-chip package according to the present invention forms a metal plate along each unit outer periphery of a substrate, bonds a semiconductor chip to an upper surface of each unit, bonds a metal spacer to an upper surface of the semiconductor chip, and The spacer and the metal plate are interconnected.

본딩 와이어를 이용하여 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 전기적으로 상호 연결할 수 있다.Bonding wires of the semiconductor chip may be electrically connected to the bonding fingers of the unit using bonding wires.

상기 각 유닛의 상면에 반도체 칩을 본딩한 직후에 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 연결할 수 있다.A bonding pad of the semiconductor chip may be connected to a bond finger of the unit immediately after bonding the semiconductor chip to the upper surface of each unit.

상기 반도체 칩의 상면에 금속판을 본딩한 직후에 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 연결할 수도 있다.A bonding pad of the semiconductor chip may be connected to a bond finger of the unit immediately after bonding the metal plate to the upper surface of the semiconductor chip.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예들을 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 일 실시 예에 따른 멀티 칩 패키지를 보인 종단면도이고, 도 4는 본 발명의 일 실시 예에 따른 멀티 칩 패키지를 보인 평면도이다. 3 is a longitudinal sectional view showing a multi-chip package according to an embodiment of the present invention, Figure 4 is a plan view showing a multi-chip package according to an embodiment of the present invention.

도 3 및 도 4를 참조하면, 본 발명의 일 실시 예에 따른 멀티 칩 패키지(100)는 기판(110)의 외곽을 따라 형성되는 금속판(120)을 구비한다.3 and 4, the multi-chip package 100 according to an embodiment of the present invention includes a metal plate 120 formed along the outer side of the substrate 110.

상기 기판(110)의 상면에는 복수 개의 반도체 칩들(130)(140)이 순차적으로 적층되고, 상기 반도체 칩들(130)(140) 사이에는 와이어 루프 갭을 확보하기 위하여 금속 스페이서(150)가 개재되어 있다.A plurality of semiconductor chips 130 and 140 are sequentially stacked on the upper surface of the substrate 110, and metal spacers 150 are interposed between the semiconductor chips 130 and 140 to secure a wire loop gap. have.

상기 반도체 칩들(130)(140)과 스페이서(150)의 접착제(111)로는 공지의 액상 접착제나 접착 테이프 등이 사용될 수 있다.As the adhesive 111 of the semiconductor chips 130 and 140 and the spacer 150, a known liquid adhesive or an adhesive tape may be used.

본딩 와이어(WB:Wire-Bonding)에 의해 상기 각 반도체 칩(130)(140)의 본딩패드(P)는 상기 기판(110)의 본드핑거(F)에 전기적으로 연결되어 있고, 상기 스페이서(150)는 연결부(151)에 의해 상기 금속판(120)에 상호 연결되어 있다.The bonding pads P of the semiconductor chips 130 and 140 are electrically connected to the bond fingers F of the substrate 110 by a bonding wire (WB) and the spacer 150 ) Is interconnected to the metal plate 120 by a connecting portion 151.

상기 금속판(120)은 상기 기판(110)의 사면(四面)에 형성되어, 그 부피를 최대한 크게 하는 것이 바람직하다.The metal plate 120 is formed on the four sides of the substrate 110, so that the volume thereof is as large as possible.

또, 통상 기판(110)의 상면에는 봉지재(Encapsulant)(160)가 코팅되는데, 상기 금속판(120)은 봉지재(160)의 외 측면으로 노출됨으로써, 칩에서 발생하는 열이 외부로 신속하게 방출하여 멀티 칩 패키지의 방열 효과를 높일 수 있다.In addition, an encapsulant 160 is coated on an upper surface of the substrate 110, and the metal plate 120 is exposed to the outer side of the encapsulant 160, so that heat generated from a chip is quickly displaced to the outside. Emission can increase the heat dissipation effect of multi-chip package.

또, 상기 금속판(120)에 접지회로가 연결될 경우 상기 금속판(120)은 접지 기능을 수행하게 되어 멀티 칩 패키지의 접지 기능을 높일 수 있다.In addition, when the ground circuit is connected to the metal plate 120, the metal plate 120 performs a grounding function to increase the grounding function of the multi-chip package.

도 5는 본 발명의 일실 예에 따른 멀티 칩 패키지 제조방법을 설명하는 흐름도이다.5 is a flowchart illustrating a method of manufacturing a multichip package according to an exemplary embodiment of the present invention.

도 5를 참조하면, 이와 같이 구성된 본 발명의 일 실시 예에 따른 멀티 칩 패키지 제조방법은 전체 기판에 다수의 유닛을 구획하고, 각 유닛 외곽을 따라 금속판을 형성하는 단계(S110)와, 상기 각 유닛의 상면에 반도체 칩을 본딩하고 상기 반도체 칩의 상면에 금속 스페이서를 본딩하는 단계(S120)와, 상기 금속 스페이서와 상기 금속판을 상호 연결하는 단계(S130)를 포함한다.Referring to FIG. 5, the method for manufacturing a multi-chip package according to an embodiment of the present invention configured as described above may include: dividing a plurality of units on an entire substrate, and forming a metal plate along each unit outside (S110); Bonding a semiconductor chip to an upper surface of the unit and bonding a metal spacer to an upper surface of the semiconductor chip (S120); and interconnecting the metal spacer and the metal plate (S130).

이하, 도 6a-6d을 참조하여 본 발명의 일실시 예에 따른 멀티 칩 패키지 제조방법에 대하여 좀더 구체적으로 설명한다.Hereinafter, a method of manufacturing a multichip package according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 6A-6D.

먼저, 도 6a에 도시된 바와 같이, 전체 기판(101)에 각 유닛(110)을 구획하고, 상기 유닛(110)의 외곽을 따라 금속판(120)을 형성한다.First, as shown in FIG. 6A, each unit 110 is partitioned on the entire substrate 101, and a metal plate 120 is formed along the periphery of the unit 110.

도 6b에 도시된 바와 같이, 상기 각 유닛(110)의 상면에 제 1 반도체 칩(130)을 적층하고 통상의 액상 접착제를 사용하여 본딩한다. As shown in FIG. 6B, the first semiconductor chip 130 is stacked on the upper surface of each unit 110 and bonded using a conventional liquid adhesive.

본딩 와이어(WB)을 이용하여 상기 제 1 반도체 칩(130)의 본딩패드(131:도 3 참조)를 상기 유닛(110)의 본드핑거(F:도 3 참조)에 전기적으로 상호 연결한다.The bonding pads 131 (see FIG. 3) of the first semiconductor chip 130 are electrically connected to the bond fingers F (see FIG. 3) of the unit 110 using bonding wires WB.

그 다음, 도 6c에 도시된 바와 같이, 상기 제 1 반도체 칩(130)의 상면에 금속 스페이서(150)를 적층하고 통상의 액상 접착제를 사용하여 본딩한 다음, 연결부(151)로 상기 금속 스페이서(150)와 상기 금속판(120)을 상호 연결한다. 상기 연결부(151)는 열 전도성이 좋은 재료라면 어떠한 것이라도 좋다.Next, as shown in FIG. 6C, the metal spacers 150 are stacked on the top surface of the first semiconductor chip 130 and bonded using a conventional liquid adhesive, and then the metal spacers (150) are connected to the connection portions 151. 150 and the metal plate 120 are interconnected. The connecting portion 151 may be any material as long as the material has good thermal conductivity.

그 다음, 도 6d에 도시된 바와 같이, 상기 금속 스페이서(150)의 상면에 제 2 차 반도체 칩(140)을 적층하여 본딩한다.Next, as illustrated in FIG. 6D, the second semiconductor chip 140 is stacked and bonded on the upper surface of the metal spacer 150.

여기서, 와이어 본딩을 진행함에 있어서, 상기 제 2 반도체(140)의 사이즈가 상기 제 1 반도체 칩(130) 사이즈보다 작을 경우에는, 상기 제 1 반도체 칩(130), 금속 스페이서(150), 제 2 반도체 칩(140)을 순차적으로 적층, 본딩한 후 각 반도체 칩의 본딩패드(F)를 상기 유닛(110)의 핑거패드(F)에 연결하여 와이어 본딩을 할 수 있다.In the wire bonding, when the size of the second semiconductor 140 is smaller than the size of the first semiconductor chip 130, the first semiconductor chip 130, the metal spacer 150, and the second semiconductor chip 130 may be formed. After stacking and bonding the semiconductor chips 140 in sequence, wire bonding may be performed by connecting the bonding pads F of each semiconductor chip to the finger pads F of the unit 110.

반면에, 상기 제 2 반도체(140)의 사이즈가 상기 제 1 반도체 칩(130) 사이즈보다 클 경우에는 상기 제 2 반도체 칩(140)이 상기 제 1 반도체 칩(130)을 가리어 와이어 본딩 작업을 방해하기 때문에 이러한 방해를 방지하기 위해, 상기 유닛(110)의 상면에 상기 제 1 반도체 칩(130)을 적층, 본딩한 직후에 와이어 본딩을 하고, 상기 제 1 반도체 칩(130)의 상면에 금속 스페이서(150)를 본딩하고 연결부(151)를 금속판(120)에 연결하며, 상기 금속 스페이서(150)의 상면에 상기 제 2 반도체 칩(140)을 본딩한 직후에 와이어 본딩을 진행하는 것이 바람직하다.On the other hand, when the size of the second semiconductor 140 is larger than the size of the first semiconductor chip 130, the second semiconductor chip 140 interferes with the wire bonding operation of the first semiconductor chip 130. Therefore, in order to prevent such interference, wire bonding is performed immediately after the first semiconductor chip 130 is stacked and bonded on the upper surface of the unit 110, and a metal spacer is formed on the upper surface of the first semiconductor chip 130. It is preferable to bond the 150, connect the connection part 151 to the metal plate 120, and perform wire bonding immediately after bonding the second semiconductor chip 140 to the upper surface of the metal spacer 150.

위와 같은 공정을 거쳐, 상기 전체 기판(101)에 멀티 적층 패키지가 완료되면 각 유닛(110)을 쏘잉(Sawing)하여 낱개의 멀티 칩 패키지를 완성한다.After the above process, when the multi-lamination package is completed on the entire substrate 101, each unit 110 is sawed to complete a single multi-chip package.

상기 멀티 칩 패키지의 상면에는 봉지재(160)가 코팅되며, 상기 금속판(120)은 멀티 칩 패키지의 외 측면으로 노출됨으로써, 칩에서 발생하는 열을 외부로 신속하게 방출시켜 반도체 칩의 안정화를 도모할 수 있다.The encapsulant 160 is coated on the upper surface of the multi-chip package, and the metal plate 120 is exposed to the outer side of the multi-chip package, thereby rapidly dissipating heat generated from the chip to the outside to stabilize the semiconductor chip. can do.

또, 상기 금속판(120)에 접지회로가 연결될 경우 상기 금속판(120)은 접지 기능을 수행하게 되어 접지 기능을 높일 수 있다. In addition, when the ground circuit is connected to the metal plate 120, the metal plate 120 performs a grounding function to increase the grounding function.

한편, 도 7은 본 발명의 다른 실시 예에 따른 멀티 칩 패키지를 보인 종단면도이다.On the other hand, Figure 7 is a longitudinal cross-sectional view showing a multi-chip package according to another embodiment of the present invention.

도 7을 참조하면, 본 발명의 다른 실시 예에 따른 멀티 칩 패키지(200)는 기판(210)의 외곽을 따라 형성되는 금속판(220)을 구비한다.Referring to FIG. 7, the multi-chip package 200 according to another embodiment of the present invention includes a metal plate 220 formed along the outer edge of the substrate 210.

상기 기판(210)의 상면에는 복수 개의 반도체 칩들(230)(240)이 순차적으로 적층되고, 상기 반도체 칩들(230)(240) 사이에는 와이어 루프 갭을 확보하기 위하여 금속 스페이서(250)가 개재되어 있다.A plurality of semiconductor chips 230 and 240 are sequentially stacked on the upper surface of the substrate 210, and metal spacers 250 are interposed between the semiconductor chips 230 and 240 to secure a wire loop gap. have.

본딩 와이어(WB:Wire-Bonding)에 의해 상기 각 반도체 칩(230)(240)의 본딩패드(P)는 상기 기판(210)의 본드핑거(F)에 전기적으로 연결되고, 상기 각 스페이서(250)는 연결부(251)에 의해 상기 금속판(220)에 상호 연결될 수 있다.The bonding pads P of the semiconductor chips 230 and 240 are electrically connected to the bond fingers F of the substrate 210 by a bonding wire (WB), and each of the spacers 250 ) May be interconnected to the metal plate 220 by a connecting portion 251.

또, 본 발명의 다른 실시 예에 따른 멀티 칩 패키지에서는 별도의 연결부(241)를 통해서 상기 각 반도체 칩(230)(240)이 상기 금속판(220)에 상호 연결되어 있다.In addition, in the multi-chip package according to another embodiment of the present invention, the semiconductor chips 230 and 240 are connected to the metal plate 220 through separate connectors 241.

본 발명의 다른 실시 예에 따른 멀티 칩 패키지에서는, 상기 스페이서(250)가 연결부(251)에 의해 상기 금속판(220)에 상호 연결됨은 물론 별도의 연결부(241)를 통해서 상기 각 반도체 칩(230)(240)이 상기 금속판(220)에 상호 연결됨으로써, 칩의 방열 효과를 좀더 높일 수 있다.In the multi-chip package according to another embodiment of the present invention, the spacers 250 are interconnected to the metal plate 220 by the connecting portion 251 as well as the respective semiconductor chips 230 through separate connecting portions 241. Since 240 is connected to the metal plate 220, the heat dissipation effect of the chip may be further enhanced.

이와 같이 구성된 본 발명의 다른 실시 예에 따른 멀티 칩 패키지의 경우에는 별도의 연결부(241)를 통해서 상기 각 반도체 칩(230)(240)이 상기 금속판(220)에 상호 연결되는 점을 제외하고는 전술한 본 발명의 일 실시 예에 따른 멀티 칩 패키지와 동일하다. 따라서, 본 발명의 다른 실시 예에 따른 멀티 칩 패키지에서는 각 반도체 칩(230)(240)에서 발생하는 열이 스페이서(250)의 연결부(251)를 통해 금속판(22)으로 전달됨은 물론, 각 반도체 칩(230)(240)에서 발생하는 열이 별도의 연결부(241)를 통해서 직접 금속판(22)으로 전달되기 때문에 좀더 신속하게 방열을 할 수 있다.In the multi-chip package according to another embodiment of the present invention configured as described above, except that the semiconductor chips 230 and 240 are connected to the metal plate 220 through separate connectors 241. The same as the multi-chip package according to an embodiment of the present invention described above. Therefore, in the multi-chip package according to another embodiment of the present invention, heat generated from each of the semiconductor chips 230 and 240 is transferred to the metal plate 22 through the connection part 251 of the spacer 250, and each semiconductor Since heat generated from the chips 230 and 240 is directly transferred to the metal plate 22 through a separate connection part 241, heat radiation may be performed more quickly.

이상 설명한 바와 같이, 본 발명의 상세한 설명에서는 본 발명의 바람직한 실시예에 관하여 설명하였으나, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 범주에서 벗어나지 않는 한도 내에서 여러 가지 변형 가능함은 물론이다. 따라서 본 발명의 권리 범위는 설명된 실시 예에 국한되어 정해져서는 안되며, 후술하는 특허청구범위뿐만 아니라, 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.As described above, in the detailed description of the present invention has been described with respect to preferred embodiments of the present invention, those skilled in the art to which the present invention pertains various modifications can be made without departing from the scope of the present invention Of course. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below, but also by the equivalents of the claims.

상술한 바와 같이 본 발명에 의하면, 복수 개의 반도체 칩들의 사이에 금속 스페이서가 개재되어 와이어 루프 갭을 확보하며, 반도체 칩들의 열을 외부로 신속하게 방열시켜 반도체 칩의 작동을 원활하게 한다.As described above, according to the present invention, a metal spacer is interposed between the plurality of semiconductor chips to secure a wire loop gap, and the heat of the semiconductor chips is quickly dissipated to the outside to smoothly operate the semiconductor chip.

또, 기판의 외곽에 형성된 금속판에 접지회로가 연결될 경우, 금속판은 접지 기능을 수행하게 되어 접지 기능을 높일 수 있다.In addition, when the ground circuit is connected to the metal plate formed on the outer periphery of the substrate, the metal plate may perform the grounding function to increase the grounding function.

Claims (9)

기판의 각 유닛 외곽을 따라 형성되는 금속판;Metal plates formed along the periphery of each unit of the substrate; 상기 각 유닛의 상면에 적층된 복수 개의 반도체 칩; 및A plurality of semiconductor chips stacked on an upper surface of each unit; And 상기 복수 개의 반도체 칩 사이에 개재되며, 상기 금속판과 연결되는 연결부를 갖는 스페이서를 포함하는 멀티 칩 패키지.And a spacer interposed between the plurality of semiconductor chips, the spacer having a connection portion connected to the metal plate. 제 1항에 있어서,The method of claim 1, 상기 스페이서는 금속 스페이서 인 것을 특징으로 하는 멀티 칩 패키지.The spacer is a multi-chip package, characterized in that the metal spacer. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 본딩 와이어에 의해 상기 반도체 칩의 본딩패드는 상기 유닛의 본드핑거에 전기적으로 연결되는 것을 특징으로 하는 멀티 칩 패키지.The bonding pad of the semiconductor chip is electrically connected to the bond finger of the unit by a bonding wire. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 금속판은 상기 유닛의 사면에 형성되는 것을 특징으로 하는 멀티 칩 패키지. The metal plate is a multi-chip package, characterized in that formed on the four sides of the unit. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 금속판은 봉지재의 외측면으로 노출되는 것을 특징으로 하는 멀티 칩 패키지.The metal plate is a multi-chip package, characterized in that exposed to the outer surface of the encapsulant. 기판의 각 유닛 외곽을 따라 금속판을 형성하는 단계;Forming a metal plate along the periphery of each unit of the substrate; 상기 각 유닛의 상면에 반도체 칩을 적층하고, 상기 반도체 칩의 상면에 금속 스페이서를 적층하는 단계;Stacking a semiconductor chip on an upper surface of each unit, and stacking a metal spacer on an upper surface of the semiconductor chip; 상기 금속 스페이서와 상기 금속판을 상호 연결하는 단계를 포함하는 멀티 칩 패키지 제조방법.And interconnecting the metal spacer and the metal plate. 제 6항에 있어서,The method of claim 6, 본딩 와이어를 이용하여 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 전기적으로 상호 연결하는 것을 특징으로 하는 멀티 칩 패키지 제조방법.And a bonding pad of the semiconductor chip is electrically interconnected to a bond finger of the unit by using a bonding wire. 제 6항에 있어서,The method of claim 6, 상기 각 유닛의 상면에 반도체 칩을 본딩한 직후에 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 연결하는 것을 특징으로 하는 멀티 칩 패키지 제조방법.And bonding a bonding pad of the semiconductor chip to a bond finger of the unit immediately after bonding the semiconductor chip to the upper surface of each unit. 제 6항에 있어서,The method of claim 6, 상기 반도체 칩의 상면에 금속판을 본딩한 직후에 상기 반도체 칩의 본딩패드를 상기 유닛의 본드핑거에 연결하는 것을 특징으로 하는 멀티 칩 패키지 제조방 법.And bonding a bonding pad of the semiconductor chip to a bond finger of the unit immediately after bonding a metal plate to an upper surface of the semiconductor chip.
KR1020070062374A 2007-06-25 2007-06-25 Multi-semiconductor chip package and manufacturing method thereof KR20080113637A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921993B2 (en) 2013-05-02 2014-12-30 Samsung Electronics Co., Ltd. Semiconductor package having EMI shielding function and heat dissipation function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921993B2 (en) 2013-05-02 2014-12-30 Samsung Electronics Co., Ltd. Semiconductor package having EMI shielding function and heat dissipation function

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