KR20080108870A - Apparatus for adjusting frequency and dll circuit with the same - Google Patents

Abstract

A frequency controller reducing electronic jamming of semiconductor IC(Integrated Circuit) and DLL(Dynamic Link Library) circuit including the same are provided to support a stable operation of a semiconductor IC by reducing a generation probability of an electronic jamming phenomenon. A frequency controller(20) reducing electronic jamming of semiconductor IC comprises a frequency control signal generator and a frequency control part. The frequency control signal generator generates a frequency control signal of multiple bits in response to a first clock. The multiple bits are transited into bit-by-bit. The frequency control part controls a frequency of a reference clock in response to the frequency control signal of multiple bits.

Description

Apparatus for Adjusting Frequency and DLL Circuit with the Same

1 is a block diagram showing the configuration of a DLL circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram showing the configuration of the frequency adjusting device shown in FIG. 1; FIG.

3 is a detailed configuration diagram of the clock divider shown in FIG. 2;

4 is a detailed configuration diagram of a frequency control signal generation unit shown in FIG. 2;

5 is a waveform diagram of a frequency control signal output from the frequency control signal generator of FIG. 4;

6 is a detailed configuration diagram of the frequency adjusting unit shown in FIG. 2;

7 to 9 are diagrams for explaining the operation of the DLL circuit according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: clock input buffer 20: frequency adjusting device

30: delay device 40: clock driver

50: delay compensation device 60: phase comparison device

70: delay control device

The present invention relates to a frequency adjusting device and a DLL (Delay Locked Loop) circuit including the same, and more particularly, to a frequency adjusting device for reducing electromagnetic interference and a DLL circuit including the same.

Typically, DLL circuits are used to provide an internal clock that is time-phased relative to a reference clock obtained by converting an external clock. The DLL circuit is used to solve the problem that the internal clock utilized in the semiconductor integrated circuit is delayed through the clock buffer and the transmission line, thereby causing a phase difference with the external clock, thereby increasing the output data access time. The DLL circuit performs a function of controlling the phase of the internal clock to be a predetermined time ahead of the external clock in order to increase the effective data output interval.

On the other hand, the recent semiconductor integrated circuits are increasing in speed and high integration, and accordingly, electromagnetic interference (EMI) has emerged as an important problem. This electromagnetic interference phenomenon becomes larger as each clock and signals operate at the correct timing at a preset frequency. As such, the more precisely the operation of the semiconductor integrated circuit is performed, the larger the electromagnetic interference phenomenon appears, but in the related art, there is no technical means to solve the problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a frequency adjusting device for reducing electromagnetic interference of a semiconductor integrated circuit and a DLL circuit including the same.

In addition, the present invention has another technical problem to provide a frequency adjustment device for supporting a stable operation of the semiconductor integrated circuit and a DLL circuit including the same.

According to an aspect of the present invention, there is provided a frequency adjusting device, including: a frequency control signal generator configured to generate a plurality of bit frequency control signals for level shifting by one bit in response to a first clock; And a frequency adjusting unit adjusting a frequency of an input reference clock in response to the plurality of bits of the frequency control signal.

In addition, the frequency adjusting method according to another embodiment of the present invention, a) generating a divided clock by dividing the reference clock at a predetermined ratio; b) periodically changing a logic value of a plurality of bits of the frequency control signal in response to the division clock; And c) giving a delay time corresponding to a logic value of the plurality of bits of the frequency control signal to the reference clock.

And a DLL circuit according to another embodiment of the present invention, the frequency adjustment device for generating a frequency adjustment clock by periodically increasing or decreasing the frequency of the reference clock; A delay device generating a delay clock by delaying the frequency adjustment clock in response to a delay control signal; A delay compensation device for generating a feedback clock by giving a delay time of the delay amount of the output path of the delay clock to the delay clock; A phase comparison device configured to generate a phase comparison signal by comparing phases of the reference clock and the feedback clock; And a delay control device generating the delay control signal in response to the phase comparison signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram showing the configuration of a DLL circuit according to an embodiment of the present invention.

As shown, a clock input buffer 10 that buffers an external clock clk_ext to generate a reference clock clk_ref, and periodically increases or decreases the frequency of the reference clock clk_ref to adjust the frequency adjustment clock clk_adf. The frequency adjusting device 20 to generate the delay device 30 to generate the delay clock clk_dly by delaying the frequency adjusting clock clk_adf in response to the delay control signal dlcnt, and drives the delay clock clk_dly. The clock driver 40 generating the output clock clk_out and giving the delay clock clk_dly a delay time that models the delay amount of the output path of the delay clock clk_dly to generate the feedback clock clk_fb. Responsive to the phase compensator 60 and the phase comparison signal (phcmp) for generating a phase comparison signal (phcmp) by comparing the phase of the delay compensation device 50, the reference clock (clk_ref) and the feedback clock (clk_fb) By the above And a delay control unit 70 for generating a control signal (dlcnt).

In the DLL circuit configured as described above, the phase comparison device 60 transmits information on which one of the reference clock clk_ref and the feedback clock clk_fb is advanced to the phase comparison signal phcmp. Is delivered to the delay control device 70. The delay control device 70 generates the delay control signal dlcnt and transmits the delay control signal dlcnt to the delay device 30 in response to the information transmitted by the phase comparison signal phcmp. The amount of delay applied to the reference clock clk_ref is controlled. Meanwhile, the delay compensation device 50 models a delay value of a delay element existing in a path through which the delay clock clk_dly is output to a data output buffer and gives a delay amount corresponding thereto to the delay clock clk_dly. The feedback clock clk_fb is generated.

When the clock inputted to the delay device 30 maintains the preset frequency correctly, electromagnetic interference occurs in the delay device 30 and the DLL circuit. Since such electromagnetic interference leads to side effects such as signal interference, the frequency adjusting device 20 is provided to prevent this. The frequency adjusting device 20 periodically increases or decreases the frequency of the reference clock clk_ref. By the operation of the frequency adjusting device 20 as described above, the delay device 30 and the DLL circuit can reduce the electromagnetic interference phenomenon.

FIG. 2 is a block diagram showing the configuration of the frequency adjusting device shown in FIG.

The frequency adjuster 20 divides the frequency of the reference clock clk_ref to generate a divided clock clk_div, and level shifts by one bit in response to the divided clock clk_div. The reference clock clk_ref in response to the frequency control signal generator 220 generating an n-bit frequency control signal fqcnt <1: n> and the n-bit frequency control signal fqcnt <1: n>. And a frequency adjusting unit 230 for adjusting the frequency to generate the frequency adjusting clock clk_adf.

The clock divider 210 divides the frequency of the reference clock clk_ref at a predetermined ratio to generate the divided clock clk_div. The division ratio (eg, 2 division, 4 division, 8 division, etc.) of the reference clock clk_ref is selected by the designer. The designer sets an optimal time interval for adjusting the frequency with respect to the reference clock (clk_ref) through the test, and selects the division ratio of the reference clock (clk_ref) accordingly.

Thereafter, the frequency control signal generator 220 transmits the n-bit frequency control signal fqcnt <1: n> at which the level is shifted by one bit in synchronization with the toggle timing of the divided clock clk_div. Create That is, the n-bit frequency control signal fqcnt <1: n> changes one bit of the logic value every time the division clock clk_div toggles.

The frequency adjuster 230 delays the reference clock clk_ref in response to the n-bit frequency control signal fqcnt <1: n>. That is, the amount of delay with respect to the reference clock clk_ref is increased or decreased according to the change of the logic value of the n-bit frequency control signal fqcnt <1: n>. At this time, the n-bit frequency control signal fqcnt <1: n> periodically indicates the increase or decrease of the delay amount with respect to the reference clock clk_ref.

FIG. 3 is a detailed configuration diagram of the clock divider shown in FIG. 2 and illustrates a clock divider configured to output one of clocks generated by dividing a reference clock into two, four, eight, and 16 divisions as a divided clock. It is shown as. In the clock divider to be implemented by the present invention, it is apparent that the division ratio and the number of clocks generated by the division are not limited to those shown in the drawings.

As illustrated, the clock divider 210 divides the two-division clock (clk_div2), the four-division clock (clk_div4), and the eight-division clock (clk_div8) from the reference clock clk_ref in response to the first reset signal rst1. And the reference clock (clk_ref), the two-division clock (clk_div2), the four-division clock (clk_div4), and the response in response to the division clock generator 212 and the selection signal sel, which generate the sixteenth division clock clk_div16. And a switching unit 214 which selects one of an eight divided clock clk_div8 and the sixteen divided clock clk_div16 and outputs the divided clock as a divided clock clk_div.

Here, the divided clock generator 212 divides the reference clock clk_ref by two in response to the first reset signal rst1 to generate the two divided clock clk_div2, and A second divider DIV2 for dividing the second divided clock clk_div2 in two to generate the fourth divided clock clk_div4 in response to the first reset signal rst1 and a response to the first reset signal rst1; By dividing the fourth divided clock clk_div4 by two to generate the eighth divided clock clk_div8 and the eighth divided clock clk_div in response to the first reset signal rst1. And a fourth divider DIV4 dividing to generate the 16 divided clock clk_div.

The selection signal sel is implemented through a test signal during a test operation. When the test operation is completed, the level is artificially fixed through a mode register or a fuse circuit. The switching unit 214 may be implemented in the form of a mux circuit controlled by the selection signal (sel), this configuration corresponds to a level of technology that can be easily implemented by those skilled in the art.

FIG. 4 is a detailed configuration diagram of the frequency control signal generation unit shown in FIG. 2, which illustrates that the frequency control signal is implemented as a 6-bit signal.

The frequency control signal generator 220 inverts the feedback signal ivfdb and the 6-bit frequency control signal fqcnt <1: 6> in response to the second reset signal rst2 and the divided clock clk_div. A shifting unit 222 for shifting 5 bits fqcnt <1: 5> to adjust a logic value of the 6-bit frequency control signal fqcnt <1: 6> and the 6-bit frequency control signal fqcnt And an inverting unit 224 that inverts the signal fqcnt <6> of the sixth bit among <1: 6> and outputs the inverted feedback signal ivfdb.

Here, the shifting unit 222 generates the frequency control signal 1 (fqcnt <1>) by latching the inverted feedback signal ivfdb in response to the second reset signal rst2 and the divided clock clk_div. The frequency control signal 1 (fqcnt <1>) is latched in response to the first flip-flop FF1, the second reset signal rst2, and the divided clock clk_div. Frequency control signal 3 (fqcnt <2>) by latching the frequency control signal 2 (fqcnt <2>) in response to the second flip-flop FF2, the second reset signal rst2, and the divided clock clk_div, which generates Latching the frequency control signal 3 (fqcnt <1: n>) in response to the third flip-flop FF3, the second reset signal rst2, and the divided clock clk_div, which generate the < 3 > Respond to a fourth flip-flop FF4, the second reset signal rst2, and the frequency division clock clk_div, which generates a frequency control signal 4 (fqcnt <4>). The fifth flip-flop FF5 and the second reset signal rst2 and the divided clock to latch the frequency control signal 4 (fqcnt <1: n>) to generate the frequency control signal 5 (fqcnt <5>). and a sixth flip-flop FF6 which latches the frequency control signal 5 (fqcnt <5>) in response to (clk_div) to generate the frequency control signal 6 (fqcnt <6>).

The inverting unit 224 includes a first inverter IV1 that inverts the frequency control signal 6 (fqcnt <6>) and outputs the inverted feedback signal ivfdb.

In the initial state, assuming that the 6-bit frequency control signals fqcnt <1: 6> are all at low level, the inversion feedback signal ivfdb has a high level potential. Thereafter, the first to sixth flip-flops FF1 to FF6 of the shifting unit 222 shift the high level inversion feedback signal ivfdb by one bit in synchronization with the toggle timing of the divided clock clk_div. do. Accordingly, the level of the 6-bit frequency control signal fqcnt <1: 6> is shifted by one bit. The potential level change of the frequency control signal fqcnt <1: 6> is shown in FIG. 5.

5 is a waveform diagram of a frequency control signal output from the frequency control signal generator of FIG. 4.

Referring to the figure, it can be seen that the frequency control signal fqcnt <1: 6> of 6 bits is shifted from low level to high level by one bit at each toggle timing of the divided clock clk_div. After all of the 6-bit frequency control signals fqcnt <1: 6> have reached a high level, a level transition from a high level to a low level occurs one bit at a time. That is, the logic value of the 6-bit frequency control signal fqcnt <1: 6> is shifted by one bit at each toggle timing of the divided clock clk_div. As such, the level of the 6-bit frequency control signal fqcnt <1: 6> is changed periodically.

FIG. 6 is a detailed configuration diagram of the frequency adjuster illustrated in FIG. 2 and exemplarily shows a frequency adjuster that operates in response to a 6-bit frequency control signal fqcnt <1: 6>.

As illustrated, the frequency adjusting unit 230 drives the reference clock clk_ref to generate the frequency adjusting clock clk_adf, and the 6-bit frequency control signal fqcnt <1: 6>. A delay unit 234 for delaying the operation of the driving unit 232 in response to.

Here, the driver 232 drives the output signal of the second inverter IV2 and the second inverter IV2 driving the reference clock clk_ref to output the frequency adjustment clock clk_adf. (IV3).

The delay unit 234 has a first stage connected between the second inverter IV2 and the third inverter IV3, and the second stage has the six-bit frequency control signal fqcnt <1: 6. And first to sixth capacitors CAP1 to CAP6 inputted by bit.

As illustrated, the first to third capacitors CAP1 to CAP3 are PMOS type capacitors, and the fourth to sixth capacitors CAP4 to CAP6 are NMOS type capacitors.

In the frequency adjusting unit 230 configured as described above, the delay value of the delay unit 234 when all of the 6-bit frequency control signals fqcnt <1: 6> are at a low level is set to a default value. In this case, the delay operation is performed by the first to third capacitors CAP1 to CAP3. That is, the frequency adjustment clock clk_adf is given a delay time by three capacitors.

Subsequently, when the six-bit frequency control signal fqcnt <1: 6> starts to transition to the high level by one bit, the first to third capacitors CAP1 to CAP3 of the delay unit 234 are displayed one by one. Able to be. If the operation that the 6-bit frequency control signal fqcnt <1: 6> transitions to the high level by one bit is continued, the fourth to sixth capacitors CAP4 to CAP6 of the delay unit 234 are one by one. Is enabled. Thereafter, when the six-bit frequency control signal fqcnt <1: 6> transitions to the low level by one bit again, the first to third capacitors CAP1 to CAP3 are enabled one by one, and then the fourth The sixth capacitors CAP4 to CAP6 are disabled one by one. That is, as the six-bit frequency control signal fqcnt <1: 6> periodically shifts by one bit, the delay unit 234 may be connected to the reference clock clk_ref driven by the driver 232. The delay amount is increased or decreased periodically. Accordingly, the frequency adjusting clock clk_adf is implemented as a clock whose frequency increases or decreases periodically, so that the DLL circuit can reduce the electromagnetic interference than when using a clock having a fixed frequency.

7 to 9 are diagrams for explaining the operation of the DLL circuit according to an embodiment of the present invention.

In Fig. 7, (A) shows the concentration of the output clock (clk_out) in the DLL circuit without using the frequency adjusting device of the present invention, (B) shows the output clock (in the DLL circuit using the frequency adjusting device of the present invention). clk_out). Here, the rated period of the output clock clk_out is 500 psec.

In FIG. 7, (A) shows that the period of the output clock clk_out is further concentrated at 500psec, and (B) shows that the period of the output clock clk_out is further dispersed from 500psec. As shown in (A), the more the clock cycle is concentrated on the rated cycle, the higher the probability of electromagnetic interference occurs. However, due to the implementation of the present invention, if the clock period is dispersed from the rated period as shown in (B), the probability of occurrence of electromagnetic interference is low.

8 and 9 show the results of experiments comparing the prior art and the present invention, respectively. 8 and 9 show jitter characteristics of a clock with respect to time at different angles. Compared to the clock in the DLL circuit to which the prior art is applied, the clock in the DLL circuit in which the frequency adjustment device of the present invention is implemented has a larger amount of jitter change.

As described above, the frequency adjusting device of the present invention and the DLL circuit including the same periodically increase or decrease the frequency of the reference clock to prevent the output clock from accurately having a rated period. Therefore, it is possible to prevent electronic interference occurring in the DLL circuit and the semiconductor integrated circuit, and to support stable operation of the semiconductor integrated circuit.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The frequency adjusting device and the DLL circuit including the same of the present invention described above have the effect of reducing the electromagnetic interference of the semiconductor integrated circuit by periodically increasing or decreasing the frequency of the output clock.

In addition, the frequency adjusting device of the present invention and the DLL circuit including the same have an effect of reducing the occurrence probability of the electromagnetic interference phenomenon to support more stable operation of the semiconductor integrated circuit.

Claims (17)

A frequency control signal generator for generating a plurality of bits of the frequency control signal for level shifting by one bit in response to the first clock; And A frequency adjusting unit adjusting a frequency of an input reference clock in response to the plurality of bits of the frequency control signal; Frequency adjusting device comprising a. The method of claim 1, And the frequency control signal generator is configured to periodically increase or decrease the number of high signals included in the plurality of bits of the frequency control signal in synchronization with the toggle timing of the first clock. The method of claim 2, The frequency control signal generator, A shifting unit configured to adjust a logic value of the frequency control signal of the plurality of bits by shifting the inverted feedback signal and the frequency control signal of the plurality of bits in response to a reset signal and the first clock; And An inversion unit inverting any one of the plurality of frequency control signals and outputting the inverted feedback signal; Frequency adjusting device comprising a. The method of claim 2, And the frequency adjusting unit periodically increases or decreases a delay time applied to the reference clock in response to a periodic change in the logic value of the frequency control signal. The method of claim 4, wherein The frequency adjusting unit, A driving unit driving the reference clock to generate the frequency adjustment clock; And A delay unit delaying the operation of the driver in response to the plurality of bits of the frequency control signal; Frequency adjusting device comprising a. The method of claim 1, And a clock divider configured to divide the frequency of the reference clock to generate a divided clock. The method of claim 6, The clock division unit, The clock division unit, A division clock generation unit configured to generate a plurality of division clocks having respective division ratios from the reference clock in response to a reset signal; And A switching unit which selects one of the reference clock and the plurality of divided clocks as the first clock in response to a selection signal; Frequency adjusting device comprising a. The method of claim 7, wherein The selection signal is implemented as a signal in the form of a form that is implemented through a test signal during a test operation, and the level is fixed through a mode register or a fuse circuit when the test operation is terminated. a) dividing the reference clock at a predetermined rate to generate a divided clock; b) periodically changing a logic value of a plurality of bits of the frequency control signal in response to the division clock; And c) giving the reference clock a delay time corresponding to a logic value of the plurality of bits of the frequency control signal; Frequency adjustment method comprising a. The method of claim 9, Step a) is a-1) generating a plurality of divided clocks having respective division ratios from the reference clock in response to a reset signal; And a-2) selecting and outputting any one of the reference clock and the plurality of divided clocks in response to a selection signal; Frequency adjustment method comprising a. The method of claim 10, The selection signal is implemented as a signal in a form in which a level is fixed through a mode signal or a fuse circuit when the test operation is implemented through the test signal and the test operation is completed. The method of claim 9, B), b-1) inverting any one of the plurality of bits of the frequency control signal and outputting the inverted feedback signal; And b-1) shifting the inversion feedback signal and the frequency control signal of the plurality of bits in response to a reset signal and the division clock to adjust a logic value of the frequency control signal of the plurality of bits; Frequency adjustment method comprising a. A frequency adjusting device for generating a frequency adjusting clock by periodically increasing or decreasing the frequency of the reference clock; A delay device generating a delay clock by delaying the frequency adjustment clock in response to a delay control signal; A delay compensation device for generating a feedback clock by giving a delay time of the delay amount of the output path of the delay clock to the delay clock; A phase comparison device configured to generate a phase comparison signal by comparing phases of the reference clock and the feedback clock; And A delay control device generating the delay control signal in response to the phase comparison signal; DLL (Delay Locked Loop) circuit, characterized in that it comprises a. The method of claim 13, The frequency adjustment device, A clock divider for dividing a frequency of the reference clock to generate a divided clock; A frequency control signal generator for generating a plurality of bits of the frequency control signal for level shifting by one bit in response to the division clock; And A frequency adjusting unit generating the frequency adjusting clock by adjusting a frequency of the reference clock in response to the plurality of bits of the frequency control signal; DLL circuit comprising a. The method of claim 14, And the frequency control signal generation unit periodically increases or decreases the number of high signals included in the plurality of bits of the frequency control signal in synchronization with the toggle timing of the divided clock. The method of claim 14, And the frequency adjusting unit periodically increases or decreases a delay time applied to the reference clock in response to a periodic change in the logic value of the frequency control signal. The method of claim 13, And a clock input buffer for buffering an external clock to generate the reference clock.

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