KR20080105937A - Display device and method of fabricating the same - Google Patents

Abstract

A display device is provided to prevent the disconnection or short of a wiring during emitting light to a sealing member by forming a transparent contact which is connected to a first signal transmitting wiring and a second signal transmitting wiring. A sealing member(600) is interposed between a substrate(100) and an opposing board(200) which is faced with substrate. A first signal transmitting wiring(300) is arranged in the sealing area sealed by the opposing board and sealing member. A second signal transmitting wiring(400) is arranged in the non-display area covering the surrounding of the sealing area. A transparent contact element(500) is electrically connected to the first signal transmitting wiring and the second signal transmitting wiring.

Description

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

1 is a plan view showing a TN type liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3A to 3D are cross-sectional views showing a process by a method of manufacturing a TN type liquid crystal display device.

4 is a plan view showing a transverse electric field type liquid crystal display device according to a third exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 4.

7 is a plan view showing an organic light emitting display device according to a fifth embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along lines III-III ′ and IV-IV ′ of FIG. 7.

9A to 9D are cross-sectional views illustrating a process of a method of manufacturing a display device according to a sixth embodiment of the present invention.

10 is a plan view showing an organic light emitting display device according to a seventh embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along lines VV and VIV in FIG. 10.

12A to 12D are cross-sectional views illustrating processes in a method of manufacturing a display device according to an eighth embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

100: substrate 110: gate wiring

160: data wiring 150: channel pattern

180 pixel electrode 181 first electrode

183: connecting electrode 200: counter substrate

300: first signal relay wiring 400: second signal relay wiring

500: transparent contact portion 600: sealing member

The present invention relates to a display device.

Recently, with the development of manufacturing technology of semiconductor devices such as thin film transistors, the development of technology of information processing devices such as mobile phones, computers, and MP3 players is rapidly progressing. In recent years, technology development of a display device for recognizing data processed by an information processing device has been rapidly progressing.

Examples of the display device include a liquid crystal display device (LCD), an organic electroluminescent display (OLED), a plasma display device (PDP), and the like.

The display device includes two substrates, a wiring for displaying an image interposed between the two substrates, a thin film transistor (TFT), and an electrode. The display device includes two substrates and a sealing area that is blocked from the outside by the sealing member. Wiring, a thin film transistor, and an electrode are disposed in the sealing area, and wiring for relaying a signal for displaying an image in the sealing area is interposed between the two substrates.

In order to form the display device, it is necessary to combine two substrates by a sealing member. At this time, the sealing member is disposed between the two substrates, and the two members are joined by curing the sealing member by irradiating ultraviolet rays (UV) or lasers.

In this case, in the process of irradiating an ultraviolet ray or a laser to the sealing member, a wire relaying a signal to the display element may be disconnected or shorted.

An object of the present invention is to intersect the sealing member, by arranging a transparent contact portion electrically connected to the first signal relay wiring and the second signal relay wiring, the wiring is disconnected or shorted in the process of irradiating light to the sealing member. It is to provide a display device for preventing.

It is still another object of the present invention to provide a method for manufacturing a display device which prevents disconnection and short circuit of wiring.

The display device of the present invention for realizing one object of the present invention comprises a sealing member interposed between a substrate, the substrate and an opposite substrate disposed to face the substrate, the substrate, the opposite substrate and the sealing member. A first signal relay wiring disposed in a sealed region sealed by the second signal relay wiring, a second signal relay wiring disposed in a non-display area surrounding the sealing region and spaced apart from the first signal relay wiring, and the first signal relay wiring; And a transparent contact part electrically connected to the second signal relay wiring.

In addition, the method of manufacturing a display device of the present invention for implementing another object of the present invention comprises the steps of forming a first signal relay wiring and a second signal relay wiring spaced apart from the first signal relay wiring on the substrate, Forming a transparent contact portion electrically connected to the first signal relay line and the second signal relay line; and a sealing member for separating the sealing area from the non-display area on the substrate, the first signal relay line and the second signal. It disposed between the relay wiring.

Hereinafter, a display device and a method of manufacturing the display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and the general knowledge in the art. Those having the present invention can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Example 1

1 is a plan view showing a TN type liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1. Although the counter substrate is not shown in FIG. 1, the counter substrate corresponding to the board is shown in FIG.

1 and 2, a TN type liquid crystal display device includes a substrate 100, a gate wiring 110, an insulating film 140, a data wiring 160, a thin film transistor TR, a protective film 170, and a pixel electrode. 180, an opposing substrate 200, a first signal relay 300, a second signal relay 400, a transparent contact portion 500, a sealing member 600, and a liquid crystal layer 700.

The substrate 100 is divided into a sealing area and a non-display area by the sealing member 600 which will be described later. The sealing region is sealed by the substrate 100, the sealing member 600, and the counter substrate 200, which will be described later, and the non-display region is formed surrounding the sealing region. The substrate 100 is a transparent insulator. The substrate 100 is, for example, a glass substrate or a quartz substrate.

The gate wiring 110 is disposed on the substrate 100 in the first direction. In addition, the gate wiring 110 is disposed in the sealing region. Examples of the material that can be used as the gate wiring 110 include aluminum (Al), aluminum alloy, copper (Cu) and molybdenum (Mo) and titanium (Ti).

The insulating layer 140 covers the gate wiring 110, the first gate signal relay wiring 310 to be described later, and the second gate signal relay wiring 510 to be described later, and is formed on the substrate 100. Examples of the material that can be used as the insulating layer 140 include silicon oxide (SiOx) and silicon nitride (SiNx).

The data line 160 is disposed in the second direction on the insulating layer 140. The data line is arranged in the sealing area. Examples of materials that can be used as the data wiring 160 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The thin film transistor TR is disposed on the substrate 100. The thin film transistor TR includes a gate electrode 111, a channel pattern 150, a source electrode 161, and a drain electrode 162.

The gate electrode 111 is branched from the gate wiring 110. The gate electrode 111 is formed integrally with the gate wiring 110.

The channel pattern 150 is disposed on the insulating layer 140. The channel pattern 150 is disposed corresponding to the gate electrode 111, and the channel pattern 150 includes an amorphous silicon pattern 151 and an n + amorphous silicon pattern 152. The material used for the amorphous silicon pattern 151 is amorphous silicon, and the material used for the n + amorphous silicon pattern 152 is amorphous silicon implanted with a high concentration of impurities. The amorphous silicon pattern 150 is disposed on the insulating layer 140 in correspondence with the gate electrode 111, and a pair of n + amorphous silicon patterns 152 are spaced apart from each other at predetermined intervals, thereby forming the amorphous silicon pattern 151 on the amorphous silicon pattern 151. Is placed on.

The source electrode 161 is branched from the data line 160, and the source electrode 161 is formed integrally with the data line 160. The source electrode 161 is in contact with one of the pair of n + amorphous silicon patterns 152.

The drain electrode 162 is spaced apart from the source electrode 161 at a predetermined interval. The drain electrode 162 is in contact with the other of the pair of n + amorphous silicon patterns 152. Examples of materials that can be used as the drain electrode 162 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The passivation layer 170 covers the data line 160, the drain electrode 162, the first data signal relay wiring 320 to be described later, and the second data signal relay wiring 520 to be described later. The passivation layer 170 includes a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, and a fifth contact hole 175. The first contact hole 171 exposes a portion of the drain electrode 162. The second contact hole 172 exposes a portion of the first gate signal relay wiring 310. The third contact hole 173 exposes a portion of the second gate signal relay wiring 510. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 520. Examples of the material that can be used as the protective film 170 include silicon oxide, silicon nitride, and the like.

The pixel electrode 180 is disposed on the passivation layer 170. The pixel electrode 180 is electrically connected to the drain electrode 162 partially exposed by the first contact hole 171. Indium tin oxide (ITO), indium zinc oxide (IZO), and the like may be used as examples of materials that may be used as the pixel electrode 180.

The first signal relay line 300 is disposed in the sealing area. Examples of materials that may be used as the first signal relay 300 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like. The first signal relay wiring 300 includes a first gate signal relay wiring 310 and a first data signal relay wiring 320.

The first gate signal relay wiring 310 is electrically connected to the gate wiring 110. The first gate signal relay wiring 310 may be formed on the same layer as the gate wiring 110. The first gate signal relay wiring 310 may be integrally formed with the gate wiring 110.

The first data signal relay wiring 320 is electrically connected to the data wiring 160. The first data signal relay wiring 320 may be formed on the same layer as the data wiring 160. The first data signal relay wiring 320 may be integrally formed with the data wiring 160.

The second signal relay wiring 400 is disposed in the non-display area. The second signal relay wiring 400 is spaced apart from the first signal relay wiring 300 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm. The second signal relay 400 includes a second gate signal relay 410 and a second data signal relay 420. Examples of materials that may be used as the second signal relay 400 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The second gate signal relay wiring 410 is spaced apart from the first gate signal relay wiring 310 at predetermined intervals. The second gate signal relay wiring 410 may be formed on the same layer as the first gate signal relay wiring 310. The second gate signal relay wiring 410 is electrically connected to the gate driving IC 800.

The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 320 at predetermined intervals. The second data signal relay wiring 420 may be formed on the same layer as the first data signal relay wiring 320. The second data signal relay wiring 420 is electrically connected to the data driver IC 900.

The transparent contact unit 500 is electrically connected to the first signal relay line 300 and the second signal relay line 400. The transparent contact portion 500 is disposed on the passivation layer 170. Examples of the material that can be used as the transparent contact portion 500 include indium tin oxide, indium zinc oxide, and the like. The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520.

The first transparent contact portion 510 is a second gate signal relay partially exposed by the first gate signal relay wiring 310 and the third contact hole 173 exposed by the second contact hole 172. It is electrically connected to the wiring 410. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410.

The second transparent contact unit 520 relays the second data signal relay partially exposed by the first data signal relay wiring 320 and the fifth contact hole 175 partially exposed by the fourth contact hole 174. It is electrically connected to the wiring 420. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

The sealing member 600 has a closed loop shape and is disposed on the passivation layer 170. The sealing member 600 is interposed between the substrate 100 and the counter substrate 200 to be described later. By the sealing member 600, the substrate 100, and the opposing substrate 200, a sealing region sealed to the outside is formed. A non-display area is formed around the sealing area. The sealing member 600 intersects with the transparent contact portion 500. Examples of the material that can be used as the sealing member 600 include a photocurable resin, a thermosetting resin, and the like.

The sealing member 600 and the transparent contact portion 500 are arranged to cross. Since the transparent contact portion 500 is transparent, the light passes through the transparent contact portion 500 when light is irradiated to the sealing member 600. Therefore, the transparent contact portion 500 is not disconnected or shorted in the process of irradiating the sealing member 600 with light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the adhesion between the sealing member 600 and the substrate 100 may be enhanced. The light can be, for example, ultraviolet or laser.

The opposite substrate 200 is disposed to face the substrate 100. The counter substrate 200 may include a black matrix pattern having a lattice structure having openings when viewed in a plan view, a color filter disposed in the openings, and a common electrode to which a common voltage is applied.

The liquid crystal layer 700 is disposed in the sealing region between the substrate 100 and the counter substrate 200. The liquid crystal layer 700 includes liquid crystals (LCs), and the liquid crystals are aligned by an electric field formed between the pixel electrode 180 and the common electrode, and the aligned liquid crystals pass through the liquid crystal layer 700. Adjust the light intensity.

Example 2

3A to 3D are cross-sectional views showing a process by a method of manufacturing a TN type liquid crystal display device.

Referring to FIG. 3A, a gate wiring 110, a gate electrode 111, a first gate signal relay wiring 310, and a second gate signal relay wiring 410 are formed on the substrate 100.

In order to form the gate wiring 110, the gate electrode 111, the first gate signal relay wiring 310, and the second gate signal relay wiring 410, a metal film is formed over the entire surface of the substrate 100. . The substrate 100 is, for example, a glass substrate or a quartz substrate. The metal film may be formed by, for example, a chemical vapor deposition process (CVD) or a sputtering process. Examples of the material forming the metal film include aluminum, aluminum alloy, copper, molybdenum, titanium, and the like.

On the metal film, a photoresist film is formed over the entire area. The photoresist film may be formed by, for example, a slit coating process or a spin process. The photoresist film is patterned through a photo process including an exposure process and a developing process, and on the metal layer, the photoresist film is formed on the gate wiring 110, the first gate signal relay wiring 310, and the second gate signal relay wiring 410. A photoresist pattern having a corresponding shape is formed.

The metal layer is patterned using the photoresist pattern as an etch mask, and a gate wiring 110, a first gate signal relay wiring 310, and a second gate signal relay wiring 410 are formed on the substrate 100. . The gate electrode 111 is formed branched from the gate wiring 110. The first gate signal line 310 and the second gate signal line 410 may be spaced apart at predetermined intervals, and the interval may be about 1 mm to about 2 mm.

After the gate wiring 110, the first gate signal relay wiring 310, and the second gate signal relay wiring 410 are formed, an insulating layer 140 is formed on the substrate 100 over the entire area. Examples of the material that can be used as the insulating film 140 include silicon oxide, silicon nitride, and the like.

Referring to FIG. 3B, after the insulating layer 140 is formed, a channel pattern 150 is formed on the insulating layer 140.

In order to form the channel pattern 150, an amorphous silicon thin film made of amorphous silicon and an n + amorphous silicon thin film made of amorphous silicon implanted with a high concentration of impurities are sequentially formed on the insulating layer 140. A photoresist film is formed over the entire surface of the n + amorphous silicon thin film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern corresponding to the channel pattern 150 is formed on the n + amorphous silicon thin film. The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the photoresist pattern as an etching mask, and a channel pattern 150 is formed on the insulating layer 140.

The channel pattern 150 is formed corresponding to the gate electrode 111. The channel pattern 150 includes an amorphous silicon pattern 151 and an n + amorphous silicon pattern 152. The amorphous silicon pattern 151 is formed on the insulating layer 140, and the n + amorphous silicon pattern 152 is formed on the amorphous silicon pattern 151 by spaced apart from each other by a predetermined interval.

After the channel pattern 150 is formed, the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring are formed on the insulating layer 140. 420 is formed.

In order to form the data wire 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420, the insulating film 140 and the channel pattern ( On the source 150, a source / drain metal film is formed over the entire area. The source / drain metal film may be formed by, for example, a chemical vapor deposition process or a sputtering process. Examples of the material that can be used as the source / drain metal film include aluminum, aluminum alloy, copper, molybdenum and titanium.

On the source / drain metal film, a photoresist film is formed over the entire area. The photoresist film is patterned through a photo process including an exposure process and a developing process, so that the data wire 160, the source electrode 161, the drain electrode 162, and the first data signal are formed on the source / drain metal film. A photoresist pattern corresponding to the relay wiring 320 and the second data signal relay wiring 420 is formed.

The source / drain metal layer is patterned by using the photoresist pattern as an etch mask, and the data line 160, the source electrode 161, the drain electrode 162, and the second layer are formed on the insulating layer 140 and the channel pattern 150. The first data signal relay wiring 320 and the second data signal relay wiring 420 are formed.

The data line 160 crosses the gate line 110 in the second direction. The source electrode 161 branches from the data line 160 and contacts one of the pair of n + amorphous silicon patterns 152. The drain electrode 162 is spaced apart from the source electrode 161 at predetermined intervals, and contacts the other one of the pair of n + amorphous silicon patterns 152.

The first data signal relay wiring 320 is integrally formed with the data wiring 160. The first data signal relay wiring 320 is spaced apart from the second data signal relay wiring 420 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm.

Referring to FIG. 3C, after the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420 are formed, the substrate 100 is formed. The passivation layer 170 is formed on the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420.

In order to form the passivation layer 170, the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data are disposed on the substrate 100 over the entire area. An inorganic film covering the signal relay wiring 420 is formed. Examples of the material that can be used as the inorganic film include silicon oxide and silicon nitride.

After the inorganic film is formed, a photoresist film is formed on the inorganic film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern is formed on the inorganic film. The photoresist pattern may include a portion of the drain electrode 162, a portion of the first gate signal relay wiring 310, a portion of the second gate signal relay wiring 410, a portion of the first data signal relay wiring 320, and a first portion thereof. 2 The inorganic film corresponding to a part of the data signal relay wiring 420 is exposed.

The inorganic layer is patterned by using the photoresist pattern as an etching mask. In this case, an insulating layer corresponding to a portion of the first gate signal relay wiring 310 and a portion of the second gate signal relay wiring 410 is etched and patterned. The passivation layer 170 is formed on the substrate 100.

The passivation layer 170 includes a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, and a fifth contact hole 175. The first contact hole 171 exposes a portion of the drain electrode 162, and the second contact hole 172 exposes a portion of the first gate signal relay wiring 310. The third contact hole 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420.

After the passivation layer 170 is formed, the pixel electrode 180 and the transparent contact portion 500 are formed on the passivation layer 170. In order to form the pixel electrode 180 and the transparent contact portion 500, a transparent conductive metal film is formed on the protective film 170 over the entire area. The transparent conductive metal film may be formed by, for example, a chemical vapor deposition process or a sputtering process. Examples of the material that can be used as the transparent conductive metal film include indium tin oxide, indium zinc oxide, and the like.

After the transparent conductive metal film is formed, a photoresist film is formed on the transparent conductive metal film over the entire area. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern corresponding to the pixel electrode 180 and the transparent contact portion 500 is formed on the transparent conductive metal film. The transparent conductive metal layer is patterned using the photoresist pattern as an etching mask, and the pixel electrode 180 and the transparent contact portion 500 are formed on the passivation layer 170.

The pixel electrode 180 is electrically connected to the drain electrode 162 partially exposed by the first contact hole 171. The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520. The first transparent contact portion 510 is electrically connected to the first gate signal relay wiring 310 partially exposed by the second contact hole 172. The first transparent contact portion 510 is electrically connected to the second gate signal relay wiring 410 partially exposed by the third contact hole 173. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410. The second transparent contact portion 320 is electrically connected to the first data signal relay wiring 320 partially exposed by the fourth contact hole 174. The second transparent contact portion 520 is electrically connected to the second data signal relay wiring 420 partially exposed by the fifth contact hole 175. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

Referring to FIG. 3D, after the pixel electrode 180 and the transparent contact portion 500 are formed, the sealing member 600 is disposed on the substrate 100. The sealing member 600 is disposed on the substrate 100 in a closed loop shape, and the sealing member 600 intersects with the transparent contact portion 500 and is disposed at the end of the first signal relay wiring 300 and the first. The second signal relay wiring 400 corresponding to the signal relay wiring 300 is disposed between the ends.

After the sealing member 600 is disposed, the alignment layer is formed on the substrate 100, and the liquid crystal layer 700 is formed.

After the liquid crystal layer 700 is formed, an opposing substrate 200 facing the substrate 100 is disposed on the sealing member 600. After the opposing substrate 200 is disposed, light passing through the substrate 100 is irradiated to the sealing member 600, and light passing through the opposing substrate 200 is irradiated to the sealing member 600. The sealing member 600 is cured by the light, and the substrate 100 and the counter substrate 200 are bonded by the sealing member 600. The sealing region is formed by the substrate 100, the counter substrate 200, and the sealing member 600.

At this time, the sealing member 600 is cured by the light passing through the substrate 100, and at the same time, the sealing member 600 is cured by the light passing through the counter substrate 200. Since the sealing member 600 intersects with the transparent contact portion 500 and the transparent contact portion 500 is transparent, when the light is irradiated to the sealing member 600, the light is transferred to the transparent contact portion 500. To pass. Therefore, the transparent contact portion 500 is not disconnected or shorted. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the bonding force between the sealing member 600 and the substrate 100 is increased. The light can be, for example, ultraviolet or laser.

Example 3

4 is a plan view showing a transverse electric field type liquid crystal display device according to a third exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 4. Although the counter substrate is not shown in FIG. 4, the counter substrate corresponding to the board is shown in FIG. 5.

4 and 5, a transverse electric field type liquid crystal display device includes a substrate 100, a gate wiring 110, a common wiring 120, an insulating film 140, a data wiring 160, a thin film transistor TR, and a protective film. 170, the pixel electrode 180, the first signal relay line 300, the second signal relay line 400, the common signal relay line 330, the transparent contact unit 500, the sealing member 600, and the opposite side. The substrate 200 and the liquid crystal layer 700 are included.

The substrate 100 is divided into a sealing area and a non-display area by the sealing member 600 which will be described later. The sealing region is sealed by the substrate 100, the sealing member 600, and the counter substrate 200, which will be described later, and the non-display region is formed surrounding the sealing region. The substrate 100 is a transparent insulator. The substrate 100 may be, for example, a glass substrate or a quartz substrate.

The gate wiring 110 is disposed on the substrate 100 in the first direction. In addition, the gate wiring 110 is disposed in the sealing region. Examples of materials that can be used as the gate wiring 110 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The common wiring 120 is disposed on the substrate 100 in a first direction parallel to the gate wiring 110. The common wiring 120 includes a common electrode 121 branched from the common wiring 120. The common electrode 121 is alternately disposed with the pixel electrode 180, which will be described later. Examples of materials that can be used as the common wiring 120 include aluminum, aluminum alloys, copper molybdenum, titanium, and the like.

The insulating layer 140 covers the gate wiring 110, the gate electrode 111, the common wiring 120, the first gate signal relay wiring 310 to be described later, and the second gate signal relay wiring 320 to be described later. It is formed on the substrate 100. Examples of the material that can be used as the insulating film 140 include silicon oxide, silicon nitride, and the like.

The data line 160 is disposed in the second direction on the insulating layer 140. The data line 160 is disposed in the sealing area. Examples of materials that can be used as the data wiring 160 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The thin film transistor TR is electrically connected to the data line 160, and the thin film transistor TR includes a gate electrode 110, a channel pattern 150, a source electrode 161, and a drain electrode 162.

The gate electrode 111 is branched from the gate wiring 110. The gate electrode 111 is integrally formed with the gate wiring 110 on the substrate 100.

The channel pattern 150 is disposed on the insulating layer 140. The channel pattern 150 is disposed corresponding to the gate electrode 111, and the channel pattern 150 includes an amorphous silicon pattern 151 and an n + amorphous silicon pattern 152. A material used as the amorphous silicon pattern 151 is amorphous silicon, and a material used as the n + amorphous silicon pattern 152 is amorphous silicon implanted with a high concentration of impurities. The amorphous silicon pattern 151 is disposed on the insulating layer 140 in correspondence with the gate electrode 111, and a pair of n + amorphous silicon patterns 152 are spaced apart from each other at predetermined intervals, thereby forming the amorphous silicon pattern 151 on the amorphous silicon pattern 151. Is placed on.

The source electrode 161 is branched from the data line 160, and the source electrode 161 is formed on the insulating layer 140 integrally with the data line 160. The source electrode 161 is in contact with one of the pair of n + amorphous silicon patterns 152.

The drain electrodes 162 are spaced apart from the source electrode 161 at predetermined intervals. The drain electrode 162 is in contact with the other of the pair of n + amorphous silicon patterns 152. Examples of materials that can be used as the drain electrode 162 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The passivation layer 170 covers the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 to be described later, and the second data signal relay wiring 420 to be described later. The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176). The first contact hole 171 exposes a portion of the drain electrode 162. The second contact hole 172 exposes a portion of the first gate signal relay wiring 310. The third contact hole 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a part of the common wiring 120. Examples of the material that can be used as the protective film 170 include silicon oxide, silicon nitride, and the like.

The pixel electrode 180 is disposed on the passivation layer 170. The pixel electrode 180 is electrically connected to the drain electrode 162 partially exposed by the first contact hole 171. Examples of materials that may be used as the pixel electrode 180 include indium tin oxide, indium zinc oxide, and the like. The pixel electrode 180 may have a comb shape when viewed in a plan view, and the pixel electrode 180 may be alternately formed with the common electrode 121. In addition, the pixel electrode 180 may be formed in a zigzag shape when viewed in a plan view.

The first signal relay line 300 is disposed in the sealing area. Examples of materials that may be used as the first signal relay 300 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like. The first signal relay wiring 300 includes a first gate signal relay wiring 310 and a first data signal relay wiring 320.

The first gate signal relay wiring 310 is electrically connected to the gate wiring 110. The first gate signal relay wiring 310 may be formed on the same layer as the gate wiring 110. The first gate signal relay wiring 310 may be integrally formed with the gate wiring 110.

The first data signal relay wiring 320 is electrically connected to the data wiring 160. The first data signal relay wiring 320 may be formed on the same layer as the data wiring 160. The first data signal relay wiring 320 may be integrally formed with the data wiring 160.

The second signal relay wiring 400 is disposed in the non-display area. The second signal relay wiring 400 is spaced apart from the first signal relay wiring 300 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm. The second signal relay 400 includes a second gate signal relay 410 and a second data signal relay 420. Examples of materials that may be used as the second signal relay 400 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The second gate signal relay wiring 410 is spaced apart from the first gate signal relay wiring 310 at predetermined intervals. The second gate signal relay wiring 410 may be formed on the same layer as the first gate signal relay wiring 310. The second gate signal relay wiring 410 is electrically connected to the gate driving IC 800.

The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 320 at predetermined intervals. The second data signal relay wiring 420 may be formed on the same layer as the first data signal relay wiring 320. The second data signal relay wiring 420 is electrically connected to the data driver IC 900.

The common signal relay wiring 330 is disposed on the passivation layer 170. The common signal relay wiring 330 is electrically connected to the common wiring 120 partially exposed through the sixth contact hole 176. The common voltage is applied to the common electrode 121 through the common signal relay wiring 330 and the common wiring 120. Examples of materials that may be used as the common signal relay 330 include indium tin oxide, indium zinc oxide, and the like.

The transparent contact unit 500 is electrically connected to the first signal relay line 300 and the second signal relay line 400. That is, the transparent contact unit 500 electrically connects the first signal relay wiring 300 and the second signal relay wiring 400. The transparent contact portion 500 is disposed on the passivation layer 170. Examples of the material that can be used as the transparent contact portion 500 include indium tin oxide, indium zinc oxide, and the like. The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520.

The first transparent contact portion 510 is a second gate signal relay partially exposed by the first gate signal relay wiring 310 and the third contact hole 173 exposed by the second contact hole 172. It is electrically connected to the wiring 410. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410.

The second transparent contact unit 520 relays the second data signal relay partially exposed by the first data signal relay wiring 320 and the fifth contact hole 175 partially exposed by the fourth contact hole 174. It is electrically connected to the wiring 420. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

The sealing member 600 has a closed loop shape and is disposed on the passivation layer 170. By the sealing member 600, the substrate 100, and the counter substrate 200 to be described later, a sealing region sealed to the outside is formed. A non-display area is formed around the sealing area. The sealing member 600 is formed to intersect the transparent contact portion 500. Examples of the material that can be used as the sealing member 600 include a photocurable resin and a thermosetting resin.

The sealing member 600 and the transparent contact portion 500 are arranged to cross. Since the transparent contact part 500 is transparent, when light is irradiated to the sealing member 600, the light passes through the transparent contact part 500. Therefore, the transparent contact part 500 is not disconnected or shorted in the process of irradiating light to the sealing member 600. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the adhesion between the sealing member 600 and the substrate 100 may be enhanced. The light can be, for example, ultraviolet or laser.

The opposite substrate 200 is disposed to face the substrate 100. The counter substrate 200 may include a black matrix pattern having a lattice structure having openings when viewed in a plan view, and a color filter pattern disposed in the openings.

The liquid crystal layer 700 is disposed between the substrate 100 and the counter substrate 200. The liquid crystal layer 700 includes liquid crystals. The liquid crystals are aligned by an electric field formed between the pixel electrode 180 and the common electrode 130, and the aligned liquid crystals adjust the intensity of light passing through the liquid crystal layer 700.

Example 4

6A to 6D are cross-sectional views illustrating a process by a method of manufacturing a transverse electric field type liquid crystal display device.

Referring to FIG. 6A, the gate wiring 110, the gate electrode 111, the common wiring 120 having the common electrode 121, the first gate signal relay wiring 310, and the second gate are disposed on the substrate 100. The signal relay wiring 320 is formed.

In order to form the gate wiring 110, the gate electrode 111, the common wiring 120, the first gate signal relay wiring 310, and the second gate signal relay wiring 410, the substrate 100 may be formed on the substrate 100. A metal film is formed over. The substrate 100 may be, for example, a glass substrate or a quartz substrate. The metal film may be formed by, for example, a chemical vapor deposition process or a sputtering process. Examples of the material forming the metal film include aluminum, aluminum alloy, copper, molybdenum, titanium, and the like.

On the metal film, a photoresist film is formed over the entire area. The photoresist film may be formed by, for example, a slit coating process or a spin process. The photoresist film is patterned through a photo process including an exposure process and a development process, and on the metal layer, a gate wiring 110, a gate electrode 111, a common wiring 120, and a first gate signal relay wiring 310. ) And a photoresist pattern having a shape corresponding to the second gate signal relay wiring 410 is formed.

The metal layer is patterned using the photoresist pattern as an etch mask, and includes a gate wiring 110, a gate electrode 111, a common wiring 120, a first gate signal relay wiring 310, and a substrate on the substrate 100. The second gate signal relay wiring 320 is formed. The gate wiring 110 is formed in the first direction. The gate electrode 111 is formed branched from the gate wiring 110. The common wiring 120 is formed parallel to the gate wiring 110. The common electrode 121 is branched from the common wiring 120. The first gate signal wire 310 and the second gate signal wire 410 may be formed to be spaced apart from each other at predetermined intervals, and the interval may be about 1 mm to about 2 mm.

After the gate wiring 110, the gate electrode 111, the common wiring 120, the first gate signal relay wiring 310, and the second gate signal relay wiring 410 are formed, the gate wiring 110 is formed on the substrate 100. The insulating film 140 is formed over. The insulating layer 140 is formed to cover the gate wiring 110, the gate electrode 111, the common wiring 120, the first gate signal relay wiring 310, and the second gate signal relay wiring 410. Examples of the material that can be used as the insulating film 140 include silicon oxide, silicon nitride, and the like.

Referring to FIG. 6B, after the insulating layer 140 is formed, a channel pattern 150 is formed on the insulating layer 140.

In order to form the channel pattern 150, an amorphous silicon thin film made of amorphous silicon and an n + amorphous silicon thin film made of amorphous silicon implanted with a high concentration of impurities are sequentially formed on the insulating layer 140. A photoresist film is formed over the entire surface of the n + amorphous silicon thin film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern corresponding to the channel pattern 150 is formed on the n + amorphous silicon thin film. The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the photoresist pattern as an etching mask, and a channel pattern 150 is formed on the insulating layer 140.

The channel pattern 150 is formed corresponding to the gate electrode 111. The channel pattern 150 includes an amorphous silicon pattern 151 and an n + amorphous silicon pattern 152. The amorphous silicon pattern 151 is formed on the insulating layer 140, and the n + amorphous silicon pattern 152 is formed on the amorphous silicon pattern 151 by spaced apart from each other by a predetermined interval.

After the channel pattern 150 is formed, the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring ( 420 is formed.

In order to form the data wire 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420, the insulating film 140 and the channel pattern ( On the source 150, a source / drain metal film is formed over the entire area. The source / drain metal film may be formed by, for example, a chemical vapor deposition process or a sputtering process. Examples of the material that can be used as the source / drain metal film include aluminum, aluminum alloy, copper, molybdenum and titanium.

On the source / drain metal film, a photoresist film is formed over the entire area. The photoresist film is patterned through a photo process including an exposure process and a developing process, so that the data wire 160, the source electrode 161, the drain electrode 162, and the first data signal are formed on the source / drain metal film. A photoresist pattern corresponding to the relay wiring 320 and the second data signal relay wiring 420 is formed.

The source / drain metal layer is patterned by using the photoresist pattern as an etch mask, and the data line 160, the source electrode 161, the drain electrode 162, and the second layer are formed on the insulating layer 140 and the channel pattern 150. The first data signal relay wiring 320 and the second data signal relay wiring 420 are formed.

The data line 160 is formed to cross the gate line 110 and the common line 120 in the second direction. The source electrode 161 branches in the first direction in the data line 160 and contacts one of the pair of n + amorphous silicon patterns 152. The drain electrode 162 is spaced apart from the source electrode 161 at predetermined intervals, and contacts the other one of the pair of n + amorphous silicon patterns 152.

The first data signal relay wiring 320 is integrally formed with the data wiring 160. The first data signal relay wiring 320 is spaced apart from the second data signal relay wiring 420 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm.

Referring to FIG. 6C, the substrate 100 may be formed after the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420 are formed. The passivation layer 170 is formed on the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data signal relay wiring 420.

In order to form the passivation layer 170, the data line 160, the source electrode 161, the drain electrode 162, the first data signal relay wiring 320 and the second data are disposed on the substrate 100 over the entire area. An inorganic film covering the signal relay wiring 420 is formed. Examples of the material that can be used as the inorganic film include silicon oxide and silicon nitride.

After the inorganic film is formed, a photoresist film is formed on the inorganic film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern is formed on the inorganic film. The photoresist pattern may include a portion of the drain electrode 162, a portion of the first gate signal relay wiring 310, a portion of the second gate signal relay wiring 410, a portion 320 of the first data signal relay wiring, 2 The inorganic film corresponding to a part of the data signal relay wiring 420 and a part of the common wiring 120 is exposed.

The inorganic layer is patterned by using the photoresist pattern as an etching mask. In this case, an insulating layer 140 corresponding to a part of the first gate signal relay wiring 310, a part of the second gate signal relay wiring 410, and a part of the common wiring 120 is etched and patterned. The passivation layer 170 is formed on the substrate 100.

The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176). The first contact hole 171 exposes a portion of the drain electrode 162, and the second contact hole 172 exposes a portion of the first gate signal relay wiring 310. The third contact hole 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a part of the common wiring 120.

After the passivation layer 170 is formed, the pixel electrode 180, the transparent contact unit 500, and the common signal relay wiring 330 are formed on the passivation layer 170.

In order to form the pixel electrode 180, the transparent contact portion 500, and the common signal relay wiring 330, a transparent conductive metal film is formed on the protective film 170 over the entire area. The transparent conductive metal film may be formed by, for example, a chemical vapor deposition process or a sputtering process. Examples of the material that can be used as the transparent conductive metal film include indium tin oxide, indium zinc oxide, and the like.

After the transparent conductive metal film is formed, a photoresist film is formed on the transparent conductive metal film over the entire area. The photoresist film is patterned through a photo process including an exposure process and a developing process, and corresponds to the pixel electrode 180, the transparent contact part 500, and the common signal relay wiring 330 on the transparent conductive metal film. A photoresist pattern is formed. The transparent conductive metal layer is patterned using the photoresist pattern as an etching mask, and the pixel electrode 180, the transparent contact unit 500, and the common signal relay wiring 330 are formed on the passivation layer 170.

The pixel electrode 180 is electrically connected to the drain electrode 162 partially exposed by the first contact hole 171. The pixel electrode 180 is alternately formed with the common electrode 121 when viewed in plan view, and the pixel electrode 180 is formed in a comb shape when viewed in plan view. Alternatively, the pixel electrode 180 may be formed in a zigzag shape when viewed in a plan view.

The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520. The first transparent contact portion 510 is electrically connected to the first gate signal relay wiring 310 partially exposed by the second contact hole 172. The first transparent contact portion 510 is electrically connected to the second gate signal relay wiring 410 partially exposed by the third contact hole 173. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410. The second transparent contact portion 520 is electrically connected to the first data signal relay wiring 320 partially exposed by the fourth contact hole 174. The second transparent contact portion 520 is electrically connected to the second data signal relay wiring 420 partially exposed by the fifth contact hole 175. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

The common signal relay wiring 330 is electrically connected to the common wiring 120 partially exposed by the sixth contact hole 176. The common voltage is applied to the common electrode 130 through the common signal relay wiring 330 and the common wiring 120.

Referring to FIG. 6D, after the pixel electrode 180 and the transparent contact portion 500 are formed, the sealing member 600 is disposed on the substrate 100. The sealing member 600 has a closed loop shape and is disposed on the substrate 100. The sealing member 600 is disposed to intersect the transparent contact portion 500, and an end of the first signal relay wiring 300 and an end of the second signal relay wiring 400 corresponding to the first signal relay wiring 300. Is placed in between.

After the sealing member 600 is disposed, the alignment layer is formed on the substrate 100, and the liquid crystal layer 700 is formed.

After the liquid crystal layer 700 is formed, an opposite substrate 200 facing the substrate 100 is disposed on the sealing member. After the opposing substrate 200 is disposed, the light passing through the substrate 100 is irradiated to the sealing member 600, and the light passing through the opposing substrate 200 is irradiated to the sealing member 600. The sealing member 600 is cured by the light, and the substrate 100 and the counter substrate 200 are bonded by the sealing member 600. The sealing region is formed by the substrate 100, the counter substrate 200, and the sealing member 600.

At this time, the sealing member 600 is cured by the light passing through the substrate 100, and at the same time, the sealing member 600 is cured by the light passing through the counter substrate 200. The sealing member 600 intersects with the transparent contact portion 500. Since the transparent contact portion 500 is transparent, the light passes through the transparent contact portion 500 when light is irradiated onto the sealing member 600. Therefore, the transparent contact portion 500 is not disconnected or shorted by light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the bonding force between the sealing member 600 and the substrate 100 is increased. The light can be, for example, ultraviolet or laser.

Example 5

7 is a plan view of an organic light emitting display device according to a fifth embodiment of the present invention. FIG. 8 is a cross-sectional view taken along lines III-III ′ and IV-IV ′ of FIG. 7. In FIG. 7, the counter substrate is not displayed, but in FIG. 8, the counter substrate corresponding to the substrate is shown.

7 and 8, the organic light emitting display device according to the fifth embodiment includes a substrate 100, a gate wiring 110, an insulating film 140, a data wiring 160, a power wiring 130, and a thin film. Transistor TR, capacitor CST, passivation layer 170, organic light emitting diode E, opposing substrate 200, first signal relay 300, second signal relay 400, transparent contact portion ( 500, a sealing member 600, a gate pad part 700, a data pad part 800, and a power pad part 900.

The substrate 100 is divided into a sealing area and a non-display area by the sealing member 600 which will be described later. The sealing region is sealed by the substrate 100, the sealing member 600, and the counter substrate 200, which will be described later, and the non-display region is formed surrounding the sealing region. The substrate 100 is transparent and is an insulator. The substrate 100 may be, for example, a glass substrate, a quartz substrate or a film.

The gate wiring 110 is disposed on the substrate 100 in the first direction. The gate line 110 is disposed in the sealing area. Examples of materials that can be used as the gate wiring 110 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The insulating layer 140 includes a gate wiring 110, a first gate electrode 111 to be described later, a second gate electrode 112 to be described later, a first gate signal relay wiring 310 to be described later, and a second gate signal relay to be described later. The wiring 410, the gate pad electrode 710 to be described later, and the first capacitor electrode 113 to be described below are covered. The insulating layer 140 includes a contact hole 141 exposing a portion of the second gate electrode 112. Examples of the material that can be used as the insulating film 140 include silicon nitride, silicon oxide, and the like.

The data line 160 is disposed in the second direction on the insulating layer 140 to cross the gate line 110. The data line 160 is disposed in the sealing area. Examples of materials that can be used as the data wiring 160 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The power line 130 is disposed parallel to the data line 160. The power line 130 is disposed in the sealing area. Examples of materials that can be used as the power supply wiring 130 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The thin film transistor TR includes a switching thin film transistor tr1 and a driving thin film transistor tr2. The thin film transistor TR is disposed on the substrate 100.

The switching thin film transistor tr2 includes a first gate electrode 111, a first channel pattern 150a, a first source electrode 161, and a first drain electrode 162.

The first gate electrode 111 is branched from the gate wiring 110 and disposed on the substrate 100.

The first channel pattern 150a corresponds to the first gate electrode 111 and is disposed on the insulating layer 140. The first channel pattern 150a includes a first amorphous silicon pattern 151a and a first n + amorphous silicon pattern 152a. The material used as the first amorphous silicon pattern 151a is amorphous silicon, and the material used as the first n + amorphous silicon pattern 152a is amorphous silicon implanted with a high concentration of impurities. The first amorphous silicon pattern 151a is disposed on the insulating layer 140, and a pair of first n + amorphous silicon patterns 152a are disposed on the first amorphous silicon pattern 151a and spaced apart from each other at predetermined intervals.

The first source electrode 161 is branched from the data line 160 and is in contact with one of the pair of first n + amorphous silicon patterns 152a. The material used as the first source electrode 161 is the same as the material used as the data line 160.

The first drain electrode 162 is spaced apart from the first source electrode 161 at predetermined intervals. The first drain electrode 162 is in contact with the other one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is electrically connected to the second gate electrode 112, which will be described later.

The driving thin film transistor tr2 includes a second gate electrode 112, a second channel pattern 150b, a second source electrode 131, and a second drain electrode 132.

The second gate electrode 112 is electrically connected to the first drain electrode 162. The second gate electrode 112 is disposed on the substrate 100.

The second channel pattern 150b is disposed on the insulating layer 140, and the second channel pattern 150b is disposed corresponding to the second gate electrode 112. The second channel pattern 150b includes a second amorphous silicon pattern 151b and a second n + amorphous silicon pattern 152b. The material used as the second amorphous silicon pattern 151b is amorphous silicon, and the material used as the second n + amorphous silicon pattern 152b is amorphous silicon implanted with a high concentration of impurities. The second amorphous silicon pattern 151b is disposed on the insulating layer 140, and the second n + amorphous silicon pattern 152b is disposed on the second amorphous silicon pattern 151b so as to be spaced apart from each other at predetermined intervals.

The second source electrode 131 is branched from the power supply line 130 and contacts one of the pair of second n + amorphous silicon patterns 152b. The material used as the second source electrode 131 is the same as the material used as the power source wiring 130.

The second drain electrode 132 is spaced apart from the second source electrode 131 at predetermined intervals. The second drain electrode 132 is in contact with the other one of the pair of second n + amorphous silicon patterns 152b. Examples of materials that can be used as the second drain electrode 132 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The capacitor CST includes a first capacitor electrode 113, a second capacitor electrode 133, and an insulating layer 140 interposed between the first capacitor electrode 113 and the second capacitor electrode 133. The first capacitor electrode 113 is disposed on the substrate 100 and is electrically connected to the second gate electrode 112. The first capacitor electrode 113 has a shape corresponding to the second capacitor electrode 133. The second capacitor electrode 133 is formed to branch from the power line 130. Accordingly, the second capacitor electrode 133 is electrically connected to the power supply wiring 130.

The passivation layer 140 may include a data line 160, a power line 130, a thin film transistor TR, a capacitor CST, a first data signal relay 320, which will be described later, and a second data signal relay 420, which will be described later. ), The first power signal relay wiring 330 to be described later, the second power signal relay wiring 430 to be described later, the data pad electrode 810 to be described later, and the power pad electrode 910 to be described below are covered. Examples of the material that can be used as the protective film 170 include silicon oxide and silicon nitride.

The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176, a seventh contact hole 177, an eighth contact hole 720, a ninth contact hole 820, and a tenth contact hole 920. The first contact hole 171 exposes a part of the second drain electrode 162, the second contact hole 172 exposes a part of the first gate signal relay wiring 310, which will be described later, and the third contact hole. Reference numeral 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a portion of the first power signal relay wiring 330, and the seventh contact hole 177 exposes a portion of the second power signal relay wiring 430. The eighth contact hole 720 exposes a portion of the gate pad electrode 710, the ninth contact hole 820 exposes a portion of the data pad electrode 810, and the tenth contact hole 920 represents a power pad. Expose a portion of the electrode 910.

The organic light emitting diode E is disposed on the passivation layer 170. The organic light emitting diode E includes a first electrode 181, a second electrode 182, and an organic light emitting layer 190. The first electrode 181 is electrically connected to the second drain electrode 132 partially exposed by the first contact hole 171. Examples of materials that can be used as the first electrode 181 include indium tin oxide, indium zinc oxide, and the like. The second electrode 182 is disposed to face the first electrode 181. The second electrodes 182 are spaced apart from each other at predetermined intervals on the first electrode 181. Examples of materials that can be used as the second electrode 182 include molybdenum, molybdenum alloys, titanium and titanium alloys, and the like. The organic emission layer 190 is interposed between the first electrode 181 and the second electrode 182. The organic emission layer 190 generates light by a current flowing between the first electrode 181 and the second electrode 182.

The first signal relay line 300 is disposed in the sealing area. Examples of materials that may be used as the first signal relay 300 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like. The first signal relay wiring 300 includes a first gate signal relay wiring 310, a first data signal relay wiring 320, and a first power signal relay wiring 330.

The first gate signal relay wiring 310 is electrically connected to the gate wiring 110. The first gate signal relay wiring 310 may be disposed on the same layer as the gate wiring 110. The first gate signal relay wiring 310 may be integrally formed with the gate wiring 110.

The first data signal relay wiring 320 is electrically connected to the data wiring 160. The first data signal relay wiring 320 may be formed on the same layer as the data wiring 160. The first data signal relay wiring 320 may be integrally formed with the data wiring 160.

The first power signal relay wiring 330 is electrically connected to the power wiring 130. The first power signal relay wiring 330 may be formed on the same layer as the power wiring 130. The first power signal relay wiring 330 may be integrally formed with the power wiring 130.

The second signal relay wiring 400 is disposed in the non-display area. The second signal relay wiring 400 is spaced apart from the first signal relay wiring 300 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm. The second signal relay 400 includes a second gate signal relay 410, a second data signal relay 420, and a second power signal relay 430. Examples of materials that may be used as the second signal relay 400 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The second gate signal relay wiring 410 is spaced apart from the first gate signal relay wiring 310 at predetermined intervals. The second gate signal relay wiring 410 may be formed on the same layer as the first gate signal relay wiring 310. The second gate signal relay wiring 410 is electrically connected to the gate pad part 700.

The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 410 at predetermined intervals from each other. The second data signal relay wiring 420 may be formed on the same layer as the first data signal relay wiring 320. The second data signal relay wiring 420 is electrically connected to the data pad unit 800.

The second power signal relay wiring 430 is spaced apart from the first power signal relay wiring 330 at predetermined intervals. The second power signal relay wiring 430 may be formed on the same layer as the first power signal relay wiring 330. The second power signal relay wiring 430 is electrically connected to the power pad unit 900.

The transparent contact unit 500 is electrically connected to the first signal relay line 300 and the second signal relay line 400. That is, the transparent contact unit 500 electrically connects the first signal relay wiring 300 and the second signal relay wiring 400. The transparent contact portion 500 is disposed on the passivation layer 170. Examples of the material that can be used as the transparent contact portion 500 include indium tin oxide, indium zinc oxide, and the like. The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520. The transparent contact portion 500 may be formed on the same layer as the first electrode 181.

The first transparent contact portion 510 is electrically connected to the first gate signal relay wiring 310 partially exposed by the second contact hole 172, and the first transparent contact portion 510 is connected to the third contact hole. An electrical connection is made to the second gate signal relay wiring 410 partially exposed by the reference numeral 173. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410.

The second transparent contact portion 520 is electrically connected to the first data signal relay wiring 320 partially exposed by the fourth contact hole 174, and the second transparent contact portion 520 is connected to the fifth contact hole. A portion 175 is electrically connected to the second data signal relay wiring 420 partially exposed. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

The third transparent contact portion 530 is electrically connected to the first power signal relay wiring 330 partially exposed by the sixth contact hole 176, and the third transparent contact portion 530 is connected to the seventh contact hole. It is electrically connected to the second power signal relay wiring 430 exposed through 177. That is, the third transparent contact unit 530 electrically connects the first power signal relay wiring 330 and the second power signal relay wiring 430.

The gate pad part 700 is disposed on the exposed area. The gate pad part 700 is electrically connected to the second gate signal relay wiring 410. The gate pad part 700 includes a gate pad electrode 710 and a first anti-corrosion conductive layer 730. The gate pad electrode 710 is integrally formed with the second gate signal relay wiring 410, and a part of the gate pad electrode 710 is exposed by the eighth contact hole 720. The first anti-corrosion conductive film 730 covers the eighth contact hole 720, and the first anti-corrosion conductive film 730 is electrically connected to the gate pad electrode 710. Examples of the material that can be used as the first anti-corrosion conductive film 730 include indium tin oxide, indium zinc oxide, and the like. The first anti-corrosion conductive film 730 may be formed on the same layer as the transparent contact portion 500. The gate pad part 700 is connected to a driving circuit that generates a gate signal.

The data pad part 800 is disposed on the exposed area. The data pad unit 800 is electrically connected to the second data signal relay wiring 420. The data pad part 800 includes a data pad electrode 810 and a second corrosion preventing conductive layer 830. The data pad electrode 810 is integrally formed with the second data signal relay wiring 420, and a part of the data pad electrode 810 is exposed through the ninth contact hole 820. The second corrosion resistant conductive film 830 covers the ninth contact hole 820, and the second corrosion resistant conductive film 830 is electrically connected to the data pad electrode 810. Examples of the material that can be used as the second anti-corrosion conductive film 830 include indium tin oxide, indium zinc oxide, and the like. The second anti-corrosion conductive film 830 may be formed on the same layer as the transparent contact portion 500. The data pad unit 800 is connected to a driving circuit that generates a data signal.

The power pad unit 900 is disposed on the exposed area. The power pad unit 900 is electrically connected to the second power signal relay wiring 430. The power pad unit 900 includes a power pad electrode 910 and a third corrosion resistant conductive film 930. The power pad electrode 900 is integrally formed with the second power signal relay wiring 430, and a part of the power pad electrode 910 is exposed by the tenth contact hole 920. The third anti-corrosion conductive film 930 covers the tenth contact hole 920, and the third anti-corrosion conductive film 930 is electrically connected to the power pad electrode 910. Examples of the material that can be used as the third anti-corrosion conductive film 930 include indium tin oxide, indium zinc oxide, and the like. The third anti-corrosion conductive film 930 may be formed on the same layer as the transparent contact portion 500. The power pad unit 900 is connected to a driving circuit that generates a power signal.

The sealing member 600 has a closed loop shape and is disposed on the passivation layer 170. By the sealing member 600, the substrate 100, and the counter substrate 200 to be described later, a sealing region sealed to the outside is formed. A non-display area is formed around the sealing area. The seal member 600 is formed to intersect the transparent contact portion 500. Examples of the material that can be used as the sealing member 600 include a photocurable resin and a thermosetting resin.

The sealing member 600 and the transparent contact portion 500 are arranged to cross. Since the transparent contact portion 500 is transparent, the light passes through the transparent contact portion 500 when light is irradiated to the sealing member 600. Therefore, the transparent contact portion 500 is not disconnected or shorted in the process of irradiating the sealing member 600 with light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the adhesion between the sealing member 600 and the substrate 100 may be enhanced. The light can be, for example, ultraviolet or laser.

The opposite substrate 200 is disposed to face the substrate 100. The opposite substrate 200 is coupled to the substrate 100 by the sealing member 600. The counter substrate 200 may include a moisture absorbent for protecting the organic light emitting diode (E).

Example 6

9A to 9D are cross-sectional views illustrating a process of a method of manufacturing a display device according to a sixth embodiment of the present invention.

Referring to FIG. 9A, the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, and the first gate signal relay wiring 310 are disposed on the substrate 100. ), A second gate signal relay wiring 410 and a gate pad electrode 710 are formed.

The substrate 100 is transparent and is an insulator. The substrate 100 may be, for example, a glass substrate, a quartz substrate, or a film.

The gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, and the second gate signal relay wiring 410. And a metal film is formed over the entire surface of the substrate 100 to form the gate pad electrode 710. Examples of the material that can be used as the metal film include aluminum, aluminum alloy, copper, molybdenum and titanium. After the metal film is formed, a photoresist film including a photosensitive material is formed on the metal film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern is formed on the metal film. The metal layer is patterned by using the photoresist pattern as an etching mask, and the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, and the first substrate are formed on the substrate. The first gate signal relay wiring 310, the second gate signal relay wiring 410, and the gate pad electrode 710 are formed.

The gate wiring 110 is formed in the first direction, and the first gate electrode 111 is branched from the gate wiring 110. The gate wiring 110 and the first gate signal relay wiring 310 are integrally formed. The second gate electrode 112 is electrically connected to the first capacitor electrode 113. The second gate signal relay wiring 410 is formed spaced apart from each other at a predetermined interval on the first gate signal relay wiring 310, and the second gate signal relay wiring 410 and the gate pad electrode 710 are integrally formed. do.

The gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, the second gate signal relay wiring 410, and After the gate pad electrode 710 is formed, the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, An insulating layer 140 is formed to cover the second gate signal relay wiring 410 and the gate pad electrode 710. The insulating layer 140 includes a contact hole exposing a part of the second gate electrode 112. Examples of materials that may be used as the insulating layer 140 include silicon oxide, silicon nitride, and the like.

Referring to FIG. 9B, after the insulating layer 140 is formed, a channel pattern 150 is formed on the insulating layer 140.

In order to form the channel pattern 150, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially formed on the insulating film 140 over the entire area. The material used as the amorphous silicon thin film is amorphous silicon, and the material used as the n + amorphous silicon thin film is amorphous silicon implanted with a high concentration of impurities. Thereafter, a photoresist film is formed on the n + amorphous silicon thin film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the n + amorphous silicon thin film. The photoresist pattern has a shape corresponding to the channel pattern 150. The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the photoresist pattern as an etching mask, and a channel pattern 150 is formed on the insulating layer 140.

The channel pattern 150 includes a first channel pattern 150a and a second channel pattern 150b. The first channel pattern 150a is formed corresponding to the first gate electrode 111, and the first channel pattern 150a includes a first amorphous silicon pattern 151a and a first n + amorphous silicon pattern 152a. do. The first amorphous silicon pattern 151a is formed on the insulating layer 140, and a pair of first n + amorphous silicon patterns 152a are formed on the first amorphous silicon pattern 151a so as to be spaced apart from each other at predetermined intervals. The second channel pattern 150b is formed corresponding to the second gate electrode 112, and the second channel pattern 150b includes a second amorphous silicon pattern 151b and a second n + amorphous silicon pattern 152b. . The second amorphous silicon pattern 151b is formed on the insulating layer 140, and the pair of second n + amorphous silicon patterns 152b are formed on the second amorphous silicon pattern 151b so as to be spaced apart from each other by a predetermined interval.

After the channel pattern 150 is formed, the data wiring 160, the first source electrode 161, the first drain electrode 162, the power supply wiring 130, the second source electrode 131, and the second drain electrode ( 132, the second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, and the second power signal relay wiring 430. The data pad electrode 810 and the power pad electrode 910 are formed.

Data wiring 160, first source electrode 161, first drain electrode 162, power supply wiring 130, second source electrode 131, second drain electrode 132, second capacitor electrode 133 ), The first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, the second power signal relay wiring 430, the data pad electrode 810, and the power supply. In order to form the pad electrode 910, a source / drain metal film is formed on the insulating layer 140. Examples of the material that can be used as the source / drain metal film include aluminum, aluminum alloy, copper, molybdenum and titanium. A photoresist film is then formed over the entire area on the source / drain metal film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the source / drain metal film. The source / drain metal layer is patterned by using the photoresist pattern as an etch mask, and the data line 160, the first source electrode 161, the first drain electrode 162, and the power source line are formed on the insulating layer 140. 130, the second source electrode 131, the second drain electrode 132, the second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, and the first power source. The signal relay wiring 330, the second power signal relay wiring 430, the data pad electrode 710, and the power pad electrode 810 are formed.

The data line 160 crosses the gate line 110 and is formed in a second direction. The first source electrode 161 branches from the data line 160 and contacts one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is spaced apart from the first source electrode 161 at a predetermined interval and contacts the other one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is electrically connected to the second gate electrode 112. The power line 130 is formed in parallel with the data line 160. The second source electrode 131 is branched from the power supply line 130 and contacts one of the pair of second n + amorphous silicon patterns 152b. The second drain electrode 132 is spaced apart from the second source electrode 131 by a predetermined interval and contacts the other one of the pair of second n + amorphous silicon patterns 152b. The second capacitor electrode 133 is branched from the power line 130 and formed to correspond to the first capacitor electrode 113.

The first data signal relay wiring 320 is integrally formed with the data wiring 160. The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 320 at a predetermined interval, and the interval may be about 1 mm to about 2 mm. The data pad electrode 810 is integrally formed with the second data signal relay wiring 420.

The first power signal relay wiring 330 is integrally formed with the power wiring 130. The second power signal relay wiring 430 is spaced apart from the first power signal relay wiring 330 at predetermined intervals, and the interval may be about 1 mm to about 2 mm. The power pad electrode 910 is integrally formed with the second power signal relay wiring 430.

Referring to FIG. 9C, the data wire 160, the first source electrode 161, the first drain electrode 162, the power source wire 130, the second source electrode 131, and the second drain electrode 132, The second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, the second power signal relay wiring 430, the data pad A passivation layer 170 is formed to cover the electrode 810 and the power pad electrode 910.

In order to form the protective film 170, an inorganic film is formed on the substrate 100. Examples of the material that can be used as the inorganic film include silicon oxide and silicon nitride. After the inorganic film is formed, a photoresist film is formed over the entire surface of the inorganic film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the inorganic layer. The photoresist pattern may be formed on an inorganic layer corresponding to a portion of the second drain electrode 132, an inorganic layer corresponding to a portion of the first gate signal relay wiring 310, and a portion of the second gate signal relay wiring 410. The corresponding inorganic film, the inorganic film corresponding to a portion of the gate pad electrode 710, the inorganic film corresponding to a portion of the first data signal relay wiring 320, and a portion of the second data signal relay wiring 420. Inorganic film, inorganic film corresponding to part of data pad electrode 810, inorganic film corresponding to part of first power signal relay wiring 330, inorganic film corresponding to part of second power signal relay wiring 430 And an inorganic film corresponding to a portion of the power pad electrode 910. The inorganic layer is patterned using the photoresist pattern as an etching mask, and a protective layer 170 is formed on the substrate 100. In this case, an insulating film corresponding to a part of the first gate signal relay wiring 310, an insulating film corresponding to a part of the second gate signal relay wiring 410, and an insulating film corresponding to a part of the gate pad electrode 710 are removed.

The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176, a seventh contact hole 177, an eighth contact hole 720, a ninth contact hole 820, and a tenth contact hole 920. The first contact hole 171 exposes a part of the second drain electrode 162, the second contact hole 172 exposes a part of the first gate signal relay wiring 310, which will be described later, and the third contact hole. Reference numeral 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a portion of the first power signal relay wiring 330, and the seventh contact hole 177 exposes a portion of the second power signal relay wiring 430. The eighth contact hole 720 exposes a portion of the gate pad electrode 710, the ninth contact hole 820 exposes a portion of the data pad electrode 810, and the tenth contact hole 920 is a power source. A portion of the pad electrode 910 is exposed.

9D, after the protective film 170 is formed, the first electrode 181, the transparent contact portion 500, the first corrosion resistant conductive film 730, and the second corrosion resistant conductive film are formed on the protective film 170. 830 and a third anti-corrosion conductive film 930 are formed.

In order to form the first electrode 181, the transparent contact portion 500, the first corrosion resistant conductive film 730, the second corrosion resistant conductive film 830, and the third corrosion resistant conductive film 930, a protective film ( A transparent metal film is formed on the entire surface 170. Examples of the material that can be used as the transparent metal film include indium tin oxide, indium zinc oxide, and the like. After the transparent metal film is formed, a photoresist film is formed over the entire area on the transparent metal film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the transparent metal film. The photoresist pattern corresponds to the first electrode 181, the transparent contact portion 500, the first corrosion resistant conductive film 730, the second corrosion resistant conductive film 830, and the third corrosion resistant conductive film 930. It has a shape to The transparent metal layer is patterned by using the photoresist pattern as an etching mask, and the first electrode 181, the transparent contact portion 500, the first anti-corrosion conductive layer 730, and the second corrosion on the passivation layer 170. The anti-conductive film 830 and the third anti-corrosion conductive film 930 are formed.

The first electrode 181 is electrically connected to the second drain electrode 132 partially exposed by the first contact hole 171. The transparent contact part 500 includes a first transparent contact part 510, a second transparent contact part 520, and a third transparent contact part 530. The first transparent contact portion 510 is electrically connected to the first gate signal relay wiring 310 partially exposed by the second contact hole 172, and the second transparent contact portion 520 is connected to the third contact hole. An electrical connection is made to the second gate signal relay wiring 410 partially exposed by the reference numeral 173. The second transparent contact portion 520 is electrically connected to the first data signal relay wiring 320 partially exposed by the fourth contact hole 174, and the second transparent contact portion 520 is connected to the fifth contact hole. A portion 175 is electrically connected to the second data signal relay wiring 420 partially exposed. The third transparent contact portion 530 is electrically connected to the first power signal relay wiring 330 partially exposed by the sixth contact hole 176, and the third transparent contact portion 530 is connected to the seventh contact hole. A portion 177 is electrically connected to the second power signal relay wiring 430 partially exposed.

The first anti-corrosion conductive film 730 covers the eighth contact hole 720, and the first anti-corrosion conductive film 730 partially exposes the gate pad electrode 710 by the eighth contact hole 720. Is electrically connected to the. The second anticorrosion conductive layer 830 covers the ninth contact hole 820, and the second anticorrosion conductive layer 830 is partially exposed by the ninth contact hole 820. Is electrically connected to the. The third anti-corrosion conductive film 930 covers the tenth contact hole 920, and the third anti-corrosion conductive film 930 is partially exposed by the tenth contact hole 920. Is electrically connected to the.

After forming the first electrode 181, the transparent contact portion 500, the first corrosion resistant conductive film 730, the second corrosion resistant conductive film 830, and the third corrosion resistant conductive film 930, the first electrode The organic emission layer 190 is formed on the 181. Before the organic emission layer 190 is formed, a pixel separation pattern may be formed on the first electrode 181.

After the organic emission layer 190 is formed, the second electrode 182 is formed. The second electrode 182 covers the organic emission layer 190. The second electrode 182 is formed to face the first electrode 181, and the second electrode 182 is electrically insulated from the transparent contact portion 500. The second electrode 182 is formed in the sealing region to be described later.

After the second electrode 182 is formed, the sealing member 600 is disposed on the substrate 100.

The sealing member 600 has a closed loop shape, and the sealing member 600 intersects with the transparent contact portion 500. The sealing member 600 has a closed loop shape and is disposed on the substrate 100. The sealing member 600 is disposed to intersect the transparent contact portion 500, and an end of the first signal relay wiring 300 and an end of the second signal relay wiring 400 corresponding to the first signal relay wiring 300. Is placed in between. Examples of the material that can be used as the sealing member include photocurable resins and thermosetting resins.

After the sealing member 600 is disposed, the counter substrate 200 facing the substrate 100 is disposed on the sealing member 600. After the opposing substrate 200 is disposed, the light passing through the substrate 100 is irradiated to the sealing member 600, and the light passing through the opposing substrate 200 is irradiated to the sealing member 600. The sealing member 600 is cured by the light, and the substrate 100 and the counter substrate 200 are bonded by the sealing member 600. The sealing region is formed by the substrate 100, the counter substrate 200, and the sealing member 600.

At this time, the sealing member 600 is cured by the light passing through the substrate 100, and at the same time the sealing member 600 is cured by the light passing through the counter substrate 200. Since the sealing member 600 intersects with the transparent contact portion 500 and the transparent contact portion 500 is transparent, when the light is irradiated to the sealing member 600, the light is transmitted to the transparent contact portion 500. Pass). Therefore, the transparent contact portion 500 is not disconnected or shorted by the light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the bonding force between the sealing member 600 and the substrate 100 is increased. The light can be, for example, ultraviolet or laser.

Example 7

10 is a plan view of an organic light emitting display device according to a seventh embodiment of the present invention. FIG. 11 is a cross-sectional view taken along lines VV and VIV in FIG. 10. In FIG. 10, the counter substrate is not displayed, but in FIG. 11, the counter substrate corresponding to the substrate is displayed.

10 and 11, an organic light emitting display device according to a seventh embodiment includes a substrate 100, a gate wiring 110, an insulating film 140, a data wiring 160, a power wiring 130, and a thin film. Transistor TR, capacitor CST, passivation layer 170, connection electrode 181, opposing substrate 200, first signal relay wiring 300, second signal relay wiring 400, transparent contact portion 500 ), A sealing member 600, a gate pad part 700, a data pad part 800, and a power pad part 900.

The substrate 100 is divided into a sealing area and a non-display area by the sealing member 600 which will be described later. The sealing region is sealed by the substrate 100, the sealing member 600, and the counter substrate 200, which will be described later, and the non-display region is formed surrounding the sealing region. The substrate 100 is transparent and is an insulator. The substrate 100 may be, for example, a glass substrate, a quartz substrate, or a film.

The gate wiring 110 is disposed on the substrate 100 in the first direction. The gate line 110 is disposed in the sealing area. Examples of materials that can be used as the gate wiring 110 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The insulating layer 140 includes a gate wiring 110, a first gate electrode 111 to be described later, a second gate electrode 112 to be described later, a first gate signal relay wiring 310 to be described later, and a second gate signal relay to be described later. The wiring 410, the gate pad electrode 710 to be described later, and the first capacitor electrode 113 to be described below are covered. The insulating layer 140 includes a contact hole 141 exposing a portion of the second gate electrode 112. Examples of the material that can be used as the insulating film 140 include silicon nitride, silicon oxide, and the like.

The data line 160 is disposed in the second direction on the insulating layer 140 to cross the gate line 110. The data line 160 is disposed in the sealing area. Examples of materials that can be used as the data wiring 160 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The power line 130 is disposed parallel to the data line 160. The power line 130 is disposed in the sealing area. Examples of materials that can be used as the power supply wiring 130 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The thin film transistor TR includes a switching thin film transistor tr1 and a driving thin film transistor tr2. The thin film transistor TR is disposed on the substrate 100.

The switching thin film transistor tr2 includes a first gate electrode 111, a first channel pattern 150a, a first source electrode 161, and a first drain electrode 162.

The first gate electrode 111 is branched from the gate wiring 110 and disposed on the substrate 100.

The first channel pattern 150a corresponds to the first gate electrode 111 and is disposed on the insulating layer 140. The first channel pattern 150a includes a first amorphous silicon pattern 151a and a first n + amorphous silicon pattern 152a. The material used as the first amorphous silicon pattern 151a is amorphous silicon, and the material used as the first n + amorphous silicon pattern 152a is amorphous silicon implanted with a high concentration of impurities. The first amorphous silicon pattern 151a is disposed on the insulating layer 140, and a pair of first n + amorphous silicon patterns 152a are disposed on the first amorphous silicon pattern 151a and spaced apart from each other at predetermined intervals.

The first source electrode 161 is branched from the data line 160 and is in contact with one of the pair of first n + amorphous silicon patterns 152a. The material used as the first source electrode 161 is the same as the material used as the data line 160.

The first drain electrode 162 is spaced apart from the first source electrode 161 at predetermined intervals. The first drain electrode 162 is in contact with the other one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is electrically connected to the second gate electrode 112, which will be described later.

The driving thin film transistor tr2 includes a second gate electrode 112, a second channel pattern 150b, a second source electrode 131, and a second drain electrode 132.

The second gate electrode 112 is electrically connected to the first drain electrode 162. The second gate electrode 112 is disposed on the substrate 100.

The second channel pattern 150b is disposed on the insulating layer 140, and the second channel pattern 150b is disposed corresponding to the second gate electrode 112. The second channel pattern 150b includes a second amorphous silicon pattern 151b and a second n + amorphous silicon pattern 152b. The material used as the second amorphous silicon pattern 151b is amorphous silicon, and the material used as the second n + amorphous silicon pattern 152b is amorphous silicon implanted with a high concentration of impurities. The second amorphous silicon pattern 151b is disposed on the insulating layer 140, and the second n + amorphous silicon pattern 152b is disposed on the second amorphous silicon pattern 151b so as to be spaced apart from each other at predetermined intervals.

The second source electrode 131 is branched from the power supply line 130 and contacts one of the pair of second n + amorphous silicon patterns 152b. The material used as the second source electrode 131 is the same as the material used as the power source wiring 130. The second source electrode 131 is formed to surround the second drain electrode 132, which will be described later, in order to improve performance of the driving thin film transistor tr2.

The second drain electrode 132 is spaced apart from the second source electrode 131 at predetermined intervals. The second drain electrode 132 is in contact with the other one of the pair of second n + amorphous silicon patterns 152b. Examples of materials that can be used as the second drain electrode 132 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The capacitor CST includes a first capacitor electrode 113, a second capacitor electrode 133, and an insulating layer 140 interposed between the first capacitor electrode 113 and the second capacitor electrode 133. The first capacitor electrode 113 is disposed on the substrate 100 and is electrically connected to the second gate electrode 112. The first capacitor electrode 113 has a shape corresponding to the second capacitor electrode 133. The second capacitor electrode 133 is formed to branch from the power line 130. Accordingly, the second capacitor electrode 133 is electrically connected to the power supply wiring 130.

The passivation layer 140 may include a data line 160, a power line 130, a thin film transistor TR, a capacitor CST, a first data signal relay 320, which will be described later, and a second data signal relay 420, which will be described later. ), The first power signal relay wiring 330 to be described later, the second power signal relay wiring 430 to be described later, the data pad electrode 810 to be described later, and the power pad electrode 910 to be described below are covered. Examples of the material that can be used as the protective film 170 include silicon oxide and silicon nitride.

The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176, a seventh contact hole 177, an eighth contact hole 720, a ninth contact hole 820, and a tenth contact hole 920. The first contact hole 171 exposes a part of the second drain electrode 132, the second contact hole 172 exposes a part of the first gate signal relay wiring 310 to be described later, and the third contact hole. Reference numeral 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a portion of the first power signal relay wiring 330, and the seventh contact hole 177 exposes a portion of the second power signal relay wiring 430. The eighth contact hole 720 exposes a portion of the gate pad electrode 710, the ninth contact hole 820 exposes a portion of the data pad electrode 810, and the tenth contact hole 920 represents a power pad. A portion of the electrode 910 is exposed.

The connection electrode 183 is electrically connected to the second drain electrode 132 partially exposed by the first contact hole 171. The connection electrode 183 is electrically connected to the organic light emitting diode disposed on the opposing substrate. Examples of materials that can be used as the connection electrode 183 include indium tin oxide, indium zinc oxide, and the like.

The first signal relay line 300 is disposed in the sealing area. Examples of materials that may be used as the first signal relay 300 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like. The first signal relay line 300 includes a first gate signal relay line 310, a first data signal relay line 320, and a first power signal relay line 330.

The first gate signal relay wiring 310 is electrically connected to the gate wiring 110. The first gate signal relay wiring 310 may be disposed on the same layer as the gate wiring 110. The first gate signal relay wiring 310 may be integrally formed with the gate wiring 110.

The first data signal relay wiring 320 is electrically connected to the data wiring 160. The first data signal relay wiring 320 may be formed on the same layer as the data wiring 160. The first data signal relay wiring 320 may be integrally formed with the data wiring 160.

The first power signal relay wiring 330 is electrically connected to the power wiring 130. The first power signal relay wiring 330 may be formed on the same layer as the power wiring 130. The first power signal relay wiring 330 may be integrally formed with the power wiring 130.

The second signal relay wiring 400 is disposed in the non-display area. The second signal relay wiring 400 is spaced apart from the first signal relay wiring 300 at predetermined intervals from each other. The spacing may be about 1 mm to about 2 mm. The second signal relay 400 includes a second gate signal relay 410, a second data signal relay 420, and a second power signal relay 430. Examples of materials that may be used as the second signal relay 400 include aluminum, aluminum alloys, copper, molybdenum, titanium, and the like.

The second gate signal relay wiring 410 is spaced apart from the first gate signal relay wiring 310 at predetermined intervals. The second gate signal relay wiring 410 may be formed on the same layer as the first gate signal relay wiring 310. The second gate signal relay wiring 410 is electrically connected to the gate pad part 700.

The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 410 at predetermined intervals from each other. The second data signal relay wiring 420 may be formed on the same layer as the first data signal relay wiring 320. The second data signal relay wiring 420 is electrically connected to the data pad unit 800.

The second power signal relay wiring 430 is spaced apart from the first power signal relay wiring 330 at predetermined intervals. The second power signal relay wiring 430 may be formed on the same layer as the first power signal relay wiring 330. The second power signal relay wiring 430 is electrically connected to the power pad unit 900.

The transparent contact unit 500 is electrically connected to the first signal relay line 300 and the second signal relay line 400. That is, the transparent contact unit 500 electrically connects the first signal relay wiring 300 and the second signal relay wiring 400. The transparent contact portion 500 is disposed on the passivation layer 170. Examples of the material that can be used as the transparent contact portion 500 include indium tin oxide, indium zinc oxide, and the like. The transparent contact part 500 includes a first transparent contact part 510 and a second transparent contact part 520. The transparent contact portion 500 may be formed on the same layer as the connection electrode 183.

The first transparent contact portion 510 is a second gate signal relay partially exposed by the first gate signal relay wiring 310 and the third contact hole 173 exposed by the second contact hole 172. It is electrically connected to the wiring 410. That is, the first transparent contact unit 510 electrically connects the first gate signal relay wiring 310 and the second gate signal relay wiring 410.

The second transparent contact unit 520 relays the second data signal relay partially exposed by the first data signal relay wiring 320 and the fifth contact hole 175 partially exposed by the fourth contact hole 174. It is electrically connected to the wiring 420. That is, the second transparent contact unit 520 electrically connects the first data signal relay wiring 320 and the second data signal relay wiring 420.

The third transparent contact unit 530 is the second power signal relay wiring exposed through the first power signal relay wiring 330 and the seventh contact hole 177 partially exposed by the sixth contact hole 176. And electrically connected to 430. That is, the third transparent contact unit 530 electrically connects the first power signal relay wiring 330 and the second power signal relay wiring 430.

The gate pad part 700 is disposed on the exposed area. The gate pad part 700 is electrically connected to the second gate signal relay wiring 410. The gate pad part 700 includes a gate pad electrode 710 and a first anti-corrosion conductive layer 730. The gate pad electrode 710 is integrally formed with the second gate signal relay wiring 410, and a part of the gate pad electrode 710 is exposed by the eighth contact hole 720. The first anti-corrosion conductive film 730 covers the eighth contact hole 720, and the first anti-corrosion conductive film 730 is electrically connected to the gate pad electrode 710. Examples of the material that can be used as the first anti-corrosion conductive film 730 include indium tin oxide, indium zinc oxide, and the like. The first anti-corrosion conductive film 730 may be formed on the same layer as the transparent contact portion 500. The gate pad part 700 is connected to a driving circuit that generates a gate signal.

The data pad part 800 is disposed on the exposed area. The data pad unit 800 is electrically connected to the second data signal relay wiring 420. The data pad part 800 includes a data pad electrode 810 and a second corrosion preventing conductive layer 830. The data pad electrode 810 is integrally formed with the second data signal relay wiring 420, and a part of the data pad electrode 810 is exposed through the ninth contact hole 820. The second corrosion resistant conductive film 830 covers the ninth contact hole 820, and the second corrosion resistant conductive film 830 is electrically connected to the data pad electrode 810. Examples of the material that can be used as the second anti-corrosion conductive film 830 include indium tin oxide, indium zinc oxide, and the like. The second anti-corrosion conductive film 830 may be formed on the same layer as the transparent contact portion 500. The data pad unit 800 is connected to a driving circuit that generates a data signal.

The power pad unit 900 is disposed on the exposed area. The power pad unit 900 is electrically connected to the second power signal relay wiring 430. The power pad unit 900 includes a power pad electrode 910 and a third corrosion resistant conductive film 930. The power pad electrode 900 is integrally formed with the second power signal relay wiring 430, and a part of the power pad electrode 910 is exposed by the tenth contact hole 920. The third anti-corrosion conductive film 930 covers the tenth contact hole 920, and the third anti-corrosion conductive film 930 is electrically connected to the power pad electrode 910. Examples of the material that can be used as the third anti-corrosion conductive film 930 include indium tin oxide, indium zinc oxide, and the like. The third anti-corrosion conductive film 930 may be formed on the same layer as the transparent contact portion 500. The power pad unit 900 is connected to a driving circuit that generates a power signal.

The sealing member 600 has a closed loop shape and is disposed on the passivation layer 170. By the sealing member 600, the substrate 100, and the counter substrate 200 to be described later, a sealing region sealed to the outside is formed. A non-display area is formed around the sealing area. The sealing member 600 is formed to cross the transparent contact portion 500. Examples of the material that can be used as the sealing member 600 include a photocurable resin and a thermosetting resin.

The sealing member 600 and the transparent contact portion 500 are arranged to cross. Since the transparent contact portion 500 is transparent, the light passes through the transparent contact portion 500 when light is irradiated to the sealing member 600. Therefore, the transparent contact portion 500 is not disconnected or shorted in the process of irradiating the sealing member 600 with light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the adhesion between the sealing member 600 and the substrate 100 may be enhanced.

The opposite substrate 200 is disposed to face the substrate 100. The opposite substrate 200 is coupled to the substrate 100 by the sealing member 600. The counter substrate 200 includes an organic light emitting diode (E).

Example 8

12A to 12D are cross-sectional views illustrating processes in a method of manufacturing a display device according to an eighth embodiment of the present invention.

Referring to FIG. 12A, the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, and the first gate signal relay wiring 310 are disposed on the substrate 100. ), A second gate signal relay wiring 410 and a gate pad electrode 710 are formed.

The substrate 100 is transparent and is an insulator. The substrate 100 may be, for example, a glass substrate, a quartz substrate, and a film.

The gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, the second gate signal relay wiring 410, and In order to form the gate pad electrode 710, a metal film is formed over the entire surface of the substrate 100. Examples of the material that can be used as the metal film include aluminum, aluminum alloy, copper, molybdenum and titanium. After the metal film is formed, a photoresist film including a photosensitive material is formed on the metal film. The photoresist film is patterned through a photo process including an exposure process and a developing process, and a photoresist pattern is formed on the metal film. The metal layer is patterned by using the photoresist pattern as an etching mask, and the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, and the first substrate are formed on the substrate. The first gate signal relay wiring 310, the second gate signal relay wiring 410, and the gate pad electrode 710 are formed.

The gate wiring 110 is formed in the first direction, and the first gate electrode 111 is branched from the gate wiring 110. The gate wiring 110 and the first gate signal relay wiring 310 are integrally formed. The second gate electrode 112 is electrically connected to the first capacitor electrode 113. The second gate signal relay wiring 410 is formed spaced apart from each other at a predetermined interval on the first gate signal relay wiring 310, and the second gate signal relay wiring 410 and the gate pad electrode 710 are integrally formed. do.

The gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, the second gate signal relay wiring 410, and After the gate pad electrode 710 is formed, the gate wiring 110, the first gate electrode 111, the second gate electrode 112, the first capacitor electrode 113, the first gate signal relay wiring 310, An insulating layer 140 is formed to cover the second gate signal relay wiring 410 and the gate pad electrode 710. The insulating layer 140 includes a contact hole exposing a part of the second gate electrode 112. Examples of a material that may be used as the insulating layer 140 include silicon oxide, silicon nitride, and the like.

Referring to FIG. 12B, after the insulating layer 140 is formed, a channel pattern 150 is formed on the insulating layer 140.

In order to form the channel pattern 150, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially formed on the insulating film 140 over the entire area. The material used as the amorphous silicon thin film is amorphous silicon, and the material used as the n + amorphous silicon thin film is amorphous silicon implanted with a high concentration of impurities. Thereafter, a photoresist film is formed on the n + amorphous silicon thin film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the n + amorphous silicon thin film. The photoresist pattern has a shape corresponding to the channel pattern 150. The amorphous silicon thin film and the n + amorphous silicon thin film are patterned by using the photoresist pattern as an etching mask, and a channel pattern 150 is formed on the insulating layer 140.

The channel pattern 150 includes a first channel pattern 150a and a second channel pattern 150b. The first channel pattern 150a is formed corresponding to the first gate electrode 111, and the first channel pattern 150a includes a first amorphous silicon pattern 151a and a first n + amorphous silicon pattern 152a. . The first amorphous silicon pattern 151a is formed on the insulating layer 140, and a pair of first n + amorphous silicon patterns 152a are formed on the first amorphous silicon pattern 151a so as to be spaced apart from each other at predetermined intervals. The second channel pattern 150b is formed corresponding to the second gate electrode 112, and the second channel pattern 150b forms the second amorphous silicon pattern 151b and the second n + amorphous silicon pattern 152b. Include. The second amorphous silicon pattern 151b is formed on the insulating layer 140, and the pair of second n + amorphous silicon patterns 152b are formed on the second amorphous silicon pattern 151b so as to be spaced apart from each other by a predetermined interval.

After the channel pattern 150 is formed, the data wiring 160, the first source electrode 161, the first drain electrode 162, the power supply wiring 130, the second source electrode 131, and the second drain electrode ( 132, the second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, and the second power signal relay wiring 430. The data pad electrode 810 and the power pad electrode 910 are formed.

Data wiring 160, first source electrode 161, first drain electrode 162, power supply wiring 130, second source electrode 131, second drain electrode 132, second capacitor electrode 133 ), The first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, the second power signal relay wiring 430, the data pad electrode 810, and the power supply. In order to form the pad electrode 910, a source / drain metal film is formed on the insulating layer 140. Examples of the material that can be used as the source / drain metal film include aluminum, aluminum alloy, copper, molybdenum and titanium. A photoresist film is then formed over the entire area on the source / drain metal film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the source / drain metal film. The source / drain metal layer is patterned using the photoresist pattern as an etching mask, and the data line 160, the first source electrode 161, the first drain electrode 162, and the power line are formed on the insulating layer 140. 130, the second source electrode 131, the second drain electrode 132, the second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, and the first The power signal relay wiring 330, the second power signal relay wiring 430, the data pad electrode 710, and the power pad electrode 810 are formed.

The data line 160 crosses the gate line 110 and is formed in a second direction. The first source electrode 161 branches from the data line 160 and contacts one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is spaced apart from the first source electrode 161 at a predetermined interval and contacts the other one of the pair of first n + amorphous silicon patterns 152a. The first drain electrode 162 is electrically connected to the second gate electrode 112. The power line 130 is formed in parallel with the data line 160. The second source electrode 131 is branched from the power supply line 130 and contacts one of the pair of second n + amorphous silicon patterns 152b. The second source electrode 131 is formed to surround the second drain electrode 132. The second drain electrode 132 is spaced apart from the second source electrode 131 by a predetermined interval and contacts the other one of the pair of second n + amorphous silicon patterns 152b. The second capacitor electrode 133 is branched from the power line 130 and formed to correspond to the first capacitor electrode 113.

The first data signal relay wiring 320 is integrally formed with the data wiring 160. The second data signal relay wiring 420 is spaced apart from the first data signal relay wiring 320 at a predetermined interval, and the interval may be 1 mm to 2 mm. The data pad electrode 810 is integrally formed with the second data signal relay wiring 420.

The first power signal relay wiring 330 is integrally formed with the power wiring 130. The second power signal relay wiring 430 is spaced apart from the first power signal relay wiring 330 at predetermined intervals, and the interval may be 1 mm to 2 mm. The power pad electrode 910 is integrally formed with the second power signal relay wiring 430.

Referring to FIG. 12C, the data wire 160, the first source electrode 161, the first drain electrode 162, the power source wire 130, the second source electrode 131, and the second drain electrode 132, The second capacitor electrode 133, the first data signal relay wiring 320, the second data signal relay wiring 420, the first power signal relay wiring 330, the second power signal relay wiring 430, the data pad A passivation layer 170 is formed to cover the electrode 810 and the power pad electrode 910.

In order to form the protective film 170, an inorganic film is formed on the substrate 100. Examples of the material that can be used as the inorganic film include silicon oxide and silicon nitride. After the inorganic film is formed, a photoresist film is formed over the entire surface of the inorganic film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the inorganic layer. The photoresist pattern corresponds to an inorganic layer corresponding to a portion of the second drain electrode 132, an inorganic layer corresponding to a portion of the first gate signal relay wiring 310, and a portion of the second gate signal relay wiring 410. An inorganic film corresponding to a portion of the inorganic film, a portion of the gate pad electrode 710, an inorganic film corresponding to a portion of the first data signal relay wiring 320, and a portion of the second data signal relay wiring 420. A base film, an inorganic film corresponding to a part of the data pad electrode 810, an inorganic film corresponding to a part of the first power signal relay wiring 330, an inorganic film corresponding to a part of the second power signal relay wiring 430, and An inorganic film corresponding to a part of the power pad electrode 910 is exposed. The inorganic layer is patterned using the photoresist pattern as an etching mask, and a protective layer 170 is formed on the substrate 100. In this case, an insulating film corresponding to a part of the first gate signal relay wiring 310, an insulating film corresponding to a part of the second gate signal relay wiring 410, and an insulating film corresponding to a part of the gate pad electrode 710 are removed.

The passivation layer 170 may include a first contact hole 171, a second contact hole 172, a third contact hole 173, a fourth contact hole 174, a fifth contact hole 175, and a sixth contact hole ( 176, a seventh contact hole 177, an eighth contact hole 720, a ninth contact hole 820, and a tenth contact hole 920. The first contact hole 171 exposes a part of the second drain electrode 162, the second contact hole 172 exposes a part of the first gate signal relay wiring 310, which will be described later, and the third contact hole. Reference numeral 173 exposes a portion of the second gate signal relay wiring 410. The fourth contact hole 174 exposes a portion of the first data signal relay wiring 320, and the fifth contact hole 175 exposes a portion of the second data signal relay wiring 420. The sixth contact hole 176 exposes a portion of the first power signal relay wiring 330, and the seventh contact hole 177 exposes a portion of the second power signal relay wiring 430. The eighth contact hole 720 exposes a portion of the gate pad electrode 710, the ninth contact hole 820 exposes a portion of the data pad electrode 810, and the tenth contact hole 920 represents a power pad. A portion of the electrode 910 is exposed.

After the passivation layer 170 is formed, the connection electrode 183, the transparent contact portion 500, the first anti-corrosion conductive layer 730, the second anti-corrosion conductive layer 830, and the third corrosion on the passivation layer 170. An anti-conductive film 930 is formed.

In order to form the connection electrode 183, the transparent contact portion 500, the first anti-corrosion conductive film 730, the second anti-corrosion conductive film 830, and the third anti-corrosion conductive film 930, the protective film 170 A transparent metal film is formed over the entire surface. Examples of the material that can be used as the transparent metal film include indium tin oxide, indium zinc oxide, and the like. After the transparent metal film is formed, a photoresist film is formed over the entire area on the transparent metal film. The photoresist film is patterned through a photo process, and a photoresist pattern is formed on the transparent metal film. The photoresist pattern corresponds to the connection electrode 183, the transparent contact portion 500, the first anti-corrosion conductive layer 730, the second anti-corrosion conductive layer 830, and the third anti-corrosion conductive layer 930. It has a shape. The transparent metal layer is patterned by using the photoresist pattern as an etching mask, and is connected to the connection electrode 183, the transparent contact portion 500, the first corrosion preventing conductive layer 730, and the second corrosion preventing layer on the protective layer 170. The conductive film 830 and the third anti-corrosion conductive film 930 are formed.

The connection electrode 183 is electrically connected to the second drain electrode 132 partially exposed by the first contact hole 171. The transparent contact part 500 includes a first transparent contact part 510, a second transparent contact part 520, and a third transparent contact part 530. The first transparent contact portion 510 is electrically connected to the first gate signal relay wiring 310 partially exposed by the second contact hole 172, and the second transparent contact portion 520 is connected to the third contact hole. An electrical connection is made to the second gate signal relay wiring 410 partially exposed by the reference numeral 173. The second transparent contact portion 520 is electrically connected to the first data signal relay wiring 320 partially exposed by the fourth contact hole 174, and the second transparent contact portion 520 is connected to the fifth contact hole. A portion 175 is electrically connected to the second data signal relay wiring 420 partially exposed. The third transparent contact portion 530 is electrically connected to the first power signal relay wiring 330 partially exposed by the sixth contact hole 176, and the third transparent contact portion 530 is connected to the seventh contact hole. A portion 177 is electrically connected to the second power signal relay wiring 430 partially exposed. The transparent contact member may have a length of about 1 mm to about 2 mm.

The first anti-corrosion conductive film 730 covers the eighth contact hole 720, and the first anti-corrosion conductive film 730 partially exposes the gate pad electrode 710 by the eighth contact hole 720. Is electrically connected to the. The second anticorrosion conductive layer 830 covers the ninth contact hole 820, and the second anticorrosion conductive layer 830 is partially exposed by the ninth contact hole 820. Is electrically connected to the. The third anti-corrosion conductive film 930 covers the tenth contact hole 920, and the third anti-corrosion conductive film 930 is partially exposed by the tenth contact hole 920. Is electrically connected to the.

12D, the connection electrode 183, the transparent contact portion 500, the first anti-corrosion conductive film 730, the second anti-corrosion conductive film 830, and the third anti-corrosion conductive film 930 are formed. Thereafter, the sealing member 600 is disposed on the substrate 100.

The sealing member 600 has a closed loop shape, and the sealing member 600 intersects with the transparent contact portion 500. The sealing member 600 has a closed loop shape and is disposed on the substrate 100. The sealing member 600 is disposed to intersect the transparent contact portion 500, and the end of the first signal relay line 300 and the second signal relay line 400 corresponding to the first signal relay line 300. Disposed between the ends. Examples of the material that can be used as the sealing member include photocurable resins and thermosetting resins.

After the sealing member 600 is disposed, the counter substrate 200 facing the substrate 100 is disposed on the sealing member 600. In this case, the organic light emitting diodes formed on the connection electrode 183 and the counter substrate 200 are electrically connected to each other. After the opposing substrate 200 is disposed, the light passing through the substrate 100 is irradiated to the sealing member 600, and the light passing through the opposing substrate 200 is irradiated to the sealing member 600. The sealing member 600 is cured by the light, and the substrate 100 and the counter substrate 200 are bonded by the sealing member 600. The sealing region is formed by the substrate 100, the counter substrate 200, and the sealing member 600.

At this time, the sealing member 600 is cured by the light passing through the substrate 100, and at the same time the sealing member 600 is cured by the light passing through the counter substrate 200. Since the sealing member 600 intersects with the transparent contact portion 500 and the transparent contact portion 500 is transparent, when the light is irradiated to the sealing member 600, the light is transmitted to the transparent contact portion 500. Pass through. Therefore, the transparent contact portion 500 is not disconnected or shorted by the light. In addition, since the transparent contact portion 500 is transparent, more light is irradiated onto the sealing member 600 than when it is opaque, and the bonding force between the sealing member 600 and the substrate 100 is increased. The light can be, for example, ultraviolet or laser.

Since the transparent contact portion is disposed to cross the sealing member and the transparent contact portion is transparent, the transparent contact portion is not disconnected or shorted in the process of irradiating light to the sealing member. In addition, since the transparent contact portion is transparent, more light is irradiated onto the sealing member than when it is opaque, and the adhesion between the sealing member and the substrate can be enhanced.

Claims (26)

Board; A sealing member interposed between the substrate and an opposing substrate disposed to face the substrate; A first signal relay wiring disposed in a sealing area sealed by the substrate, the opposing substrate, and the sealing member; A second signal relay line spaced apart from the first signal relay line and disposed in a non-display area surrounding the sealing area; And And a transparent contact portion electrically connected to the first signal relay wiring and the second signal relay wiring. The display device of claim 1, wherein the first signal relay line is electrically connected to a gate line disposed in one direction in the sealing area. The display device of claim 1, wherein the first signal relay line is electrically connected to a data line disposed in one direction in the sealing area. The display device of claim 1, wherein the first signal relay line is electrically connected to a power line arranged in one direction in the sealing area. The method of claim 1, A gate wiring disposed in the sealing region in a first direction; A data line crossing the gate line and disposed in the sealing region in a second direction; A thin film transistor electrically connected to the data line; And And a pixel electrode electrically connected to the thin film transistor, wherein the transparent contact portion and the pixel electrode are disposed on the same layer. The method of claim 1, A gate wiring disposed in the sealing region in a first direction; A data line crossing the gate line and disposed in the sealing region in a second direction; A switching thin film transistor electrically connected to the data line; A power supply wiring arranged parallel to the data wiring; And And a driving thin film transistor electrically connected to the power line. The display device of claim 6, further comprising a first electrode electrically connected to the driving thin film transistor, an organic emission layer formed on the first electrode, and a second electrode formed on the organic emission layer. An electrode is formed on the same layer. The display device of claim 6, further comprising a connection electrode electrically connected to the driving thin film transistor, the connection electrode being electrically connected to an opposite substrate facing the substrate, wherein the connection electrode and the transparent contact portion are formed on the same layer. Device. The display device of claim 1, further comprising a pad part electrically connected to the second signal relay wiring and electrically connected to a driving circuit. The method of claim 9, wherein the pad part includes a pad electrode electrically connected to the second signal relay wiring and a corrosion preventing conductive film covering the pad electrode, wherein the transparent contact part and the corrosion preventing conductive film are formed on the same layer. Display. The display device of claim 1, wherein the first signal relay line and the second signal relay line are spaced apart from each other by 1 mm to 2 mm. The display device of claim 1, wherein the transparent contact portion comprises at least one of indium tin oxide and indium zinc oxide. The display device of claim 1, wherein the first signal relay wiring and the second signal relay wiring are disposed on the same layer. The display device of claim 1, wherein the transparent contact portion is disposed to cross the sealing member. Forming a first signal relay wiring and a second signal relay wiring spaced apart from the first signal relay wiring on a substrate; Forming a transparent contact portion electrically connected to the first signal relay wiring and the second signal relay wiring; And And disposing a sealing member on the substrate, the sealing member separating the sealing area from the non-display area, between the first signal relay line and the second signal relay line. The method of claim 15, Forming the first signal relay wiring and the second signal relay wiring Forming the first signal relay wiring; And And forming a second signal relay line spaced apart from the first signal relay line. The method of claim 15, Forming a gate wiring arranged in a first direction on the substrate and a gate electrode branched from the gate wiring; Forming an insulating film covering the gate wiring and the gate electrode; Forming a channel pattern on the insulating film; Forming a source electrode in contact with the channel pattern, a data line disposed in a second direction, and a drain electrode spaced apart from the source electrode and in contact with the channel pattern on the insulating layer; And Forming a pixel electrode electrically connected to the drain electrode. The method of claim 17, wherein the forming of the transparent contact portion comprises forming the transparent contact portion and the pixel electrode together. The method of claim 15, Forming a gate wiring arranged in a first direction on the substrate and a gate electrode branched from the gate wiring; Forming an insulating film covering the gate wiring and the gate electrode; Forming a channel pattern on the insulating film; Forming a source electrode in contact with the channel pattern, a data line arranged in a second direction, a power line arranged in parallel with the data line, and a drain electrode spaced apart from the source electrode to contact the channel pattern on the insulating layer; step; And Forming an organic light emitting diode electrically connected to the drain electrode. The method of claim 19, wherein forming the organic light emitting diode Forming a first electrode electrically connected to the drain electrode; Forming an organic emission layer on the first electrode; And Forming a second electrode covering the organic emission layer. The method of claim 20, wherein in the forming of the first electrode, simultaneously forming the first electrode and the transparent contact portion. The method of claim 15, Forming a gate wiring arranged in a first direction on the substrate and a gate electrode branched from the gate wiring; Forming an insulating film covering the gate wiring and the gate electrode; Forming a channel pattern on the insulating film; A data wiring disposed in a second direction on the substrate, a power wiring disposed in parallel to the data wiring, a source electrode in contact with the channel pattern, and a drain electrode spaced apart from the source electrode and in contact with the channel pattern; Doing; And Forming a connection electrode electrically connected to the drain electrode. The method of claim 22, wherein in the forming of the connection electrode, simultaneously forming the connection electrode and the transparent contact portion. The method of claim 15, Arranging an opposing substrate facing the substrate on a sealing member; And And coupling the substrate and the counter substrate by irradiating light to the sealing member. The method of claim 24, wherein the light comprises at least one of ultraviolet light and laser light. The display device of claim 24, wherein in the bonding of the substrate and the opposing substrate, the sealing member is irradiated with light passing through the substrate and light passing through the opposing substrate to couple the substrate and the opposing substrate. Manufacturing method.

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