KR20150072829A - Thin film transistor array substrate and method of fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a manufacturing method thereof, capable of implementing a narrow bezel by reducing a bezel region. The thin film transistor array substrate according to the present invention includes a horizontal gate wire and a gate electrode which are formed on the substrate, a data wire which is formed to define a pixel region by intersecting the horizontal gate wire, a gate connection pattern whose one end is connected to the gate electrode, and a vertical gate wire which is connected to the other end of the gate connection pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate.

The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array substrate capable of reducing a bezel region and realizing a narrow bezel and a method of manufacturing the same.

In recent years, the demand for display devices has been increasing in accordance with the development of the information society. In response to this demand, in recent years, various display devices such as a liquid crystal display device (LD), a plasma display panel (PDP), an electro luminescent display (ELD) Display) have been studied, and some of them have already been used as display devices in various devices.

Among them, liquid crystal display devices are mostly used while substituting RT (athode Ray Tube) for the use of a portable image display device because of its excellent image quality, light weight, thinness and low power consumption. 2. Description of the Related Art [0002] A liquid crystal display device has been developed variously as a television and a computer monitor for receiving and displaying broadcast signals in addition to a mobile type application such as a monitor of a notebook computer.

The liquid crystal display device includes a color filter array substrate on which color filters are formed, a thin film transistor array substrate on which thin film transistors are formed, and a liquid crystal layer formed between the color filter array substrate and the thin film transistor array substrate.

A plurality of gate wirings and data wirings cross the thin film transistor array substrate to define pixel regions. A data driver (Data D-I) for supplying a data signal to the data line and a gate driver (Gate D-I) for supplying a scan signal to the gate line are formed.

However, in general, the data driver and the gate driver are formed on the other side of the thin film transistor array substrate. For example, the data driver is provided on the upper side of the substrate, and the gate driver is provided on the left and right sides of the substrate. As a result, the bezel region of the thin film transistor array substrate increases.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems and it is an object of the present invention to provide a thin film transistor capable of reducing a bezel area by providing a vertical gate wiring over a data line, And an object of the present invention is to provide an array substrate and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a thin film transistor array substrate comprising: a horizontal gate wiring formed on a substrate; A data line crossing the horizontal gate line and defining a pixel region; A vertical gate wiring arranged in parallel with the data wiring with a first protective layer and a second protective layer in between; And a gate connection pattern connecting the horizontal gate wiring and the vertical gate wiring.

The vertical gate wiring may overlap the data wiring.

The thin film transistor array substrate may further include a pixel electrode formed of the same material as the gate connection pattern, and the pixel electrode may be formed on the second passivation layer.

The second passivation layer may be formed of an organic insulating material to prevent parasitic capacitance between the vertical gate line and the data line.

The second protective layer may be a photoactive compound.

The thin film transistor array substrate may further include a gate pad electrode and a data pad electrode connected to the vertical gate line and the data line, respectively, and the gate pad and the data pad are connected to each other by the horizontal gate line and the data line May be disposed at the same end of the pixel region in which the defined unit pixels are arranged or may be arranged to face each other.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, including: forming a horizontal gate line on a substrate; Forming a gate insulating film covering the horizontal gate wiring, the gate insulating film including a gate contact hole exposing a part of the horizontal gate wiring; A data line crossing the horizontal gate line on the gate insulating layer to define a pixel region, a semiconductor layer constituting a channel of the switching device, and a source electrode and a drain electrode; Forming a first protective layer and a second protective layer including a gate contact hole and a drain contact hole on the data line, the source electrode, and the drain electrode; Forming a gate connection pattern on the second passivation layer to connect the vertical gate wiring and the pixel electrode to the vertical gate wiring and the horizontal gate wiring; Forming a third passivation layer including the pad portion contact hole on the vertical gate wiring, the pixel electrode, and the gate connection pattern; And forming a common electrode and pad portion connection wiring on the third passivation layer.

The vertical gate wiring, the gate connection pattern, and the pixel electrode can be formed using the same mask.

Further, the semiconductor layer, the source electrode, the drain electrode, and the data line can be formed using the same mask.

The step of forming the horizontal gate wiring on the substrate may include forming the gate pad electrode and the data pad electrode simultaneously.

According to the present invention, the gate driver for connecting the vertical gate wiring and the horizontal gate wiring and for driving the horizontal gate wiring is provided on the upper side or the lower side of the substrate like a data driver, and a bezel region There is an effect of reducing the width of the light emitting diode.

1 is a plan view of a thin film transistor array substrate according to the present invention.
2 is a cross-sectional view taken along line I-I 'of Fig. 1
3A to 3E are process plan views showing a method of manufacturing a thin film transistor array substrate according to the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

Hereinafter, a thin film transistor array substrate of the present invention will be described.

1 is a plan view of a thin film transistor array substrate according to the present invention, and FIG. 2 is a sectional view taken along line I-I 'of FIG.

1 and 2, the thin film transistor array substrate of the present invention includes a substrate 110, a horizontal gate wiring 111, a vertical gate wiring 118 connected to the horizontal gate wiring 111, a data wiring 114, A first passivation layer 115, a second passivation layer 116, a gate connection pattern 117a, a pixel electrode 117b, a third passivation layer 119, and a common electrode 120. The thin film transistor, the first passivation layer 115, the second passivation layer 116,

The horizontal gate line 111 and the data line 114 cross each other and a pixel region is defined. Particularly, in order to reduce the bezel area, the vertical gate wiring 118 and the horizontal gate wiring 111, which are parallel to the data wiring 114 and overlap the data wiring 114, And are connected to each other through the gate connection pattern 117a. Therefore, a gate driver (Gate D-I) for supplying a scan signal to the horizontal gate line 111 can be formed on the substrate 110 or on the lower side of the substrate 110 like a data driver (Data D-I).

Specifically, the thin film transistor includes a gate electrode 111b, a gate insulating film 112, a semiconductor layer 113a, a source electrode 114a, and a drain electrode 114b.

The gate electrode 111b protrudes from the horizontal gate wiring 111 or is defined as a partial area of the horizontal gate wiring 111. [ In the figure, the gate electrode 111b is defined as a partial region of the horizontal gate wiring 111.

At this time, the gate pad is not formed at one end or the other end of the gate wiring 106.

A gate insulating film 112 is formed so as to cover the horizontal gate wiring 111 and the gate electrode 111b. The gate insulating film 112 is formed of a material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like.

At this time, the gate insulating film 112 is provided with a gate contact hole 301H for exposing the gate wiring 111. [ And the gate contact hole 301H is a portion overlapping the gate connection pattern 117a.

An aluminum alloy (AlNd), a copper (u), a copper alloy, a molybdenum (Mo), a molybdenum alloy (MoTi), and the like are formed on the gate insulating film 112 so as to cross the horizontal gate wiring 111, A plurality of data lines 114 made of any one or two or more materials are formed.

At this time, the horizontal gate wiring 111 and the data wiring 114 cross each other,

Is defined as a pixel region.

A semiconductor layer 113a is formed so as to overlap the gate electrode 111b and a source electrode 114a and a drain electrode 114b are formed on the semiconductor layer 113a.

The source electrode 114a is connected to the data line 114 and the semiconductor layer 113a, the source electrode 114a and the drain electrode 114b and the data line 114 are formed in accordance with the manufacturing method. When a halftone mask is formed by the same mask process, a semiconductor pattern 113b made of the same material as the semiconductor layer 113a is further formed under the data line 114. [ Such a semiconductor pattern 113b may be omitted by a manufacturing method.

The source electrode 114a and the drain electrode 114b spaced apart from each other by the gate electrode 111b, the gate insulating film 112 and the semiconductor layer 113a sequentially stacked in the respective switching regions TrA are connected to the thin film transistors Tr).

A first protective layer 115 made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) and a second protective layer 115 made of an organic insulating material, for example, photo- 2 protective layer 116 is provided with a flat surface.

The first passivation layer 115 and the second passivation layer 116 are formed on the gate contact hole 301H and the drain electrode 114b exposing a part of the horizontal gate wiring 111, (302H).

A gate connection pattern 117a, a pixel electrode 117b and a vertical gate wiring 118 are formed as a transparent conductive material on the second passivation layer 116 by the same mask process using a halftone mask. At this time, the vertical gate wiring 118 overlaps with the data wiring 114 and is formed on the gate connection pattern 117a. The transparent conductive material may be a material such as a tin oxide (TO), an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium tin zinc oxide (ITZO) to be.

The gate connection pattern 117a connects the horizontal gate wiring 111 and the vertical gate wiring 118 exposed through the gate contact hole 301H to each other and is formed of a transparent conductive material. Therefore, the horizontal gate wiring 111 and the vertical gate wiring 118 are connected through the gate connection pattern 117a. One end of the vertical gate wiring 118 extends to a non-display region (not shown) located on the upper side of the display region, and a gate pad (not shown) is provided at one end thereof.

That is, when a signal voltage is applied from a driver or a printed circuit board (not shown) which is in contact with the gate connection pattern 117a through a gate pad (not shown) provided at one end of the gate connection pattern 117a, The scan signal of the wiring 118 is transferred to the horizontal gate wiring 111. [ A pixel electrode 117b is formed on the second passivation layer 116 to be connected to the drain electrode 114b exposed through the drain contact hole 302H. The pixel electrode 117b is formed in the shape of a tubular electrode.

A third passivation layer 119 is formed on the vertical gate wiring 118 so as to cover the entire surface of the substrate 110. The third passivation layer 119 is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. A common electrode 120 is formed on the third passivation layer 119. The common electrode 120 is formed on the entire surface of the substrate 110 and has a plurality of slits exposing the third passivation layer 119. The common electrode 120 overlaps the pixel electrode 117b with the third passivation layer 119 interposed therebetween to generate a fringe electric field.

That is, the thin film transistor array substrate of the present invention has the vertical gate wiring 118 on the second protective layer 116, and is connected to the horizontal gate wiring 111 through the gate connection pattern 117a. That is, since the vertical gate line 118 is formed to overlap the data line 114, the bezel region can be reduced because the data driver and the gate driver are provided on one side of the TFT array substrate.

A plurality of gate pad electrodes (not shown) and data pad electrodes (not shown) connected to the external driving circuit are formed on the upper and left non-display regions of the array substrate 10, (Not shown).

In addition, a plurality of vertical gate wirings 118 connected to the respective gate pad electrodes (not shown) through the gate link wirings (not shown) and extending in the vertical direction are formed in the display region of the array substrate 10, And is connected to each of the data pad electrodes (not shown) and the data link wiring (not shown).

Hereinafter, a manufacturing method of the thin film transistor array substrate according to the present invention will be described in detail.

FIGS. 3A to 3E are process plan views illustrating a method of manufacturing a thin film transistor array substrate of the present invention, and FIGS. 4A to 4G are process sectional views illustrating a method of manufacturing a thin film transistor array substrate of the present invention.

As shown in FIGS. 3A and 4A, a horizontal gate wiring line 111 and a gate electrode 111b are formed on a substrate 110 by a first mask process. At this time, the gate electrode 111b is protruded from the horizontal gate wiring 111 or defined as a partial area of the horizontal gate wiring 111. [ The horizontal gate wiring 111 and the gate electrode 111b are formed of an opaque conductive material. The opaque conductive material is Mo, Ti, u, AlNd, Al, r, Mo alloy, u alloy, Al alloy and the like.

At this time, the gate pad is not formed at one end or the other end of the gate wiring 106.

Then, a gate insulating film is formed on the horizontal gate wiring 111 and the gate electrode 111b. At this time, the gate insulating film includes a material such as silicon oxide (SiOx), silicon nitride (SiNx) and the like.

A semiconductor layer 113a, a source electrode 114a, a drain electrode 114b and a data line 114 are formed on a gate insulating film 112 by using a halftone mask as a second mask process, as shown in FIGS. 3B and 4B, Are formed by the same mask process. The source electrode 114a, the drain electrode 114b and the data line 114 may be formed of a metal such as aluminum (Al), aluminum alloy (AlNd), copper (u), copper alloy, molybdenum (Mo) MoTi). ≪ / RTI >

Specifically, the semiconductor layer 113a is formed on the gate insulating film 112 so as to overlap with the gate electrode 111b, the source electrode 114a and the drain electrode 114b are formed on the semiconductor layer 113a, Spaced apart. The data wiring 114 is formed to cross the horizontal gate wiring 111 and the gate insulating film 112. Particularly, since the semiconductor layer 113a and the data line 114 are formed by the same mask process as described above, the semiconductor pattern 113b is formed under the data line 114 with the same material as the semiconductor layer 113a.

At this time, the source electrode 114a is connected to the data line 130, and the semiconductor layer 113a, the source electrode 114a, the drain electrode 114b, and the data line 114 are formed using different masks The semiconductor pattern 113b may be omitted under the data line 114. In this case,

The source electrode 114a and the drain electrode 114b which are spaced apart from the sequentially stacked gate electrode 111b, the gate insulating layer 112 and the semiconductor layer 113a constitute a thin film transistor which is a switching element.

3C, 4C, and 4D, a first protective layer 115 made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) is sequentially formed on the data line and the thin film transistor Tr Thereby forming a second protective layer 116 made of an organic insulating material such as photo-acryl, which forms a flat surface. Specifically, as shown in 4c, the second passivation layer 116 is selectively removed by a third mask process to selectively remove the upper portion of the horizontal gate wiring 111 and the upper portion of the drain electrode. The first passivation layer 115 and the gate insulating film 112 at the same position removed in the previous mask step are removed by a halftone mask which is a fourth mask process such as 4d to form the gate contact hole 301H and the drain contact hole 302H.

The gate contact hole 301H exposes the gate insulating film 112 and exposes a part of the horizontal gate wiring 111 at the same time. The drain contact hole 302H exposes the drain electrode 114b.

The reason for forming such a double layer protective layer structure is to enhance the bonding strength with the pixel electrode formed on the second passivation layer 116 and further to improve the characteristics of the thin film transistor. In addition, since the organic insulating material is formed on the inorganic insulating material, generation of parasitic capacitance can be minimized. The bonding strength between the organic insulating material and the conductive material is weaker than the bonding force between the organic insulating material and the inorganic insulating material and the bonding strength between the inorganic insulating material and the conductive material. Therefore, the inorganic insulating material layer is interposed between the organic conductive material and the conductive material . In addition, since the active layer exposed between the source and drain electrodes has poor interface characteristics when the surface of the active layer is in contact with the organic insulating material, deterioration of the characteristics may occur. To prevent this, an inorganic insulating material having excellent interfacial characteristics In order to promote improvement.

Next, a transparent conductive material and an opaque conductive material are sequentially formed on the second passivation layer 116, as shown in FIGS. 3D and 4E. Then, in the fifth mask process, the opaque conductive material is patterned to form the vertical gate wiring 118, and the transparent conductive material is patterned to form the pixel electrode 117b and the gate connection pattern 117a. At this time, it is preferable to use a halftone mask.

Specifically, a transparent conductive material and an opaque conductive material are sequentially formed on the second protective layer 116. The transparent conductive material may be a material such as a tin oxide (TO), an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium tin zinc oxide (ITZO) to be. The opaque conductive material is Mo, Ti, u, AlNd, Al, r, Mo alloy, u alloy, Al alloy and the like.

Then, a first photoresist pattern is formed on the opaque conductive material using a halftone mask. The first photoresist pattern is formed so as to correspond only to the region where the pixel electrode 117b and the gate connection pattern 117a are to be formed.

Then, using the first photoresist pattern as a mask, the exposed opaque conductive material and the transparent conductive material are removed. Then, the first photoresist pattern is ashed to form a second photoresist pattern remaining only in a region where the vertical gate electrode 118 is to be formed. Then, the exposed opaque conductive material is removed using the second photoresist pattern as a mask to form the pixel electrode 117b and the gate connection pattern 117a made of a transparent conductive material only. Then, the second photoresist pattern is removed to form a vertical gate wiring 118 on the gate connection pattern 117a.

Specifically, the pixel electrode 117b is connected to the drain electrode 114b exposed through the drain contact hole 302H, and is formed in a tubular electrode shape. The gate connection pattern 117a connects the vertical gate wiring 118 and the horizontal gate wiring 111 exposed by the gate contact hole 301H with each other.

The gate connection pattern 117a connects the horizontal gate wiring 111 and the vertical gate wiring 118 exposed through the gate contact hole 301H to each other and is formed of a transparent conductive material. Therefore, the horizontal gate wiring 111 and the vertical gate wiring 118 are connected through the gate connection pattern 117a. That is, the vertical gate wiring 118 and the horizontal gate wiring 111 provided in the different layers of the gate connection pattern 117a are connected to each other, and the scan signal of the vertical gate wiring 118 through the gate connection pattern 117a Is transferred to the horizontal gate wiring 111. A pixel electrode 117b is formed on the second passivation layer 116 to be connected to the drain electrode 114b exposed through the drain contact hole 302H. The pixel electrode 117b is formed in the shape of a tubular electrode.

Next, although not shown, a third passivation layer 119 is formed on the second passivation layer 116 to cover the pixel electrode 117b and the gate connection pattern 117a. At this time, the third passivation layer 119 is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. A pad portion contact hole (not shown) exposing a part of the gate insulating layer 112, the first passivation layer 115, and the third passivation layer 119 is formed by a sixth mask process.

A photoresist pattern (not shown) is formed on the third passivation layer 119 by performing a mask process on the photoresist, and the photoresist pattern (not shown) The insulating layer 112, the first passivation layer 115, and the third passivation layer 119, as shown in FIG.

3E and 4F, the common electrode 120 is formed on the third passivation layer 119 by a seventh mask process. The common electrode 120 is formed on the entire surface of the substrate 110 and has a plurality of slits exposing the third passivation layer 119. The common electrode 120 overlaps the pixel electrode 117b with the third passivation layer 119 interposed therebetween to generate a fringe electric field.

At this time, when the pad region is viewed in detail, connection wirings (not shown) are formed on the substrate on which the pad portion contact holes (not shown) are formed. The connection wiring (not shown) is connected to a gate pad electrode (not shown) and a data pad electrode (not shown) through a link portion contact hole (not shown).

That is, the thin film transistor array substrate of the present invention has the vertical gate wiring 118 on the second protective layer 116, and is connected to the horizontal gate wiring 111 through the gate connection pattern 117a. That is, since the vertical gate line 118 is formed to overlap the data line 114, the bezel region can be reduced because the data driver and the gate driver are provided on one side of the TFT array substrate.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

110: substrate 111: horizontal gate wiring
111b: gate electrode 112: gate insulating film
113a: semiconductor layer 113b: semiconductor pattern
114: data line 114a: source electrode
114b: drain electrode 115: first protective layer
116: second protection layer 117a: gate connection pattern
117b: pixel electrode 118: vertical gate wiring
119: third protection layer 120: common electrode
301H: Gate contact hole 302H: Drain contact hole

Claims (10)

A horizontal gate wiring formed on the substrate;
A data line crossing the horizontal gate line and defining a pixel region;
A vertical gate wiring arranged in parallel with the data wiring with a first protective layer and a second protective layer in between;
And a gate connection pattern connecting the horizontal gate wiring and the vertical gate wiring.
The method according to claim 1,
Wherein the vertical gate wiring overlaps with the data wiring.
The method according to claim 1,
And a pixel electrode formed of the same material as the gate connection pattern, wherein the pixel electrode is formed on the second passivation layer.
The method according to claim 1,
Wherein the second protective layer is formed of an organic insulating material to prevent parasitic capacitance between the vertical gate line and the data line.
5. The method of claim 4,
Wherein the second protective layer is a photosensitive compound (Photo Active Compound).
The method according to claim 1,
A gate pad electrode and a data pad electrode connected to the vertical gate wiring and the data wiring, respectively, wherein the gate pad and the data pad are formed in the same pixel region in which the unit pixels defined by the horizontal gate wiring and the data wiring are arranged And are arranged at one end or facing each other.
Forming a horizontal gate wiring on the substrate;
Forming a gate insulating film covering the horizontal gate wiring, the gate insulating film including a gate contact hole exposing a part of the horizontal gate wiring;
A data line crossing the horizontal gate line on the gate insulating layer to define a pixel region, a semiconductor layer constituting a channel of the switching device, and a source electrode and a drain electrode;
Forming a first protective layer and a second protective layer including a gate contact hole and a drain contact hole on the data line, the source electrode, and the drain electrode;
Forming a gate connection pattern on the second passivation layer to connect the vertical gate wiring and the pixel electrode to the vertical gate wiring and the horizontal gate wiring;
Forming a third passivation layer including the pad portion contact hole on the vertical gate wiring, the pixel electrode, and the gate connection pattern;
And forming a common electrode and pad portion connection wiring on the third passivation layer.
8. The method of claim 7,
Wherein the vertical gate wiring, the gate connection pattern, and the pixel electrode are formed using the same mask.
8. The method of claim 7,
Wherein the semiconductor layer, the source electrode, the drain electrode, and the data wiring are formed using the same mask.
8. The method of claim 7,
Wherein forming the horizontal gate wiring on the substrate comprises simultaneously forming the gate pad electrode and the data pad electrode.

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