JP2011232641A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of suppressing electrostatic breakdown.SOLUTION: The liquid crystal display device includes: an insulating substrate; a first substrate including gate wiring extending along a first direction above the insulating substrate, source wiring extending along a second direction crossing the first direction above the insulating substrate, a guard ring wiring which extends along at least the second direction and is spaced from the gate wiring and source wiring, a first wiring which is closest to the guard ring wiring between the source wiring and the guard ring wiring and extends along the second direction, and a second wiring which is closest to the first wiring between the source wiring and the first wiring and extends along the second direction; a second substrate facing the first substrate; and a liquid crystal layer held between the first substrate and the second substrate. The first wiring is spaced from the guard ring wiring and the second wiring, and the shortest distance between the first wiring and the guard ring wiring is longer than that between the first wiring and the second wiring.

Description

  The present invention relates to a liquid crystal display device.

  In recent years, flat display devices have been actively developed, and among them, liquid crystal display devices have been applied to various fields by taking advantage of features such as light weight, thinness, and low power consumption.

  In such a liquid crystal display device, a guard ring is disposed on the periphery of the substrate in order to prevent electrostatic breakdown due to static electricity charged during the manufacturing process or after manufacturing. The charges induced on the substrate by external static electricity are concentrated on the guard ring, and the charges are less likely to be induced on other wirings. For this reason, electrostatic breakdown that causes failure of the liquid crystal display device is less likely to occur. However, the charge induced in the guard ring induces a charge on another wiring on the substrate, and a high electric field is generated between the two, causing a discharge, and the switching element connected to the wiring is electrostatically destroyed. is there.

  For example, Patent Document 1 discloses a substrate for a liquid crystal display device having a guard ring that is disposed at the edge of the substrate so as to be electrically insulated from other wiring, and a method for manufacturing the same. In particular, the guard ring is formed of a lower layer portion formed of a conductive film having a first resistivity and a conductive film having a second resistivity lower than the first resistivity on the lower layer portion. And an upper layer portion that is separated into an inner peripheral portion and an outer peripheral portion at intervals of. With such a configuration, when a high potential static electricity is charged in the guard ring, an arc discharge occurs between the inner and outer peripheral portions, the potential charged in the guard ring is lowered, and the card ring and other wiring are connected. It is intended to prevent arc discharge between them.

JP 2002-287159 A

  An object of the present invention is to provide a liquid crystal display device capable of suppressing electrostatic breakdown.

According to one aspect of the invention,
An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first substrate comprising: a first wiring; and a second wiring that is closest to the first wiring and extends along a second direction between the source wiring and the first wiring, and the first substrate. And a liquid crystal layer held between the first substrate and the second substrate, wherein the first wiring is separated from the guard ring wiring and the second wiring, Before the first wiring The liquid crystal display device the shortest distance between the guard ring line is equal to or longer than the shortest distance between the second wiring and the first wiring is provided.

According to another aspect of the invention,
An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first substrate comprising: a first wiring; a metal pattern that is disposed between the edge of the insulating substrate and the guard ring wiring and is in an electrically floating state; and a second substrate facing the first substrate And a liquid crystal layer held between the first substrate and the second substrate, wherein the first wiring is separated from the guard ring wiring and the metal pattern, and the first wiring The liquid crystal display device the shortest distance between the guard ring line is equal to or longer than the shortest distance between the metal pattern and the guard ring line is provided.

According to another aspect of the invention,
An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first wiring, a second wiring that is closest to the first wiring and extends in a second direction between the source wiring and the first wiring, an edge of the insulating substrate, and the guard ring wiring; Between the first substrate and the second substrate, the second substrate facing the first substrate, and held between the first substrate and the second substrate. A liquid crystal layer, wherein the first wiring is separated from the guard ring wiring, the second wiring, and the metal pattern, and a shortest distance between the first wiring and the guard ring wiring is the first wiring. A liquid crystal display device, wherein the shortest distance between the first wiring and the guard ring wiring is longer than the shortest distance between the guard ring wiring and the metal pattern. Is provided.

  According to this invention, a liquid crystal display device capable of suppressing electrostatic breakdown can be provided.

FIG. 1 schematically shows a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG. FIG. 3 is a diagram schematically showing a cross-sectional structure of the array substrate constituting the liquid crystal display panel shown in FIG. 4 is a plan view schematically showing an array substrate constituting the liquid crystal display panel shown in FIG. FIG. 5 is an enlarged view of a region A including the guard ring wiring, the first wiring, and the second wiring shown in FIG. FIG. 6 is an enlarged view of a region B including the guard ring wiring and the metal pattern shown in FIG.

  Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 connected to the liquid crystal display panel LPN, a flexible wiring board 3, and the like.

  The liquid crystal display panel LPN is held between an array substrate (first substrate) AR, a counter substrate (second substrate) CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. The active area ACT is composed of a plurality of pixels PX arranged in a matrix of m × n (where m and n are positive integers).

  The driving IC chip 2 and the flexible wiring board 3 are mounted on the array substrate AR and function as a signal supply source that supplies signals necessary for driving the pixels PX.

  FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG.

  In the active area ACT, the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like. ing. Each pixel PX includes a switching element SW electrically connected to the gate line G and the source line S, a pixel electrode PE electrically connected to the switching element SW, and a common facing the pixel electrode PE via the liquid crystal layer LQ. A common electrode CE having a potential is provided. The storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE.

  Each gate line G is drawn outside the active area ACT and connected to the gate line drive circuit GD. Such a gate wiring drive circuit GD may be formed on both sides of the active area ACT, but in the illustrated example, it is formed only on one side. Each source line S is drawn outside the active area ACT and connected to the source line drive circuit SD. In the illustrated example, each auxiliary capacitance line C is drawn to the outside of the active area ACT and connected to the auxiliary capacitance line drive circuit CD formed on the opposite side of the gate line drive circuit GD across the active area ACT. Yes. The gate line driving circuit GD, the source line driving circuit SD, and the auxiliary capacitance line driving circuit CD are formed on, for example, the array substrate AR and connected to the driving IC chip 2.

  In the illustrated example, the drive IC chip 2 is mounted outside the active area ACT of the liquid crystal display panel LPN. The liquid crystal display panel LPN is formed with terminals TA, TB, and TC for connecting a flexible wiring board. The plurality of terminals TA are arranged between the terminal TB and the terminal TC, and are connected to the driving IC chip 2 through various wirings. The terminals TB and TC are connected to a guard ring wiring GR disposed on the periphery of the liquid crystal display panel LPN. The guard ring wiring GR functions as a common wiring, for example, and is electrically connected to the common electrode CE.

  In the present embodiment, the liquid crystal display panel LPN may have a configuration in which a horizontal electric field mode is applied, or may have a configuration in which a vertical electric field mode is applied. In the liquid crystal display panel LPN to which the horizontal electric field mode is applied, the array substrate AR includes the pixel electrode PE and the common electrode CE, and a horizontal electric field (that is, an electric field substantially parallel to the main surface of the substrate) formed therebetween is mainly used. Is used to switch the liquid crystal molecules constituting the liquid crystal layer LQ. In the liquid crystal display panel LPN to which the vertical electric field mode is applied, the array substrate AR is provided with the pixel electrode PE, the counter substrate CT is provided with the common electrode CE, and the vertical electric field formed between them (that is, on the main surface of the substrate). The liquid crystal molecules constituting the liquid crystal layer LQ are switched mainly using a substantially vertical electric field).

  FIG. 3 is a diagram schematically showing a cross-sectional structure of the array substrate AR constituting the liquid crystal display panel LPN shown in FIG.

  That is, the array substrate AR is formed by using an insulating substrate 20 having a light transmission property such as a glass plate. The array substrate AR includes a switching element SW on the upper surface of the insulating substrate 20 in the active area ACT. The switching element SW shown here is a top-gate thin film transistor (TFT). The switching element SW includes a semiconductor layer SC.

  The semiconductor layer SC can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here. Such a semiconductor layer SC is disposed on the insulating substrate 20 and covered with the gate insulating film 21. The gate insulating film 21 is also disposed on the insulating substrate 20.

  The gate electrode WG of the switching element SW is disposed on the gate insulating film 21 and is located immediately above the semiconductor layer SC. The gate electrode WG is electrically connected to the gate wiring G. In the illustrated example, the gate electrode WG is formed integrally with the gate wiring G. The auxiliary capacitance line C is disposed on the gate insulating film 21 that is the same layer as the gate electrode WG.

  Further, outside the active area ACT, the guard ring wiring GR is disposed on the gate insulating film 21 which is the same layer as the gate electrode WG.

  The gate electrode WG, the gate line G, the auxiliary capacitance line C, and the guard ring line GR are covered with the first interlayer insulating film 22. The first interlayer insulating film 22 is also disposed on the gate insulating film 21. The gate insulating film 21 and the first interlayer insulating film 22 are formed of an inorganic material such as silicon nitride (SiN).

  The source electrode WS and the drain electrode WD of the switching element SW are disposed on the first interlayer insulating film 22. The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the gate insulating film 21 and the first interlayer insulating film 22. The source electrode WS is electrically connected to the source line S. In the illustrated example, the source electrode WS is formed integrally with the source line S.

  The gate electrode WG, the source electrode WS, and the drain electrode WD are formed of a conductive material such as molybdenum, aluminum, tungsten, or titanium. The gate electrode WG, the gate wiring G, the auxiliary capacitance line C, and the guard ring wiring GR are formed in the same process using the same material. The source wiring S, the source electrode WS, and the drain electrode WD are formed in the same process using the same material.

  The source wiring S, the source electrode WS, and the drain electrode WD are covered with the second interlayer insulating film 23. The second interlayer insulating film 23 is also disposed on the first interlayer insulating film 22. The second interlayer insulating film 23 is formed of various organic materials such as an ultraviolet curable resin and a thermosetting resin.

  The pixel electrode PE is disposed on the second interlayer insulating film 23. The pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 23. Further, the pixel electrode PE is also located immediately above the auxiliary capacitance line C. Such a pixel electrode PE is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE and the second interlayer insulating film 23 are covered with a first alignment film 24.

  Although the common electrode CE is not illustrated, in the configuration in which the horizontal electric field mode is applied, the array substrate AR includes the common electrode CE that is electrically insulated from the pixel electrode PE, and in the configuration in which the vertical electric field mode is applied, A counter substrate (not shown) includes a common electrode CE.

  FIG. 4 is a plan view schematically showing the array substrate AR constituting the liquid crystal display panel LPN shown in FIG. In FIG. 4, the details of the active area ACT are not shown.

  The insulating substrate 20 constituting the array substrate AR has a substantially rectangular shape, a first end side 20A and a second end side 20B substantially parallel to the first direction X, and a third end side 20C substantially parallel to the second direction Y. And a fourth end side 20D. Above the insulating substrate 20, there are a gate line G, an auxiliary capacity line C, a source line S, a guard ring line GR, a gate line drive circuit GD, a source line drive circuit SD, an auxiliary capacity line drive circuit CD, and a terminal TA. , TB, TC, metal pattern MP, and the like are formed.

  The gate line G and the auxiliary capacitance line C extend along the first direction X in the active area ACT. The source line S extends along the second direction Y intersecting the first direction X in the active area ACT. The guard ring wiring GR is disposed outside the active area ACT and is separated from the gate wiring G, the auxiliary capacitance line C, and the source wiring S.

  The terminals TA, TB, and TC are arranged in the vicinity of the first end side 20A of the insulating substrate 20. In the array substrate AR, the drive IC chip 2 is mounted between the first end side 20A and the active area ACT. Between the plurality of terminals TA and the driving IC chip 2, a wiring W1 that electrically connects them is formed.

  The guard ring wiring GR may be formed as a series of uninterrupted rings, but in the example shown here, one end is connected to the terminal TB and the other end is connected to the terminal TC. There is a break between TB and terminal TC. Note that the pattern of the guard ring wiring GR is not limited to the illustrated example.

  The guard ring wiring GR is disposed on the peripheral edge corresponding to the vicinity of each end side of the insulating substrate 20. That is, the guard ring wiring GR extends along the second direction Y in the vicinity of the third end side 20C from the terminal TB in the vicinity of the first end side 20A, near the third end side 20C, and the second end side. The second end side 20B and the fourth end side 20D extend along the first direction X in the vicinity of the second end side 20B via the vicinity of the corner where 20B and the third end side 20C intersect. It extends along the second direction Y in the vicinity of the fourth end side 20D through the vicinity of the intersecting corner, and further passes through the outside of the driving IC chip 2 to the terminal TC in the vicinity of the first end side 20A. It is formed continuously.

  A part of such guard ring wiring GR, for example, in the vicinity of the corner where the second end side 20B and the fourth end side 20D intersect, is electrically connected to the common electrode CE formed on the counter substrate CT (not shown). A power feeding unit SP to be connected is formed. The power feeding unit SP is electrically connected to the common electrode CE via a conductive member (not shown).

  The source line drive circuit SD is formed between the active area ACT and the first end side 20A, and here, in particular, is formed between the active area ACT and the drive IC chip 2. The source line drive circuit SD extends substantially along the first direction X. A source line S drawn outside the active area ACT is connected to such a source line drive circuit SD. Between the source wiring driving circuit SD and the driving IC chip 2, a wiring W2 that electrically connects both is formed.

  The gate wiring drive circuit GD is formed between the active area ACT and the guard ring wiring GR along the third end side 20C. The gate line driving circuit GD extends substantially along the second direction Y. That is, the guard ring wiring GR is formed between the gate wiring driving circuit GD and the third end side 20C. The gate wiring G drawn out to the outside of the active area ACT is connected to such a gate wiring driving circuit GD.

  Between the gate wiring driving circuit GD and the driving IC chip 2, a wiring W3 that electrically connects both is formed. Such a wiring W3 is separated from the guard ring wiring GR, and is formed inside the guard ring wiring GR, that is, on the active area ACT side.

  The wiring W3 includes a first wiring W31 and a second wiring W32 extending along the second direction Y between the source wiring S of the active area ACT and the guard ring wiring GR outside the active area. The first wiring W31 is separated from the guard ring wiring GR, but is the wiring closest to the guard ring wiring GR. The second wiring W32 is a wiring closest to the first wiring W31 between the source wiring S and the first wiring W31. That is, the guard ring wiring GR, the first wiring W31, and the second wiring W32 are arranged in this order from the third end side 20C of the insulating substrate 20 toward the gate wiring driving circuit GD.

  The storage capacitor line drive circuit CD is formed between the active area ACT and the guard ring wiring GR along the fourth end side 20D. The storage capacitor line drive circuit CD extends substantially along the second direction Y. That is, the guard ring line GR is formed between the storage capacitor line drive circuit CD and the fourth end side 20D. An auxiliary capacitance line C drawn outside the active area ACT is connected to such an auxiliary capacitance line drive circuit CD.

  Between the auxiliary capacitance line drive circuit CD and the drive IC chip 2, a wiring W4 that electrically connects both is formed. Similar to the wiring W3, the wiring W4 is also separated from the guard ring wiring GR and is formed on the inner side of the guard ring wiring GR, that is, on the active area ACT side.

  The wiring W4 also includes the first wiring W41 and the second wiring W42 extending along the second direction Y between the source wiring S of the active area ACT and the guard ring wiring GR outside the active area. The first wiring W41 is equivalent to the first wiring W31 described above, and is the wiring closest to the guard ring wiring GR, although it is separated from the guard ring wiring GR. The second wiring W42 is equivalent to the second wiring W32 described above, and is the wiring closest to the first wiring W41 between the source wiring S and the first wiring W41. That is, the guard ring wiring GR, the first wiring W41, and the second wiring W42 are arranged in this order from the fourth end 20D of the insulating substrate 20 toward the storage capacitor line drive circuit CD.

  The metal pattern MP is disposed between any end side of the insulating substrate 20 and the guard ring wiring GR. Such a metal pattern MP is, for example, a mark engraved with a production number or a mark necessary for alignment, and is not connected to any wiring or circuit. That is, the metal pattern MP is in an electrically floating state. In the illustrated example, the metal pattern MP is formed in a substantially quadrangular shape, and is disposed in the vicinity of a corner where the first end side 20A and the third end side 20C intersect. The position where the metal pattern MP is arranged is not limited to the illustrated example.

  Next, the positional relationship between the guard ring wiring GR and the wiring inside the guard ring wiring GR will be described.

  FIG. 5 is an enlarged view of a region A including the guard ring wiring GR, the first wiring W31, and the second wiring W32 illustrated in FIG.

  The shortest distance dA between the first wiring W31 and the guard ring wiring GR is longer than the shortest distance dB between the first wiring W31 and the second wiring W32 (dA> dB). The guard ring wiring GR, the first wiring W31, and the second wiring W32 are disposed on the same layer (that is, disposed on the gate insulating film 21 that is the same layer as the gate wiring G and the like). In some cases (ie, one of the wirings is in the same layer as the gate wiring G and the other wiring is in the same layer as the source wiring S). . In any case, in the present embodiment, the shortest distance corresponds to an interval between wirings in the XY plane defined by the first direction X and the second direction Y.

  In the illustrated example, the shortest distance dA corresponds to the distance along the first direction X from the end of the guard ring wiring GR facing the first wiring W31 to the end of the first wiring W31 facing the guard ring wiring GR. The shortest distance dB corresponds to the distance along the first direction X from the end of the first wiring W31 facing the second wiring W32 to the end of the second wiring W32 facing the first wiring W31. . As an example, dB is about 10 μm while dB is about 100 μm.

  Here, the positional relationship between the guard ring wiring GR and the first wiring W31 and the second wiring W32 has been described with reference to FIG. 5, but the guard ring wiring GR and the first wiring W41 on the fourth end 20D side are described. This also applies to the positional relationship with the second wiring W42, and detailed description thereof is omitted.

  Next, the positional relationship between the guard ring wiring GR and the metal pattern MP outside thereof will be described.

  FIG. 6 is an enlarged view of a region B including the guard ring wiring GR and the metal pattern MP shown in FIG.

  The shortest distance dC between the guard ring wiring GR and the metal pattern MP is shorter than the shortest distance dA between the first wiring W31 and the guard ring wiring GR described above (dA> dC). Note that the guard ring wiring GR and the metal pattern MP may be arranged in the same layer or in different layers. In any case, in the present embodiment, the shortest distance corresponds to an interval in the XY plane defined by the first direction X and the second direction Y.

  In the illustrated example, the shortest distance dC corresponds to the distance along the first direction X from the end side facing the metal pattern MP of the guard ring wiring GR to the end side facing the guard ring wiring GR of the metal pattern MP. As an example, dC is about 100 μm, whereas dC is about 20 μm.

  When the array substrate AR having the above-described configuration is applied, the charges induced on the array substrate AR by external static electricity are concentrated on the guard ring wiring GR disposed on the peripheral edge of the array substrate AR.

  According to the present embodiment, the array substrate AR includes the guard ring wiring GR, the wiring adjacent to the inside of the guard ring wiring GR, for example, the first wiring W31, and the second wiring W32 adjacent to the inside of the first wiring W31. The shortest distance dA between the first wiring W31 and the guard ring wiring GR is longer than the shortest distance dB between the first wiring W31 and the second wiring W32. That is, the second wiring W32 is formed at a position separated from the first wiring W31 by a shortest distance dB that is smaller than the distance dA.

  As a result, even if the charge induced in the guard ring wiring GR is induced inside the guard ring wiring GR, the amount of charge can be dispersed. That is, even if charges are induced to the first wiring W31 and the second wiring W32, the distance from the guard ring wiring GR to the first wiring W31 is long, and the induced charges are the first wiring W31 and the second wiring. As a result, the amount of charge induced in the first wiring W31 and the second wiring W32 is reduced. Therefore, a high electric field is unlikely to be generated between the guard ring wiring GR and the wiring inside the guard ring wiring GR, and a discharge between them is suppressed, and the thin film transistor connected to various wirings such as the first wiring W31 and the second wiring W32. It is possible to suppress electrostatic breakdown of various circuits including the above.

  Similarly, the shortest distance dA between the guard ring wiring GR and the first wiring W41 is longer than the shortest distance dB between the first wiring W41 and the second wiring W42. For this reason, the amount of charge induced in the first wiring W41 and the second wiring W42 is reduced, and the same effect can be obtained.

  In addition, according to the present embodiment, the array substrate AR includes the guard ring wiring GR, the wiring adjacent to the inside of the guard ring wiring GR, for example, the first wiring W31, and the metal pattern MP adjacent to the outside of the guard ring wiring GR. The shortest distance dA between the first wiring W31 and the guard ring wiring GR is longer than the shortest distance dC between the guard ring wiring GR and the metal pattern MP.

  As a result, the charges induced in the guard ring wiring GR are more easily induced in the metal pattern MP on the outer side than the first wiring W31 on the inner side. Therefore, it is possible to reduce the amount of charge induced in the first wiring W31 due to the charge induced in the guard ring wiring GR, while generating a discharge between the guard ring wiring GR and the metal pattern MP. It becomes easy to do. Therefore, the discharge between the various wirings arranged inside the guard ring wiring GR such as the first wiring W31 and the second wiring W32 and the guard ring wiring GR is suppressed, and the first wiring W31 and the second wiring W32 are suppressed. It is possible to suppress electrostatic breakdown of various circuits including thin film transistors connected to various wirings.

  Similarly, the shortest distance dA between the guard ring wiring GR and the first wiring W41 is longer than the shortest distance dC between the guard ring wiring GR and the metal pattern MP. For this reason, it is possible to reduce the amount of charge induced in the first wiring W41. On the other hand, the guard ring wiring GR and the metal pattern MP are likely to be discharged, and the same effect can be obtained.

  In order to induce a discharge between the guard ring wiring GR and the metal pattern MP, it is desirable that the distance that the guard ring wiring GR and the metal pattern MP run in parallel at the shortest distance dC is long.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device LPN ... Liquid crystal display panel AR ... Array substrate CT ... Opposite substrate LQ ... Liquid crystal layer ACT ... Active area PX ... Pixel G ... Gate wiring C ... Auxiliary capacity line S ... Source wiring GD ... Gate wiring drive circuit SD ... Source wiring drive circuit CD ... Auxiliary capacitance line drive circuit TA ... Terminal TB ... Terminal TC ... Terminal GR ... Guard ring wiring MP ... Metal pattern W31 ... First wiring W32 ... Second wiring

Claims (5)

An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first substrate comprising: a first wiring; and a second wiring extending in the second direction closest to the first wiring between the source wiring and the first wiring;
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate,
The first wiring is separated from the guard ring wiring and the second wiring, and the shortest distance between the first wiring and the guard ring wiring is longer than the shortest distance between the first wiring and the second wiring. A characteristic liquid crystal display device. An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first substrate comprising: a first wiring; and an electrically floating metal pattern disposed between an edge of the insulating substrate and the guard ring wiring;
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate,
The first wiring is separated from the guard ring wiring and the metal pattern, and the shortest distance between the first wiring and the guard ring wiring is longer than the shortest distance between the guard ring wiring and the metal pattern. Liquid crystal display device. An insulating substrate; a gate wiring extending along a first direction above the insulating substrate; a source wiring extending along a second direction intersecting the first direction above the insulating substrate; The guard ring wiring extending along two directions and spaced apart from the gate wiring and the source wiring, and extending along the second direction closest to the guard ring wiring between the source wiring and the guard ring wiring. A first wiring, a second wiring that is closest to the first wiring and extends in a second direction between the source wiring and the first wiring, an edge of the insulating substrate, and the guard ring wiring; A first substrate comprising: a metal pattern disposed between and electrically floating;
A second substrate facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate,
The first wiring is separated from the guard ring wiring, the second wiring, and the metal pattern, and a shortest distance between the first wiring and the guard ring wiring is between the first wiring and the second wiring. A liquid crystal display device, wherein the liquid crystal display device is longer than a shortest distance, and a shortest distance between the first wiring and the guard ring wiring is longer than a shortest distance between the guard ring wiring and the metal pattern.   4. The liquid crystal display device according to claim 1, wherein the second substrate includes a common electrode that is electrically connected to the guard ring wiring. 5. The first substrate further includes a drive circuit extending along the second direction,
4. The liquid crystal display device according to claim 1, wherein the guard ring wiring is formed between the drive circuit and an edge of the insulating substrate along the second direction. 5. .

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