KR20080101158A - Fabrication method of transistor having silicide layer - Google Patents

Fabrication method of transistor having silicide layer Download PDF

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Publication number
KR20080101158A
KR20080101158A KR1020070047523A KR20070047523A KR20080101158A KR 20080101158 A KR20080101158 A KR 20080101158A KR 1020070047523 A KR1020070047523 A KR 1020070047523A KR 20070047523 A KR20070047523 A KR 20070047523A KR 20080101158 A KR20080101158 A KR 20080101158A
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KR
South Korea
Prior art keywords
film
semiconductor substrate
silicide
heat treatment
polysilicon pattern
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KR1020070047523A
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Korean (ko)
Inventor
김준석
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삼성전자주식회사
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Priority to KR1020070047523A priority Critical patent/KR20080101158A/en
Publication of KR20080101158A publication Critical patent/KR20080101158A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of manufacturing a transistor including a silicide film is provided. A polysilicon pattern is formed on the semiconductor substrate. A gate spacer having an excess of nitrided region is formed on the sidewall of the polysilicon pattern. Source / drain regions are formed in the semiconductor substrate adjacent to both sides of the polysilicon pattern. A silicide layer is formed on the polysilicon pattern and the source / drain regions.

Description

Fabrication method of transistor having silicide layer {Fabrication method of transistor having silicide layer}

1 is a process flowchart showing a method of forming a silicide film according to the prior art.

2 to 4 and 6 to 8 are cross-sectional views showing a method of manufacturing a transistor including a silicide film according to an embodiment of the present invention.

FIG. 5 is an enlarged cross-sectional view enlarging E of FIG. 4.

9 is a process flowchart showing a method of forming a silicide film according to an embodiment of the present invention.

The present invention relates to a method for manufacturing a transistor, and more particularly to a method for manufacturing a transistor having a silicide film.

As electronic products adopting semiconductor devices become smaller, lighter, and slimmer, high integration density, low threshold voltage (Vth), fast operation speed, and low power consumption are demanded in the semiconductor devices. According to the necessity of high integration as described above, the transistor adopted by the semiconductor device should be minimized as much as possible.

However, there are various problems as the transistor shrinks. For example, as the width of the gate electrode of the transistor narrows, the channel length of the transistor gradually decreases, thereby causing a short channel effect. In addition, the width of the gate electrode is narrowed to increase the electrical resistance of the gate electrode. As the electrical resistance of the gate electrode increases, the transmission speed of the electrical signal applied to the gate electrode becomes slow due to the resistance-capacitance delay time.

On the other hand, the method of reducing the electrical resistance of the gate electrode is described in US Patent No. 5,646,782 "Method to ensure isolation between source-drain and gate electrode using self aligned silicidation ”, as disclosed by Koh.

According to Koh, a metal film is formed on the semiconductor substrate on which the polysilicon gate electrode and the source / drain regions are formed. The semiconductor substrate is heat-treated to react silicon of the gate electrode and the source / drain regions with the metal film to form metal silicide. The formation of the metal silicide may reduce the electrical resistance of the gate electrode. In addition, the contact resistance of the source / drain regions can be reduced.

However, the metal silicide may be titanium silicide (TiSi) or cobalt silicide (CoSi). The titanium silicide and the cobalt silicide may react with silicon atoms of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film to form a parasitic silicide film. In addition, the gate spacer formed on the sidewall of the gate electrode generally includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. After forming the gate spacer, the metal silicide is formed. Therefore, when forming the metal silicide, there is a possibility that the metal silicide and the silicon atoms of the gate spacer react to form a parasitic silicide film. The parasitic silicide layer may provide a path of leakage current between the gate electrode and the source / drain region. This is a problem because the semiconductor device may not work properly.

Meanwhile, a method of forming a metal silicide is generally described with reference to FIG. 1. A metal film forming process S2 is performed on the polysilicon gate electrode having the gate spacer and the semiconductor substrate having the source / drain regions. The semiconductor substrate is subjected to a first heat treatment process (S4) at a first temperature (S4). In order to reduce the possibility that the parasitic silicide layer may be formed, a cleaning process S6 is performed after the first heat treatment process. Subsequently, a second heat treatment step S8 is performed at a second temperature higher than the first temperature. This has the problem of lengthening the process time.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a method of manufacturing a transistor including a silicide layer capable of electrically separating a gate electrode and a source / drain region.

According to an embodiment of the present invention for achieving the above technical problem, a method of manufacturing a transistor including a silicide film is provided. According to this method, a polysilicon pattern is formed on a semiconductor substrate. A gate spacer having an excess nitrogen region is formed on sidewalls of the polysilicon pattern. Source / drain regions are formed in the semiconductor substrate adjacent to both sides of the polysilicon pattern. A silicide layer is formed on the polysilicon pattern and the source / drain regions.

An isolation layer may be formed on the semiconductor substrate to define an active region.

The excess nitrogen region may be formed using a decoupled plasma nitridation (DPN) method. The excess nitrogen region may be formed along the surface of the gate spacer.

The silicide layer may be formed as follows. A metal film is formed on the semiconductor substrate having the polysilicon pattern, the gate spacer having the excess nitrogen region, and the source / drain regions. Subsequently, the semiconductor substrate is heat-treated to react the metal layer with the polysilicon pattern and the source / drain regions. As a result of the reaction, a silicide layer is formed on the polysilicon pattern and the source / drain regions.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the disclosed contents to be thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

2 to 4 and 6 to 8 are cross-sectional views illustrating a method of manufacturing a transistor including a silicide film according to an embodiment of the present invention, and FIG. 5 is an enlarged cross-sectional view of FIG. 4E. 9 is a process flowchart showing a method of forming a silicide film according to an embodiment of the present invention.

Referring to FIG. 2, an isolation layer 102 may be formed on the semiconductor substrate 100 to define the active region 104. The semiconductor substrate 100 may be a single crystal silicon wafer, and may have an n-type or p-type conductivity. The isolation layer 102 may be formed using a shallow trench isolation (STI) technique. In addition, the device isolation layer 102 may be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

A dielectric film may be formed on the semiconductor substrate 100. The dielectric layer may be formed of an insulating layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, high-k dielectrics, or a combination thereof.

A polysilicon film may be formed on the dielectric film. In addition, a capping film may be formed on the polysilicon film. A photoresist pattern may be formed on the capping layer. The capping layer 110 may be formed by etching the capping layer using the photoresist pattern as an etching mask. The polysilicon layer 108 may be etched using the capping pattern 110 as an etch mask to form a polysilicon pattern 108. Subsequently, the dielectric layer may be partially etched. Therefore, the dielectric layer may remain only under the polysilicon pattern 108. The dielectric layer remaining under the polysilicon pattern 108 may form a gate dielectric layer 106. The capping pattern 110 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Meanwhile, the formation of the capping pattern 110 may be omitted. That is, the polysilicon pattern 108 may be formed using the photoresist pattern as an etching mask.

Referring to FIG. 3, a spacer layer 120 may be formed on the semiconductor substrate 100. The spacer layer 120 may be formed of an insulating film that is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The spacer layer 120 may be formed of a material having an etch selectivity with respect to the capping pattern 110. For example, when the capping pattern 110 is formed of a silicon nitride layer, the spacer layer 120 may be formed of a silicon oxide layer.

4 and 5, the excess nitrogen region 120N is formed on the surface of the spacer layer 120 by using the DPN method. The DPN method includes a chamber pressure of 10 mtorr to 30 mtorr, a chamber temperature of 0 ° C. to 500 ° C., an RF source power of 100 W to 1000 W, and N 2 , NH 3 , N 2 O, NF 3 , The semiconductor substrate 100 having the spacer layer 120 may be exposed for 5 seconds to 300 seconds under an atmosphere of one gas 130 selected from a group consisting of NO or a combination thereof. The gas 130 may be supplied at a flow rate of 10 sccm to 500 sccm. After performing the DPN method, the semiconductor substrate may be heat treated for 1 to 30 minutes at a temperature of 100 to 800 ° C. in an atmosphere selected from N 2 , Ar, vacuum, or a combination gas of N 2 and Ar. In addition, the excess nitrogen region 120N may be formed along the surface of the spacer layer 120.

Referring to FIG. 6, the spacer layer 120 having the excess nitrogen region 120N may be anisotropically etched to form the gate spacer 120S having the excess nitrogen region 120N. Source / drain regions 140 may be formed in the semiconductor substrate 100 having the gate spacer 120S. The source / drain regions 140 may be formed of the polysilicon pattern using the gate spacer 120S having the device isolation layer 102, the capping pattern 110, and the excess nitrogen region 120N as an ion implantation mask. It may be formed by implanting impurity ions into the semiconductor substrate 100 adjacent to both sides of the (108). The source / drain regions 140 may have an n-type or p-type conductivity, but are formed to have a conductivity type different from that of the semiconductor substrate 100. For example, when the conductivity type of the semiconductor substrate 100 is p type, the conductivity type of the source / drain regions 140 is formed to be n type.

The formation of the excess nitrogen region 120N has an effect that the concentration of nitrogen atoms is relatively higher than the concentration of silicon atoms on the surface of the gate spacer 120S.

Referring to FIG. 7, the capping pattern 110 is removed to expose the top surface of the polysilicon pattern 108. The capping pattern 110 may be removed by selectively etching the semiconductor substrate 100 and the gate spacer 120S having the excess nitrogen region 120N. A metal film 150 may be formed on the semiconductor substrate 100 including the polysilicon pattern 108 and the gate spacer 120S having the excess nitrogen region 120N. The metal film 150 may be a titanium (Ti) film, a cobalt (Co) film, a nickel (Ni) film, or a tungsten (W) film.

In addition, a sacrificial layer (not shown) may be formed on the metal layer 150. The sacrificial layer may be titanium nitride (TiN), and the sacrificial layer may serve to prevent the surface of the metal layer 150 from being exposed and oxidized. Formation of the sacrificial layer may be omitted.

8 and 9, the gate silicide layer 160a and the source / drain may be formed on the polysilicon pattern 108 and the source / drain regions 140 using a heat treatment process on the semiconductor substrate 100. The drain silicide layer 160b may be formed. The polysilicon pattern 108 and the gate silicide layer 160a may form a gate electrode 162.

A method of forming the silicide layers 160a and 160b will be described in detail. A metal film 150 may be formed on the semiconductor substrate 100 including the polysilicon pattern 108 and the gate spacer 120S having the excess nitrogen region 120N (S12). The semiconductor substrate 100 including the metal film 150 may be heat treated. The heat treatment may include a first heat treatment step S14 and a second heat treatment step S16. The first heat treatment step S14 may be performed under a first temperature, and the second heat treatment step S16 may be performed under a second temperature higher than the first temperature. The first heat treatment process S16 may serve to react the metal film 150 with the source / drain regions 140 or the metal film 150 with the polysilicon pattern 108. The silicide layers 160a and 160b are formed by the reaction. The second heat treatment step S18 may serve to lower the resistivity of the silicide layers 160a and 160b.

 Hereinafter, the first heat treatment step S14 and the second heat treatment step S16 will be described in detail with reference to forming titanium silicide layers (TiSi). It may have a C54 phase. The C49 phase may be formed by heat treatment for 30 seconds at a temperature of 650 ℃ to 660 ℃, the C54 phase may be formed by heat treatment for 30 seconds at a temperature of 850 ℃ to 870 ℃. In addition, the C49 phase has a specific resistance of 60 ~ 80 μΩcm, the C54 phase has a specific resistance of 13 ~ 16 μΩcm. That is, the C49 phase titanium silicide may be formed in the first heat treatment step S14, and the C54 phase titanium silicide having lower specific resistance than the titanium silicide in the C49 phase may be formed in the second heat treatment step S16. . Subsequently, the cleaning process S18 may be performed to remove the unreacted metal film from the metal film. The cleaning process (S18) may be performed using a cleaning solution containing sulfuric acid.

Typically, titanium silicide (TiSi) and cobalt silicide (CoSi) may react with silicon atoms such as silicon oxide, silicon nitride, and silicon oxynitride to form parasitic silicides. Therefore, a parasitic silicide layer may be formed in the manufacturing process of a transistor including a general silicide layer to provide a path for leakage current between the gate electrode and the source / drain regions. However, according to the exemplary embodiment of the present invention, the gate spacer 120S having the excess nitrogen region 120N is formed using the DPN method. Since the concentration of nitrogen is excessive on the surface of the gate spacer 120S, silicon atoms may not react with the silicide layers 160a and 160b on the surface of the gate spacer 120S. That is, parasitic silicide cannot be formed. As a result, the source / drain regions 140 and the gate electrode 162 may be electrically separated from each other.

In addition, as shown in FIG. 1, the cleaning process S6 is performed between the first heat treatment step S4 and the second heat treatment step S8 to prevent the parasitic silicide film from being formed. . However, according to the exemplary embodiment of the present invention, since the gate spacer 120S includes the excess nitrogen region 120N on its surface, the parasitic silicide cannot be formed as described above. As a result, as shown in FIG. 9, the second heat treatment step S16 is continuously performed after the first heat treatment step S14, and the cleaning process S18 is performed after the second heat treatment step S16. Can be done. This makes it possible to shorten the process time.

As described above, according to the exemplary embodiment of the present invention, the gate spacer having the excess nitrogen region is formed on the gate sidewall. The gate spacer serves to suppress the formation of the parasitic silicide layer when the silicide layer is formed. In addition, since the cleaning process performed between the first heat treatment process and the second heat treatment process can be omitted, the process time can be shortened.

Claims (9)

Forming a polysilicon pattern on the semiconductor substrate, Forming a gate spacer having an excess nitrogen region on the sidewall of the polysilicon pattern, Source / drain regions are formed in the semiconductor substrate adjacent to both sides of the polysilicon pattern, And forming a silicide film on the polysilicon pattern and the source / drain regions. The method of claim 1, Forming the gate spacers Forming a spacer film on the semiconductor substrate having the polysilicon pattern; The excess nitrogen region is formed in the spacer layer using a decoupled plasma nitridation method, Anisotropically etching the spacer film having the excess nitrogen region. The method of claim 2, The decoupled plasma nitriding (DPN) method Chamber pressure from 10 mtorr to 30 mtorr, chamber temperature from 0 ° C to 500 ° C, RF source power from 100W to 1000W, and N 2 , NH 3 , N 2 O, NF 3 , And exposing the semiconductor substrate with the spacer film for 5 seconds to 300 seconds under one gas atmosphere selected from the group consisting of NO or a combination thereof. The method of claim 3, wherein After performing the decoupled plasma nitridation (DPN) method, the semiconductor substrate is heated to a temperature of 100 to 800 ° C. in one atmosphere selected from the group consisting of N 2 , Ar, vacuum, or a combination gas of N 2 and Ar. The method of manufacturing a transistor further comprising heat treatment for 1 to 30 minutes. The method of claim 2, And the spacer layer is formed of one selected from the group consisting of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a combination film thereof. The method of claim 1, And the excess nitrogen region is formed along the surface of the gate spacer. The method of claim 1, The silicide layer is formed of a cobalt silicide (CoSi) film, a titanium silicide (TiSi) film, and a nickel silicide (NiSi) film. The method of claim 1, Forming the silicide film Forming a metal film on the semiconductor substrate having the polysilicon pattern, the gate spacer and the source / drain regions, Performing a first heat treatment process on the semiconductor substrate under a first temperature; And performing a second heat treatment process on the semiconductor substrate at a second temperature higher than the first temperature. The method of claim 8, And a cleaning process is not performed between the first heat treatment process and the second heat treatment process.
KR1020070047523A 2007-05-16 2007-05-16 Fabrication method of transistor having silicide layer KR20080101158A (en)

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