KR20080097304A

KR20080097304A - Liquid crystal display and method for fabricating the same

Info

Publication number: KR20080097304A
Application number: KR1020070042376A
Authority: KR
Inventors: 정보경; 조기술
Original assignee: 엘지디스플레이 주식회사
Priority date: 2007-05-01
Filing date: 2007-05-01
Publication date: 2008-11-05

Abstract

The present invention relates to a liquid crystal display device having improved conductive foreign material and a method of manufacturing the same. According to the disclosed method, the method includes providing a first substrate having a thin film transistor portion and a pixel portion defined therein, forming a gate electrode on the thin film transistor portion of the first substrate, and forming a gate on the substrate having the gate electrode. Forming a source electrode and a drain electrode through an insulating film; forming a passivation film having a contact hole exposing the drain electrode; a pixel electrode covering the contact hole and the pixel portion on the passivation layer, and a conductive electrode covering the pixel electrode; It comprises a step of sequentially forming a foreign matter prevention pattern.

Description

Liquid crystal display device and manufacturing method therefor {LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME}

1 is a perspective view schematically showing a configuration of a general liquid crystal display device.

2 is a plan view of a general liquid crystal display device.

3 is a cross-sectional view taken along the line II ′ of FIG. 2 to explain a method of manufacturing a general liquid crystal display device.

4A to 4D are cross-sectional views of processes taken along the line II ′ of FIG. 2.

5 is a schematic plan view for explaining a liquid crystal display device according to a first embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along the line II-II ′ of FIG. 5.

7A to 7E are cross-sectional views taken along line II-II ′ of FIG. 5 to explain a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

8 is a schematic plan view for explaining a liquid crystal display device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along line III-III ′ of FIG. 8;

10A to 10E are cross-sectional views taken along line III-III ′ of FIG. 8 to explain a method of manufacturing a liquid crystal display device according to a second exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to prevent conductive foreign substances generated between a pixel electrode of a thin film transistor array substrate and a common electrode of a color filter substrate in a TN mode. The present invention relates to a liquid crystal display device and a method of manufacturing the same.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express an image.

1 is a perspective view schematically illustrating a configuration of a general liquid crystal display device. Hereinafter, the configuration of the above-described liquid crystal display device will be described with reference to FIG. 1.

As shown in FIG. 1, a general liquid crystal display device includes a first substrate 1, which is a thin film transistor array substrate, and a second substrate 71, which is a color filter substrate, spaced apart from each other with a liquid crystal layer interposed therebetween. It is configured to include. In this case, one surface of the second substrate 71 facing the first substrate 1 may include a black matrix 76 and color filters R, G, and B (77a, 77b, 77c: 77) and color. Transparent common electrodes 79 are provided on the filter 77, respectively.

In addition, a plurality of pixel regions P may be defined on one surface of the first substrate 1 facing the second substrate 71, and may include gate lines 2 extending beyond one side of the pixel region P. Each of the data lines 4 extends beyond the other side of the pixel region P through which the gate line 2 passes.

Due to this configuration, the pixel region P corresponds to a region defined by the intersection of the gate line 2 and the data line 4, and at the intersection of the gate line 2 and the data line 4. The thin film transistor T is configured. In addition, a transparent pixel electrode 22P is formed in the pixel region P in contact with the thin film transistor T.

The liquid crystal display device having the above-described configuration has a method of driving the liquid crystal by an electric field applied up and down by the common electrode 79 and the pixel electrode 22, and has excellent characteristics such as transmittance and aperture ratio.

2 is a plan view of a general liquid crystal display device. 3 is a cross-sectional view of the liquid crystal display taken along the line II ′ of FIG. 2. The liquid crystal display device configured as described above will be described in more detail with reference to FIGS. 2 and 3 as follows.

As shown in FIGS. 2 and 3, a general liquid crystal display device includes a gate wiring 2 and a data wiring 4 and a gate wiring formed on the first substrate 1 with the gate insulating film 12 interposed therebetween. (2) and the thin film transistor T formed at the intersection of the data wiring 4, the pixel electrode 22P2, the gate pad 50 connected with the gate wiring 2, and the data wiring 4 and the connection. Configured data pad 60. At this time, the gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region P.

The thin film transistor T keeps the pixel signal of the data line 4 charged and maintained in the pixel electrode 22P2 in response to the gate signal of the gate line 2. To this end, the thin film transistor T includes a gate electrode 6 connected to the gate wiring 2, a source electrode 8 connected to the data wiring 4, and a drain electrode connected to the pixel electrode 22. (10) is provided.

The pixel electrode 22P2 is formed in the pixel region P and is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 20 penetrating through the passivation layer 18. Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor T and the common electrode 79 supplied with the reference voltage. By such an electric field, liquid crystal molecules between the first substrate 1 and the second substrate 71 rotate by dielectric anisotropy.

In addition, the light transmittance through the pixel region P varies according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

On the other hand, the gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate wiring 2. The gate pad 50 has a gate pad lower electrode 52 extending from the gate line 2 and a gate pad lower electrode through the first contact hole 18H1 penetrating through the gate insulating layer 12 and the passivation layer 18. And a gate pad upper electrode 22P1 connected to 52.

In addition, the data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through the data pad lower electrode 62 extending from the data line 4 and the third contact hole 18H3 penetrating through the passivation layer 18. It consists of the data pad upper electrode 22P3.

In addition, the thin film transistor T further includes an active layer 14 forming a channel between the gate insulating layer 12, the source electrode 8, and the drain electrode 10. In this case, the active layer 14 is formed to overlap the data line 4 and the data pad lower electrode 62. An ohmic contact layer 16 for ohmic contact with the source electrode 8, the drain electrode 10, and the data pad lower electrode 62 is further formed on the active layer 14.

Fabrication of the first substrate of the liquid crystal display device configured as described above is performed through a four mask process, and briefly introduced with reference to FIGS. 2 and 4A to 4D as follows.

As shown in FIG. 2 and FIG. 4A, first, a second substrate 1 having a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion defined therein is provided. 4A, the left side corresponds to the gate pad portion, the thin film transistor portion, the pixel portion, and the data pad portion. Subsequently, a gate wiring metal film is formed on the second substrate 1, and the gate wiring metal film is patterned by a photolithography process to form the gate wiring 2. The gate line 2 includes a gate pad lower electrode 52 formed in the gate pad part and a gate electrode 6 formed in the thin film transistor part.

Next, as shown in FIG. 4B, a gate insulating film 12 is formed on the substrate having the gate wiring 2. In this case, the gate insulating layer 12 may use a silicon oxide film or a silicon nitride film. Thereafter, an amorphous silicon film, a silicon film doped with impurities, and a second metal film are sequentially formed on the gate insulating film 12. Next, the data line 4 is formed by selectively patterning the second metal film, the silicon film doped with impurities, and the amorphous silicon film. In this case, the data line 4 includes a source electrode 8 / a drain electrode 10 formed in the thin film transistor unit, and a data pad lower electrode 62 formed in the data pad unit.

In addition, a semiconductor layer 14 is formed between the gate insulating layer 12 and the source electrode 8 / drain electrode 10 and between the gate insulating layer 12 and the data pad lower electrode 62. Here, the semiconductor layer 14 corresponds to an amorphous silicon film remaining after the patterning process for forming the data line. Thus, the source electrode 8 and the drain electrode 10 are patterned to expose the channel region of the semiconductor layer.

Meanwhile, reference numeral 16, which is not described in FIG. 4B, is a silicon film doped with impurities remaining after patterning, and corresponds to an ohmic contact layer.

Thereafter, as shown in FIG. 4C, the passivation layer 18 is formed on the substrate having the data pad lower electrode 62. Thereafter, the passivation layer 18 and the gate insulating layer 12 are patterned to expose the gate pad lower electrode 52, the drain electrode 10, and the data pad lower electrode 62. And fourth contact holes 18H1, 18H2, and 18H3.

Subsequently, as shown in FIG. 4D, a transparent conductive film is formed on the substrate having the first, second, and third contact holes 18H1, 18H2, and 18H3. In this case, the transparent conductive film uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO). Subsequently, each of the gate pad upper electrodes 54, the pixel electrodes 22, and the data covering the first, second, third, and fourth contact holes 18H1, 18H2, and 18H3 by patterning the transparent conductive film. The pad upper electrode 66 is formed.

In the liquid crystal display device according to the related art, a conductive material for forming the thin film transistor T and the pixel electrode 22 is formed while the thin film transistor T or the pixel electrode 22 is formed on the first substrate. They may be deposited on process chamber walls or robotic arms. Therefore, the conductive material on the process chamber wall, the robot arm, or the like remains on the surface of the pixel electrode or the common electrode of the second substrate to act as a conductive foreign material. Accordingly, there is a problem in that the first substrate and the second substrate are shorted by the conductive foreign material.

Accordingly, in order to solve the above problem, an object of the present invention is to form a conductive foreign matter prevention pattern on a pixel electrode, thereby preventing the short circuit of the first substrate and the second substrate by the conductive foreign matter and its It is to provide a manufacturing method.

In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention comprises the steps of providing a first substrate having a thin film transistor portion and a pixel portion, respectively, and forming a gate electrode on the thin film transistor portion of the first substrate Forming a source electrode and a drain electrode on the substrate having the gate electrode; forming a source electrode and a drain electrode; forming a passivation layer having a contact hole exposing the drain electrode; and forming the contact hole and the pixel portion on the passivation layer. And sequentially forming a covering pixel electrode and a conductive foreign material prevention pattern covering the pixel electrode.

The forming of the pixel electrode may include forming a transparent conductive film on the passivation layer, forming a conductive foreign material prevention pattern covering the contact hole and the pixel portion on the transparent conductive film, and using the conductive foreign material prevention pattern as a mask. Etching the conductive film.

In this case, the transparent conductive film uses any one of indium tin oxide (ITO) and indium zinc oxide (IZO).

The conductive foreign matter prevention pattern formation may further include forming a conductive foreign matter prevention film on the transparent conductive film, and patterning the conductive foreign matter prevention film. Here, it is preferable that the said conductive foreign material prevention film is an organic film. The organic layer may be a photo acrylic layer.

The liquid crystal display according to the present invention includes a first substrate having a thin film transistor portion and a pixel portion defined therein, a gate electrode formed on the thin film transistor portion of the first substrate, a gate insulating film formed on a substrate having the gate electrode, and the gate. A protective film having a source electrode and a drain electrode formed on the insulating film, a contact hole formed on the gate insulating film and exposing the drain electrode, a pixel electrode formed on the protective film and covering the contact hole and the pixel portion, and a conductive foreign material. Prevention pattern.

The substrate further includes a second substrate formed to face the first substrate, and a common electrode formed on the second substrate.

Moreover, it is preferable that the said conductive foreign material prevention film is an organic film. The organic layer may be a photo acrylic layer.

(Example)

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a schematic plan view illustrating a liquid crystal display device according to a first embodiment of the present invention. 6 is a cross-sectional view of the thin film transistor array substrate taken along the line II-II ′ of FIG. 5. 7A to 7E are cross-sectional views illustrating processes of manufacturing a thin film transistor array substrate taken along the line II-II ′ of FIG. 5.

Hereinafter, a liquid crystal display device according to a first embodiment of the present invention will be described with reference to the drawings.

5 and 6, the liquid crystal display according to the first exemplary embodiment of the present invention includes a first substrate 101 in which a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion are defined, respectively. A gate wiring 102 formed on the first substrate 101 and provided with a gate electrode 106 formed on the thin film transistor unit, and a gate pad lower electrode 152 formed on the gate pad unit, and the gate A gate insulating film 112 formed on a substrate having a wiring 102, a source electrode 108 and a drain electrode 110 formed on the gate insulating film 112 and formed in the thin film transistor unit, and the data pad unit. A data line 104 each having a data pad lower electrode 162 formed thereon, and a gate pad lower electrode 152, a drain electrode 110, and a data pad lower portion formed on a substrate having the data line 104. electrode( A passivation layer 118 having respective first, second, and third contact holes 118H1, 118H2, 118H3 exposing 162, and formed on the passivation layer 118 and formed on the first, second, and third contact holes 118H3. A gate pad upper electrode 122P1 and a data pad upper electrode 122P3 covering the three contact holes 118H1 and 118H3, and a pixel electrode 122P2 covering the second contact hole 118H2 and the pixel portion; The conductive foreign material prevention pattern 141P covering the pixel electrode 122P2 is formed.

In this case, a semiconductor layer 114 is interposed between the gate insulating layer 112, the source electrode 108, and the drain electrode 110. In this case, the source electrode 108 and the drain electrode 110 are patterned to expose the channel region of the semiconductor layer 114.

In addition, the gate pad upper electrode 122P1, the pixel electrode 122P2, and the data pad upper electrode 122P3 may be patterned with the same layer. In detail, the gate pad upper electrode 122P1, the pixel electrode 122P2, and the data pad upper electrode 122P3 may be formed of a transparent conductive film. The transparent conductive film may be any one of indium tin oxide (ITO) and indium zinc oxide (IZO).

In addition, the conductive foreign matter prevention pattern 141P may be formed of an organic layer. Here, a photo acryl film is used as said organic film.

Meanwhile, the liquid crystal display device according to the first embodiment of the present invention described above includes a second substrate 171 formed to face the first substrate 101, and a common electrode 179 formed on the second substrate 171. It may further include.

Hereinafter, a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention having the above-described configuration will be described.

As shown in FIGS. 5 and 7A, a first substrate 1 in which a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion are defined, respectively, is provided. Subsequently, a gate wiring metal film is formed on the first substrate 1, and then the gate wiring metal film is patterned to form a gate wiring 102. In this case, the gate wiring 102 includes a gate pad lower electrode 152 formed in the gate pad part and a gate electrode 106 formed in the thin film transistor part.

Next, as shown in FIGS. 5 and 7B, a gate insulating layer 112 is formed on the substrate having the gate wiring 102. In this case, the gate insulating film 112 may use a silicon oxide film or a silicon nitride film. Thereafter, an amorphous silicon film, a silicon film doped with impurities, and a metal film for data wiring are sequentially formed on the gate insulating film 112. Subsequently, the ohmic contact layer 116, the semiconductor layer 114, and the data line 104 are formed by selectively patterning the metal layer for data wiring, the silicon layer doped with impurities, and the amorphous silicon layer. In this case, the data line 104 includes a source electrode 108 and a drain electrode 110 formed in the thin film transistor unit, and a data pad lower electrode 162 formed in the data pad unit. The source electrode 108 and the drain electrode 110 are patterned to expose the channel region of the semiconductor layer 14.

In addition, the ohmic contact layer 116 and the semiconductor layer 114 are formed in the thin film transistor unit and the data pad unit, respectively.

Meanwhile, the channel region of the semiconductor layer 114 may be damaged in the process of etching the metal layer for data wiring. Accordingly, in order to recover damage of the channel region of the semiconductor layer 114, the channel protection layer 121 is formed by supplying O 2 plasma to the channel region of the semiconductor layer 114. In this case, the channel passivation layer 121 may be formed by supplying N 2 plasma instead of the O 2 plasma. Here, the process of forming the channel protective layer 121 may be selectively performed.

Thereafter, as shown in FIG. 7C, the passivation layer 118 is formed on the substrate having the channel passivation layer 121. Subsequently, the passivation layer 118 and the gate insulating layer 112 are patterned to expose the gate pad lower electrode 152, the drain electrode 110, and the data pad lower electrode 162, respectively. Three contact holes 118H1, 118H2, and 118H3 are formed.

Subsequently, as shown in FIGS. 5 and 7D, the transparent conductive film 121 is formed on the substrate having the first, second, and third contact holes 18H1, 18H2, and 18H3. In this case, the transparent conductive film may be any one of indium tin oxide (ITO) and indium zinc oxide (IZO). Next, a conductive foreign matter prevention film is formed on the substrate having the transparent conductive film 121. The conductive foreign matter prevention film may be an organic film. In this case, the organic film may be a polyacrylic film.

Subsequently, the conductive foreign material prevention layer is patterned to form a conductive foreign material prevention preliminary pattern 141 covering the pixel portion including the gate pad part, the data pad part, and the second contact hole 118H2. In this case, the conductive foreign material prevention preliminary pattern 141 may be formed so that the thickness of the gate pad portion and the data pad portion is relatively thinner than the pixel portion including the second contact hole 118H2. Here, the conductive foreign material prevention preliminary pattern 141 may be formed by selective exposure using a halftone technique.

Next, as illustrated in FIG. 7E, the transparent conductive layer is etched using the conductive foreign material prevention preliminary pattern as a mask to form a pixel electrode 122P2 covering the second contact hole 118H2 and the pixel portion. In this case, the transparent conductive film etching process is a wet etching. The gate pad upper electrode 122P1 and the data pad upper electrode 122P3 are formed to cover the first contact hole 118H1 and the third contact hole 118H3 at the same time as the pixel electrode 122P2 is formed.

Thereafter, the conductive foreign material prevention preliminary pattern is ashed to form a conductive foreign material prevention pattern 141P covering the pixel electrode 122P2. At this time, the ashing process proceeds until the conductive foreign material prevention preliminary patterns formed on the data pad portion and the gate pad portion are completely removed. Subsequently, although not shown in the drawing, after the ashing process is completed, a curing process may be performed on the substrate having the conductive foreign matter prevention pattern 141P.

As described above, in the first embodiment according to the present invention, by adopting the structure in which the pixel electrode is covered by the conductive foreign matter prevention pattern, the conductive foreign matter is prevented from adhering to the pixel electrode surface. Therefore, a short phenomenon between the first substrate and the second substrate due to the adhesion of the conductive foreign material is prevented.

8 is a schematic plan view illustrating a liquid crystal display device according to a second exemplary embodiment of the present invention. 9 is a cross-sectional view taken along line III-III ′ of FIG. 8. 10A through 10E are cross-sectional views taken along line III-III ′ of FIG. 8 to explain a method of manufacturing a liquid crystal display device according to a second exemplary embodiment of the present invention.

Hereinafter, a liquid crystal display device according to a second embodiment of the present invention will be described with reference to the drawings.

8 and 9, the liquid crystal display according to the second exemplary embodiment of the present invention includes a first substrate 201 in which a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion are defined, respectively. A gate wiring 202 formed on the first substrate 201 and including a gate electrode 206 formed on the thin film transistor unit, and a gate pad lower electrode 252 formed on the gate pad unit; A source electrode 208 and a drain electrode 210 formed on the substrate having the substrate 202 and exposed to the channel region, and a data pad lower electrode 262 formed on the data pad portion. A gate insulating film 212 having a data wiring 204, a contact hole 212H interposed between the gate wiring 202 and the data wiring 204 and exposing the gate pad lower electrode 252, and Contact hole A gate pad upper electrode 227P1 covering 212H, a pixel electrode 227P2 covering at least a portion of the drain electrode and the pixel portion, a data pad upper electrode 227P3 covering the data pad portion, and the pixel electrode 227P2 It is comprised including the conductive foreign matter prevention pattern 241P.

The semiconductor device may further include a semiconductor layer 214 interposed between the gate insulating layer 212, the source electrode 208, and the drain electrode 210. In this case, the source electrode 208 and the drain electrode 210 are patterned to expose the channel region of the semiconductor layer 214.

The semiconductor device may further include a channel passivation layer 221 formed in the channel region of the semiconductor layer 214, and the channel passivation layer 221 may be either silicon oxide or silicon nitride.

In addition, the conductive foreign material prevention pattern 261P may be formed of an organic film. Here, a photo acryl film is used as said organic film.

The gate pad upper electrode 227P1, the pixel electrode 227P2, and the data pad upper electrode 227P3 may be patterned with the same film. In detail, the gate pad upper electrode 227P1, the pixel electrode 227P2, and the data pad upper electrode 227P3 may be formed of a transparent conductive film.

Meanwhile, the liquid crystal display device according to the second embodiment of the present invention described above includes a second substrate 271 formed to face the first substrate 201 and a common electrode 279 formed on the second substrate 271. It may further include.

Hereinafter, a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention described above with reference to the drawings.

8 and 10A, a first substrate 201 in which a thin film transistor unit, a pixel unit, a gate pad unit, and a data pad unit are defined, respectively, is provided. Subsequently, a gate wiring metal film is formed on the first substrate 201, and the gate wiring metal film is patterned to form a gate wiring 202. In this case, the gate line 202 includes a gate electrode 206 formed in the thin film transistor unit and a gate pad 252 formed in the gate pad unit.

Next, as shown in FIGS. 8 and 10B, a gate insulating film 212 is formed on the first substrate having the gate wiring 202. In this case, the gate insulating film 212 may use a silicon oxide film or a silicon nitride film. Thereafter, an amorphous silicon film, a silicon film doped with impurities, and a metal film for data wiring are sequentially formed on the gate insulating film 212. Subsequently, the ohmic contact layer 216, the semiconductor layer 214, and the data wiring 204 are selectively formed by patterning the metal film for data wiring, the silicon film doped with impurities, and the amorphous silicon film several times. In this case, the data line 204 includes a source electrode 208 and a drain electrode 210 formed in the thin film transistor unit, and a data pad lower electrode 262 formed in the data pad unit. The source electrode 208 and the drain electrode 210 are patterned to expose the channel region of the semiconductor layer 214.

In addition, the semiconductor layer 214 may be formed between the gate insulating layer 212 and the source electrode 208 / drain electrode 210 in the thin film transistor unit and the gate insulating layer 212 and the data pad lower electrode in the data pad unit. 262 is formed between. The semiconductor layer 214 corresponds to an amorphous silicon film remaining after the patterning process for forming the data line.

The ohmic contact layer 216 is disposed between the semiconductor layer 214 and the source electrode 208 / drain electrode 210 in the thin film transistor unit, and the semiconductor layer 214 and the data pad lower electrode 262 in the data pad unit. It is formed between. In addition, the ohmic contact layer 216 corresponds to an amorphous silicon film remaining after patterning for forming the data line.

Meanwhile, the channel region of the semiconductor layer 214 may be damaged in the process of etching the data line metal film or in the subsequent pixel electrode patterning process. Therefore, in order to recover damage of the channel region of the semiconductor layer, an O 2 plasma treatment process 251 is selectively performed on the channel region of the semiconductor layer 214 exposed by the source electrode 208 and the drain electrode 210. Proceeding to form a channel protective film 221 which is a silicon oxide film. In this case, the channel passivation layer 221 may be formed by supplying N2 plasma instead of the O2 plasma.

Subsequently, as shown in FIG. 10D, a transparent conductive film 227 is formed on the substrate having the channel protective film 221. Next, a conductive foreign matter prevention film is formed on the substrate having the transparent conductive film 227. In this case, the transparent conductive layer 227 may be any one of indium tin oxide (ITO) and indium zinc oxide (IZO). In addition, the conductive foreign matter prevention film may be an organic film. In this case, the organic film may be a polyacryl film.

Subsequently, the conductive foreign material prevention film is patterned to form a conductive foreign material prevention preliminary pattern 241 covering the pixel part including the gate pad part, the data pad part, and the drain electrode 210. In this case, the conductive foreign material prevention preliminary pattern 241 may be formed so that the thickness of the gate pad portion and the data pad portion is relatively thinner than the pixel portion including the drain electrode 210. Here, the conductive foreign material prevention preliminary pattern 241 may be formed by selective exposure using a halftone technique.

Next, as illustrated in FIG. 10E, the transparent conductive film is etched using the conductive foreign material prevention preliminary pattern as a mask to form a pixel electrode 227P2 covering the pixel portion including the drain electrode 210. In this case, the transparent conductive film etching process is a wet etching.

The gate pad upper electrode 227P1 covering the contact hole 212H1 of the gate pad portion and the data pad upper electrode 222P3 covering the data pad portion are formed at the same time as the pixel electrode 227P2 is formed.

Thereafter, the conductive foreign material prevention preliminary pattern is ashed to form a conductive foreign material prevention pattern 241P covering the pixel electrode 227P2. At this time, the ashing process proceeds until the conductive foreign material prevention preliminary patterns formed on the data pad portion and the gate pad portion are completely removed.

As described above, in the second embodiment of the present invention, by forming the conductive foreign matter prevention pattern covering the pixel electrode, the conductive foreign matter is prevented from adhering to the surface of the pixel electrode. Therefore, the short problem between the first substrate and the second substrate due to the attachment of the conductive foreign material is solved. In addition, since the protective film formation can be omitted, the process is simplified.

According to the present invention, a conductive foreign matter prevention pattern covering the pixel electrode is provided. Accordingly, conductive foreign matter is prevented from adhering to the pixel electrode surface. Accordingly, there is an advantage that the short phenomenon between the first substrate and the second substrate due to the adhesion of the conductive foreign material is prevented.

Claims

Providing a substrate having a thin film transistor portion and a pixel portion defined therein,

Forming a gate electrode on the thin film transistor portion of the substrate;

Forming a source electrode and a drain electrode by interposing a gate insulating film on a substrate having the gate electrode;

Forming a protective film having a contact hole exposing the drain electrode;

And sequentially forming a pixel electrode covering the contact hole and the pixel portion and a conductive foreign material prevention pattern covering the pixel electrode on the passivation layer.

The method of claim 1, wherein forming the pixel electrode

Forming a transparent conductive film on the protective film;

Forming a conductive foreign material prevention pattern covering the contact hole and the pixel portion on the transparent conductive film;

And etching the transparent conductive film using the conductive foreign material prevention pattern as a mask.

The method of claim 2, wherein the transparent conductive film is one of indium tin oxide (ITO) and indium zinc oxide (IZO).

The method of claim 3, wherein the conductive foreign material prevention pattern formation

Forming a conductive foreign material prevention film on the transparent conductive film;

The method of manufacturing a liquid crystal display device further comprising the step of patterning the conductive foreign material prevention film.

The method for manufacturing a liquid crystal display device according to claim 4, wherein the conductive foreign material prevention film is an organic film.

The method of manufacturing a liquid crystal display device according to claim 5, wherein the organic film is a photo acrylic film.

The method of claim 3, wherein the transparent conductive film etching process is performed by wet etching.

Providing a substrate on which a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion are defined, respectively;

Forming a gate wiring on the substrate, the gate wiring including a gate electrode formed on the thin film transistor and a gate pad lower electrode formed on the gate pad;

Forming a gate insulating film on the substrate having the gate wiring;

Forming a data line on the gate insulating layer, the data line having a source electrode and a drain electrode formed on the thin film transistor to expose a channel region, and a lower data pad electrode formed on the data pad part, respectively; Wow,

Forming a protective film having first, second, and third contact holes exposing the gate pad lower electrode, the drain electrode, and the data pad lower electrode on the substrate having the data line, respectively;

Forming a pixel electrode covering the second contact hole and the pixel portion at the same time as forming the gate pad upper electrode and the data pad upper electrode covering the first and third contact holes on the passivation layer;

Forming a conductive foreign material prevention pattern covering the pixel electrode.

The method of claim 8, wherein the forming of the pixel electrode

Forming a transparent conductive film on the protective film;

A conductive foreign matter prevention preliminary pattern is formed on the transparent conductive layer to cover the pixel portion including the first and third contact holes and the second contact hole, and the conductive foreign matter prevention preliminary pattern has a relative thickness of the gate pad part and the data pad part. Thinly formed into,

And etching the transparent conductive film using the conductive foreign material prevention preliminary pattern as a mask.

The method of claim 9, further comprising ashing the conductive foreign material prevention preliminary pattern to form a conductive foreign material prevention pattern covering the pixel electrode.

The method of claim 9, wherein the conductive foreign material prevention preliminary pattern formation is

12. The method of claim 11, wherein the conductive foreign matter prevention film is an organic film.

The method of claim 12, wherein the organic film is a photo acrylic film.

Forming a gate electrode on the thin film transistor of the substrate;

Forming a gate insulating film on the substrate having the gate electrode;

Forming a source electrode and a drain electrode exposing the semiconductor layer and the channel region of the semiconductor layer sequentially stacked on the gate insulating film;

And sequentially forming the drain electrode, the pixel electrode covering the pixel portion, and the conductive foreign material prevention pattern covering the pixel electrode.

15. The method of claim 14, wherein forming the pixel electrode

Forming a transparent conductive film on the protective film;

Forming a conductive foreign material prevention pattern covering the drain electrode and the pixel portion on the transparent conductive film;

The method of claim 15, wherein the transparent conductive film is any one of indium tin oxide (ITO) and indium zinc oxide (IZO).

The method of claim 15, wherein the conductive foreign material prevention pattern formation

18. The method of claim 17, wherein the conductive foreign material prevention film is an organic film.

19. The method of claim 18, wherein the organic film is a photo acrylic film.

The method of claim 15, wherein the transparent conductive film etching process is performed by wet etching.

15. The method of claim 14, further comprising forming a source electrode and a drain electrode,

And forming a channel passivation layer covering the channel region of the semiconductor layer.

The method of claim 21, wherein the channel protective film

And selectively O 2 plasma treatment in the channel region of the semiconductor layer.

Forming a gate wiring on the substrate, the gate wiring including a gate electrode formed on the thin film transistor, and a gate pad lower electrode formed on the gate pad;

Forming a gate insulating film on the substrate having the gate wiring;

Forming a data line on the gate insulating layer, wherein the data line includes a source electrode / drain electrode formed on the thin film transistor to expose a channel region, and a lower data pad electrode formed on the data pad; ,

Patterning the gate insulating layer to form a contact hole exposing the gate pad lower electrode;

Forming a pixel pad upper electrode covering the contact hole and a data pad upper electrode covering the gate insulating film of the data pad part, and simultaneously forming at least a portion of the drain electrode and a pixel electrode covering the pixel part;

The method of claim 23, wherein forming the pixel electrode

Forming a transparent conductive film on the protective film;

A conductive foreign material preliminary pattern is formed on the transparent conductive layer to cover the contact hole, the data pad part, and at least a portion of the drain electrode and the pixel part. The conductive foreign material preliminary pattern may have a relatively thick thickness between the gate pad part and the data pad part. Thinly formed into,

25. The method of claim 24, further comprising forming a conductive foreign material prevention pattern covering the pixel electrode by ashing the conductive foreign material prevention preliminary pattern.

The method of claim 24, wherein the conductive foreign material prevention preliminary pattern formation is

27. The method of claim 26, wherein the conductive foreign material prevention film is an organic film.

28. The method of claim 27, wherein the organic film is a photo acrylic film.

24. The method of claim 23, further comprising forming a semiconductor layer interposed between the gate insulating film, the source electrode, and the drain electrode.

30. The method of claim 29, wherein the source electrode and the drain electrode are formed to selectively expose the surface of the semiconductor layer.

31. The method of claim 30, wherein the source electrode and the drain electrode are formed to expose the channel region of the semiconductor layer.

The method of claim 31, wherein after forming the contact hole,

And forming a channel passivation layer in the channel region of the semiconductor layer.

The method of claim 32, wherein the channel protective film

A first substrate having a thin film transistor portion and a pixel portion defined therein;

A gate electrode formed on the thin film transistor of the first substrate;

A gate insulating film formed on a substrate having the gate electrode;

A source electrode and a drain electrode formed on the gate insulating film;

A protective film formed on the gate insulating film and having a contact hole exposing the drain electrode;

And a pixel electrode formed over the passivation layer, the pixel electrode covering the contact hole and the pixel portion, and a conductive foreign material prevention pattern.

The method of claim 34,

A second substrate formed to face the first substrate;

The liquid crystal display device further comprising a common electrode formed on the second substrate.

The liquid crystal display device according to claim 34, wherein the conductive foreign material prevention pattern is an organic film.

The liquid crystal display device according to claim 36, wherein the organic film is a photo acrylic film.

A substrate on which a gate pad portion, a thin film transistor portion, a pixel portion, and a data pad portion are defined,

A gate wiring formed on the substrate and having a gate electrode formed on the thin film transistor, and a gate pad lower electrode formed on the gate pad;

A gate insulating film formed on the substrate having the gate wiring;

A data line formed on the gate insulating layer, the data line including a source electrode and a drain electrode formed on the thin film transistor unit, and a lower data pad electrode formed on the data pad unit;

A protective film formed on a substrate having the data wirings, the protective film having first, second, and third contact holes respectively exposing the gate pad lower electrode, the drain electrode, and the data pad lower electrode;

A gate pad upper electrode and a data pad upper electrode formed on the passivation layer and covering the first and third contact holes, and a pixel electrode covering the second contact hole and the pixel portion;

A liquid crystal display device including a conductive foreign material prevention pattern covering the pixel electrode.

39. The liquid crystal display device of claim 38, further comprising a semiconductor layer interposed between the gate insulating film, the source electrode, and the drain electrode.

The liquid crystal display device according to claim 38, wherein the conductive foreign material prevention pattern is an organic film.

41. The liquid crystal display device according to claim 40, wherein the organic film is a photo acrylic film.

A first substrate having a thin film transistor portion and a pixel portion defined therein,

A gate insulating film formed on the first substrate having the gate electrode;

A source electrode and a drain electrode exposing the semiconductor layer and the channel region of the semiconductor layer sequentially stacked on the gate insulating film;

And a pixel electrode covering the drain electrode, the pixel portion, and a conductive foreign material prevention pattern covering the pixel electrode.

The method of claim 42, wherein

A second substrate formed to face the first substrate;

43. The liquid crystal display device according to claim 42, wherein the conductive foreign material prevention pattern is an organic film.

45. The liquid crystal display device according to claim 44, wherein the organic film is a photo acrylic film.

43. The liquid crystal display device of claim 42, further comprising a channel passivation layer formed in the channel region of the semiconductor layer.

47. The liquid crystal display device according to claim 46, wherein the channel protective film is a silicon oxide film.

A data line formed on a substrate having the gate wiring, the data line including a source electrode and a drain electrode formed on the thin film transistor to expose a channel region, and a lower data pad electrode formed on the data pad;

A gate insulating layer interposed between the gate line and the data line and having a contact hole exposing the gate pad lower electrode;

A gate pad upper electrode covering the contact hole and a data pad upper electrode covering the gate insulating film of the data pad part, and at least a portion of the drain electrode and a pixel electrode covering the pixel part;

49. The liquid crystal display device of claim 48, further comprising a semiconductor layer interposed between the gate insulating film, the source electrode, and the drain electrode.

50. The liquid crystal display device according to claim 49, wherein the source electrode and the drain electrode selectively expose the surface of the semiconductor layer.

51. The liquid crystal display device of claim 50, wherein the source electrode and the drain electrode expose a channel region of the semiconductor layer.

52. The liquid crystal display device of claim 51, further comprising a channel passivation layer formed in the channel region of the semiconductor layer.

53. The liquid crystal display device according to claim 52, wherein the channel protective film is a silicon oxide film.

55. The liquid crystal display device according to claim 54, wherein the organic film is a photo acrylic film.