KR20080095608A - Overlay vernier of semiconductor device and method for forming the same - Google Patents

Overlay vernier of semiconductor device and method for forming the same Download PDF

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Publication number
KR20080095608A
KR20080095608A KR1020070040334A KR20070040334A KR20080095608A KR 20080095608 A KR20080095608 A KR 20080095608A KR 1020070040334 A KR1020070040334 A KR 1020070040334A KR 20070040334 A KR20070040334 A KR 20070040334A KR 20080095608 A KR20080095608 A KR 20080095608A
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KR
South Korea
Prior art keywords
vernier
parent
mother
forming
overlay
Prior art date
Application number
KR1020070040334A
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Korean (ko)
Inventor
엄재두
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070040334A priority Critical patent/KR20080095608A/en
Publication of KR20080095608A publication Critical patent/KR20080095608A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

An overlay vernier of a semiconductor device and a method for forming the same are provided to measure an over layer and a son vernier on the upper layer by superposing a first mother vernier and a second mother vernier and to align them. An overlay vernier of a semiconductor device comprises a first mother vernier(110) of rectangular shape on a semiconductor substrate(100); a second mother vernier(120) of concave type having a step at each side of the rectangular first mother vernier; a son vernier(130) formed at the center portion of the semiconductor substrate.

Description

Overlay vernier of semiconductor device and method for forming the same

1 is a plan view of an overlay vernier according to the prior art.

2A to 2B are a plan view and a cross-sectional view of an overlay vernier according to an embodiment of the present invention.

3A and 3B are a plan view and a cross-sectional view of an overlay vernier according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 110 first parent vernier

120: second vernier 130: purple vernier

The present invention relates to an overlay vernier of a semiconductor device and a method of forming the same. The present invention relates to an overlay vernier of a semiconductor device and a method of forming the same, which can measure and compensate for an overlapping degree regardless of the number and direction of lower layers.

The semiconductor device undergoes a complicated process in which a plurality of exposure masks are overlapped and used, and alignment between the exposure masks used step by step is performed based on a mark of a specific shape.

The mark is called an alignment key or alignment mark, and is used for alignment between different masks or between dies for one mask.

A stepper, which is a step and repeat type exposure apparatus used in a semiconductor device manufacturing process, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned automatically or manually on the basis of the alignment mark, the stage is mechanically terminated, so that the alignment error occurs during the repeated process, if the alignment error exceeds the allowable range of the device failure occurs.

As described above, the adjustment range of the overlapping accuracy according to the misalignment is about 0 to 30% of the design rule, according to the design rule of the device. In addition, an overlay accuracy measurement mark for confirming that the alignment between the layers formed on the semiconductor substrate is correctly used is also used in the same manner as the alignment mark.

Conventional alignment marks and overlapping precision measurement marks are formed on a scribe line which is a portion where a chip is not formed in a semiconductor wafer, and as a measuring method of misalignment using the alignment marks, a veneer alignment mark is used. Visual inspection using the box and automatic check using a box in box or box in bar or bar in bar or box and bar alignment mark Measured by the method, then compensated.

As semiconductor devices are highly integrated, densities of patterns formed on wafers are becoming more dense. In particular, in memory devices, the pattern density of the cell region is very high compared to the peripheral region. Meanwhile, devices formed in the cell region or the peripheral region are manufactured by repeatedly performing a thin film deposition process and a thin film patterning process.

1 is a plan view of an overlay vernier according to the prior art.

Referring to FIG. 1, the overlay vernier includes a parent vernier 10 and a child vernier 20. By measuring the distance between the parent vernier 10 and the child vernier 20, the degree of overlay between the thin film already formed on the wafer in the previous step and the thin film to be formed in the current step is measured. Such overlay vernier is formed in the scribe area of the wafer.

The overlay vernier according to the related art described above measures the overlay in the Y-axis direction by using the distances a and b of the parent vernier 10 and the child vernier 20 in one direction with respect to one lower layer. The overlay in the X-axis direction is measured using the distances c and d of the parent vernier 10 and the child vernier 20 in different directions.

However, when there are two or more lower layers, the first lower layer measures only the overlay in the Y-axis direction using the distances a and b of the parent vernier 10 and the child vernier 20 in one direction, and the second lower layer. Is only measuring the overlay in the X-axis direction using the distance (c, d) of the parent vernier 10 and the child vernier 20 in the vertical direction.

Because of this, when aligning a plurality of lower layers at the same time, the accuracy is low by aligning only the overlay in one direction.

The technical problem to be achieved by the present invention is to form a first vernier for measuring the overlay overlapping degree of the first lower layer, the second vernier for measuring the overlay overlapping degree of the first lower layer first vernier The overlay vernier of the semiconductor device capable of measuring and aligning the overlay of the first vernier and the second vernier and the vernier formed in the upper layer by etching the interruption portion of the first vernier and forming the overlayer To provide a way.

The overlay vernier of the semiconductor device according to the first exemplary embodiment of the present invention may include a first parent vernier having a rectangular structure formed on a semiconductor substrate, a second parent vernier having a stepped recess in each rectangular side of the first parent vernier, And a ruler vernier formed at a central portion on the semiconductor substrate surrounded by the first mother vernier.

Each of the four sides of the first mother vernier is formed in two parallel bar types, and the space between the two parallel bars is the concave second mother vernier.

The overlay vernier of the semiconductor device according to the second embodiment of the present invention includes a first parent vernier having a rectangular structure formed on a semiconductor substrate, and a second parent vernier formed convexly and convexly on each rectangular side of the first parent vernier. And a ruler vernier formed at a central portion on the semiconductor substrate surrounded by the first mother vernier.

In the method for forming an overlay vernier of a semiconductor device according to the first embodiment of the present invention, the method may further include forming a first parent vernier having a rectangular structure on a semiconductor substrate, and etching an interruption portion of each side of the first parent vernier having the rectangular structure. Forming a mother vernier, and forming a child vernier pattern on the semiconductor substrate surrounded by the first mother vernier.

In the forming of the second parent vernier, the middle portion of each side of the first parent vernier is etched to form the first parent vernier having two parallel bar types on each side, and the space between the two parallel bar types. Forming the second mother vernier, and the step of forming the first mother vernier, the width of the rectangular one side is formed three times the width of the second mother vernier.

In the method of forming an overlay vernier of a semiconductor device according to the second embodiment of the present invention, forming a first parent vernier having a rectangular structure on a semiconductor substrate, and forming a first parent vernier on each side of the first parent vernier of the rectangular structure. Forming a mother vernier, and forming a child vernier pattern on the semiconductor substrate surrounded by the first mother vernier.

The forming of the second parent vernier forms the second parent vernier protruding on each side of the first parent vernier, wherein the width of each side of the first parent vernier is three times the width of each of the second parent vernier sides. to be.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A to 3B are a plan view and a cross-sectional view of an overlay vernier according to an embodiment of the present invention.

2A and 2B, a first parent vernier pattern 110 is formed on the semiconductor substrate 100 to measure the degree of overlap between the upper layer and the first lower layer. The first mother vernier pattern 110 may be formed in a rectangular structure, and may be formed by applying a photoresist material on the semiconductor substrate 100 and then performing exposure and development processes. The width of one side of the first mother vernier pattern 110 may be formed in consideration of the size of the second mother vernier pattern that is subsequently formed. Preferably, when the number of overlapping lower layer layers is N, it is preferable to form a width that is 2N-1 times the width of one side of the parent vernier pattern formed last. For example, when the two lower layers overlap, the width of one side of the first first vernier pattern 110 is preferably formed to be three times wider than the width of the subsequent second vernier pattern.

In this case, since the first parent vernier pattern 110 is formed in a rectangular structure, the degree of overlap between the X and Y axes may be measured when the degree of overlap between the first lower layer and the upper layer is measured.

3A and 3B, the middle portion of the first parent vernier pattern 110 is etched to form a second parent vernier pattern 110 in order to measure the degree of overlap between the upper layer and the second lower layer. That is, the middle portion of each side of the first parent vernier pattern 110 having a rectangular structure is etched to etch each side of the first parent vernier pattern 110 into two horizontal patterns. As a result, the second mother vernier pattern 120 is formed with a step difference from the first mother vernier pattern 110. That is, each side of the first parent vernier pattern 110 is formed in two parallel bar types, and the space between the two parallel bars is the second parent vernier pattern 120.

Thereafter, the ruler vernier 130 for measuring the degree of overlap with the upper layer is formed.

After that, when the degree of overlap between the upper layer and the first and second lower layers is measured by a measuring device, the signals of the first and second lower layers are separated by two first parent vernier patterns 110. By detecting it as a signal and converting it into a signal with an average value, we can measure the overlap between two lower layers simultaneously. The distance deviation from the signal of the upper layer is calculated and used as the overlap correction value to compensate for the overlap.

4A to 4B are a plan view and a cross-sectional view of an overlay vernier according to another example of the present invention.

Referring to FIGS. 4A and 4B, the second parent vernier pattern 120 is measured on the first parent vernier pattern 110 formed as shown in FIGS. 2A and 2B to measure the degree of overlap between the upper layer and the second lower layer. Form. That is, the second mother vernier pattern 120 having a structure protruding from the edge portion of each side of the first mother vernier pattern 110 having a rectangular structure is formed. As a result, the second mother vernier pattern 120 is formed to protrude with the stepped portion of the first mother vernier pattern 110.

Thereafter, the ruler vernier 130 for measuring the degree of overlap with the upper layer is formed.

Thereafter, when the degree of overlap between the upper layer and the first and second lower layers is measured by a measuring device, the signals of the first and second lower layers may be transmitted to the first parent vernier pattern 110 and the second vernier pattern protruding. When the signal is detected by the signal 120 and converted into a signal having an average value, the degree of overlap between the two lower layers may be simultaneously measured. The distance deviation from the signal of the upper layer is calculated and used as the overlap correction value to compensate for the overlap.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, after forming a first vernier for measuring the overlay overlapping degree of the first lower layer, the second mother vernier for measuring the overlay overlapping degree of the first lower layer is the first model. By etching the interruption portion of the vernier or forming the first vernier, the overlay of the vernier formed on the upper layer by overlapping the first and second vernier can be measured and aligned.

Claims (9)

A first parent vernier having a rectangular structure formed on the semiconductor substrate; A second parent vernier having a stepped concave in each rectangular side of the first parent vernier; And An overlay vernier of the semiconductor device comprising a ruler vernier formed in the center portion on the semiconductor substrate surrounded by the first mother vernier. The method of claim 1, Each of the four sides of the first mother vernier is an overlay vernier of the semiconductor device formed in two parallel bar type. The method of claim 2, The space between the two parallel bars (Bar) is the overlay vernier of the semiconductor device is the concave second parent vernier. A first parent vernier having a rectangular structure formed on the semiconductor substrate; A second parent vernier having a step and convex formed on each rectangular side of the first parent vernier; And An overlay vernier of the semiconductor device comprising a ruler vernier formed in the center portion on the semiconductor substrate surrounded by the first mother vernier. Forming a first parent vernier having a rectangular structure on the semiconductor substrate; Etching a stop portion of each side of the first mother vernier of the rectangular structure to form a second mother vernier; And Forming a vernier pattern on the semiconductor substrate surrounded by the first mother vernier. The method of claim 5, wherein In the forming of the second parent vernier, the middle portion of each side of the first parent vernier is etched to form the first parent vernier having two parallel bar types on each side, and the space between the two parallel bar types. Overlay vernier forming method of a semiconductor device to form the second mother vernier. The method of claim 5, wherein The forming of the first parent vernier is a method of forming an overlay vernier of a semiconductor device, wherein the width of the rectangular one side is formed to be three times the width of the second parent vernier. Forming a first parent vernier having a rectangular structure on the semiconductor substrate; Forming a second parent vernier on the stop of each side of the first parent vernier of the rectangular structure; And Forming a vernier pattern on the semiconductor substrate surrounded by the first mother vernier. The method of claim 8, The forming of the second mother vernier may include forming the second mother vernier protruding on each side of the first mother vernier, wherein the width of each side of the first mother vernier is three times the width of each side of the second mother vernier. Method of forming overlay vernier of semiconductor device.
KR1020070040334A 2007-04-25 2007-04-25 Overlay vernier of semiconductor device and method for forming the same KR20080095608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070040334A KR20080095608A (en) 2007-04-25 2007-04-25 Overlay vernier of semiconductor device and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070040334A KR20080095608A (en) 2007-04-25 2007-04-25 Overlay vernier of semiconductor device and method for forming the same

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KR20080095608A true KR20080095608A (en) 2008-10-29

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