KR20080088103A - Attaching apparatus - Google Patents

Attaching apparatus Download PDF

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Publication number
KR20080088103A
KR20080088103A KR1020070030524A KR20070030524A KR20080088103A KR 20080088103 A KR20080088103 A KR 20080088103A KR 1020070030524 A KR1020070030524 A KR 1020070030524A KR 20070030524 A KR20070030524 A KR 20070030524A KR 20080088103 A KR20080088103 A KR 20080088103A
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South Korea
Prior art keywords
semiconductor chip
collet
spacer
void
insulating member
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KR1020070030524A
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Korean (ko)
Inventor
조범상
김진용
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070030524A priority Critical patent/KR20080088103A/en
Publication of KR20080088103A publication Critical patent/KR20080088103A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface
    • H01L2224/75305—Shape of the pressing surface comprising protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)

Abstract

An attaching apparatus is provided to prevent the defect of a wire bonding and the crack of a semiconductor chip due to voids by removing the voids generated between the semiconductor chip and a spacer through a void removal pin. An attaching apparatus attaches an insulating member on upper surfaces on a substrate and a semiconductor chip. A head(110) performs a reciprocal movement at a certain interval. A collet(130) is coupled with the head and has a vacuum hole on its lower surface facing the semiconductor chip to pick-up the insulating member. A plurality of void removal pins(140) are formed on a region except for an area adjacent to a position on which the vacuum hole is formed on the lower surface of the collet. The void removal pins pass through the insulating member when the insulating member is attached to form holes for exhausting air. A length of the void removal pin is longer than a height of the insulating member.

Description

어태치 장치{ATTACHING APPARATUS}Attachment device {ATTACHING APPARATUS}

도 1은 반도체칩과 스페이서 사이에 보이드가 발생된 상태에서 상부 반도체칩이 적층된 상태를 나타낸 도면.1 is a view showing a state in which an upper semiconductor chip is stacked in a state where voids are generated between a semiconductor chip and a spacer.

도 2는 본 발명에 따른 어태치 장치의 단면도.2 is a cross-sectional view of the attach device according to the present invention.

도 3은 본 발명에 따른 콜렛의 바닥면을 도시한 평면도.Figure 3 is a plan view showing the bottom surface of the collet according to the present invention.

도 4는 본 발명에 따른 보이드 제거 핀의 확대도.4 is an enlarged view of a void removal pin in accordance with the present invention.

도 5a는 기판 상에 하부 반도체칩이 접착된 상태를 나타낸 도면.5A is a view showing a state in which a lower semiconductor chip is adhered on a substrate.

도 5b는 본 발명에 따른 어태치 장치를 이용하여 스페이서를 픽업하고 하부 반도체칩으로 이송하는 상태를 나타낸 단면도.5B is a cross-sectional view illustrating a state in which a spacer is picked up and transferred to a lower semiconductor chip by using an attach apparatus according to the present invention;

도 5c는 보이드가 발생되게 스페이서가 하부 반도체칩의 상부면에 부착된 상태를 나타낸 단면도.5C is a cross-sectional view illustrating a state in which a spacer is attached to an upper surface of a lower semiconductor chip so that voids are generated.

도 5d는 스페이서에 보이드 제거 핀이 관통되어 보이드가 제거된 상태를 나타낸 단면도.5D is a cross-sectional view illustrating a state in which a void is removed through a spacer and voids are removed.

도 5e는 스페이서에서 어태치 장치가 제거된 상태를 나타낸 단면도.5E is a cross-sectional view showing a state where an attach device is removed from a spacer.

도 5f는 스페이서의 상부면에 상부 반도체칩을 부착시킨 단면도.5F is a cross-sectional view of the upper semiconductor chip attached to the upper surface of the spacer;

본 발명은 어태치 장치에 관한 것으로, 보다 구체적으로는, 접착부재를 부착할 때 발생되는 보이드(void)를 제거하기에 적합한 구조를 갖는 어태치 장치에 관한 것이다.The present invention relates to an attach apparatus, and more particularly, to an attach apparatus having a structure suitable for removing voids generated when attaching the adhesive member.

최근 들어, 반도체 제조 기술의 개발에 따라 단시간 내에 보다 많은 데이터를 처리하기에 적합한 반도체 소자(semiconductor device)가 개발되고 있다.Recently, with the development of semiconductor manufacturing technology, semiconductor devices suitable for processing more data in a short time have been developed.

반도체 소자는 순도 높은 실리콘으로 이루어진 실리콘 웨이퍼에 반도체칩을 제조하는 반도체칩 제조 공정, 반도체칩을 전기적으로 검사하는 다이 소팅(sorting) 공정 및 양품 반도체칩을 패키징하는 패키징 공정 등을 통해 제조된다.The semiconductor device is manufactured through a semiconductor chip manufacturing process for manufacturing a semiconductor chip on a silicon wafer made of high purity silicon, a die sorting process for electrically inspecting the semiconductor chip, and a packaging process for packaging a good semiconductor chip.

이들 중 패키징 공정에 의하여 반도체 소자의 성능 및 품질이 향상될 수 있다. 예를 들면, 최근에는 반도체 소자의 크기가 반도체칩의 약 100% 내지 120%에 불과한 칩 스캐일 패키지(chip scale package) 및 반도체 소자의 용량 및 처리 속도를 배가시키기 위해서 복수개의 반도체칩들을 상호 적층시킨 적층 반도체 패키지 등이 개발되었다.Among them, the packaging process may improve performance and quality of the semiconductor device. For example, in recent years, in order to double the capacity and processing speed of a chip scale package and a semiconductor device having a size of about 100% to 120% of a semiconductor chip, a plurality of semiconductor chips are stacked on each other. Laminated semiconductor packages and the like have been developed.

이들 중 적층 반도체 패키지는 복수개의 반도체칩들을 상호 적층 시키기 때문에 반도체칩들을 상호 절연시키는 절연부재(insulating member), 즉 스페이서를 필요로 한다. 스페이서는 반도체칩들을 상호 이격시켜 절연시키고, 하부 반도체칩에 형성된 도전성 와이어들의 변형을 방지한다.Among them, the stacked semiconductor package requires an insulating member, that is, a spacer, to insulate the semiconductor chips from each other because the plurality of semiconductor chips are stacked on each other. The spacers insulate the semiconductor chips from each other and prevent deformation of the conductive wires formed in the lower semiconductor chip.

도 1은 반도체칩과 스페이서 사이에 보이드가 발생된 상태에서 상부 반도체 칩이 적층된 상태를 나타낸 도면이다.1 is a view illustrating a state in which upper semiconductor chips are stacked in a state where voids are generated between a semiconductor chip and a spacer.

그러나, 도 1을 참조하면, 접착성 있는 스페이서(20)를 하부 반도체칩(10)에 부착할 때, 스페이서(20)의 에지(edge) 부분이 스페이서(20)의 중앙 부분보다 먼저 하부 반도체칩(10) 상에 부착되어 스페이서(20) 및 하부 반도체칩(10)의 사이에 빈 공간인 보이드(void; 22)가 빈번하게 발생되고 있다.However, referring to FIG. 1, when the adhesive spacer 20 is attached to the lower semiconductor chip 10, the edge portion of the spacer 20 is formed earlier than the center portion of the spacer 20. A void 22, which is attached to the top surface 10 and is an empty space between the spacer 20 and the lower semiconductor chip 10, is frequently generated.

스페이서(20) 및 하부 반도체칩(10) 사이에 보이드가 발생된 상태에서, 하부 반도체칩(30)이 보이드(22)를 갖는 스페이서(20)의 상부에 배치될 경우, 도 1에 도시된 바와 같이 상부 반도체칩(30)은 보이드(22)에 의하여 하부 반도체칩(10)에 대하여 기울어지게 배치될 수밖에 없다.In the state where voids are generated between the spacer 20 and the lower semiconductor chip 10, when the lower semiconductor chip 30 is disposed above the spacer 20 having the voids 22, as shown in FIG. 1. Likewise, the upper semiconductor chip 30 may be inclined with respect to the lower semiconductor chip 10 by the voids 22.

이와 같이 상부 반도체칩(30)이 하부 반도체칩(10)에 대하여 기울어지게 배치될 경우 상부 반도체칩(30)에 와이어 본딩 공정을 진행할 때 지정된 위치에 도전성 와이어(40)가 본딩되지 않아 와이어 본딩 불량을 유발시킨다.As such, when the upper semiconductor chip 30 is disposed to be inclined with respect to the lower semiconductor chip 10, when the wire bonding process is performed on the upper semiconductor chip 30, the conductive wire 40 is not bonded at the designated position, thereby causing poor wire bonding. Cause.

또한, 하부 반도체칩(10) 및 스페이서(20) 사이의 보이드(22)의 공기가 고온 공정에서 팽창하면서 터져 하부 반도체칩(10)의 크랙 또는 손상을 일으키는 문제점을 갖는다. 미설명 부호 1은 하부 반도체칩(10) 및 상부 반도체칩(30)이 실장되는 기판이다. In addition, the air of the void 22 between the lower semiconductor chip 10 and the spacer 20 expands in a high temperature process to cause cracking or damage of the lower semiconductor chip 10. Reference numeral 1 is a substrate on which the lower semiconductor chip 10 and the upper semiconductor chip 30 are mounted.

본 발명의 목적은 기판 및 반도체칩 상에 절연 부재를 부착하고, 절연 부재가 부착될 때 기판 및 절연 부재, 또는 반도체칩 및 절연 부재 사이에 발생되는 보이드를 제거하는 어태치 장치를 제공하는 데 있다.An object of the present invention is to provide an attaching apparatus for attaching an insulating member on a substrate and a semiconductor chip, and removing voids generated between the substrate and the insulating member or the semiconductor chip and the insulating member when the insulating member is attached. .

본 발명에 따른 어태치 장치는, 반도체칩이 부착될 기판의 상부면 및 반도체칩의 상부면에 접착성을 갖는 절연 부재를 부착하는 것으로써, 특정 구간을 왕복 운동하는 헤드, 상기 헤드와 결합되고, 상기 기판 및 상기 반도체칩과 마주보는 하부면에 진공홀이 형성되어 상기 절연 부재를 픽업하는 콜렛 및 상기 콜렛의 하부면 중 진공홀이 형성된 부근을 제외한 나머지 영역에 복수개 형성되며, 상기 반도체칩 및 상기 기판 상에 상기 절연 부재를 부착할 때 상기 절연 부재를 관통하여 공기를 배출시키는 구멍을 형성하는 보이드 제거 핀들을 포함한다.Attachment apparatus according to the present invention, by attaching an adhesive insulating member to the upper surface of the substrate to which the semiconductor chip is attached and the upper surface of the semiconductor chip, the head reciprocating a specific section, coupled with the head And a plurality of vacuum holes are formed in the lower surface facing the substrate and the semiconductor chip, and a plurality of the semiconductor chips are formed in the remaining region except for the vicinity of the collet for picking up the insulating member and the lower surface of the collet. And a void removing pin forming a hole through which the air is discharged when attaching the insulating member on the substrate.

(실시예)(Example)

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 의한 어태치 장치의 단면도이다.2 is a cross-sectional view of the attach apparatus according to the present invention.

도시된 바와 같이, 본 발명에 의한 어태치 장치(100)는 적층 반도체 패키지(50)에서 절연 부재 즉, 반도체칩(10, 30)들을 상호 이격시켜 절연시키고, 하부 반도체칩(10)에 형성된 도전성 와이어(40)들의 변형을 방지하는 스페이서(20)를 하부 반도체칩(10)에 부착하는 장치로, 어태치 장치(100)는 헤드(110), 샤프트(120), 콜렛(130) 및 보이드 제거 핀(140)들을 포함한다. 바람직하게, 본 발명에 의한 어태치 장치(100)은 스페이서(20) 뿐만 아니라 반도체칩(10)을 실장 부재에 부착하는 다이 어태치 공정에서는 반도체칩(10)을 픽업하여 실장 기판에 장착한다.As shown, the attach device 100 according to the present invention insulates the insulating members, that is, the semiconductor chips 10 and 30 from each other in the multilayer semiconductor package 50, and insulates the conductive elements formed on the lower semiconductor chip 10. A device for attaching a spacer 20 to the lower semiconductor chip 10 to prevent deformation of the wires 40. The attaching device 100 includes a head 110, a shaft 120, a collet 130, and voids. Pins 140. Preferably, the attach apparatus 100 according to the present invention picks up the semiconductor chip 10 and mounts it on the mounting substrate in the die attach step of attaching not only the spacer 20 but also the semiconductor chip 10 to the mounting member.

헤드(110)에는 샤프트(120)가 결합되고, 샤프트(120)에는 콜렛(130)이 결합 되며, 콜렛(130)의 하부면에는 보이드 제거 핀(140)들이 일정 길이로 돌출 형성된다.The shaft 120 is coupled to the head 110, the collet 130 is coupled to the shaft 120, and the void removing pins 140 protrude to a predetermined length on the lower surface of the collet 130.

헤드(110)는 좌/우로 움직이는 이송 장치(도시 안됨)에 의해 소정길이로 절단된 스페이서들이 모여있는 장소로부터 기판이 배치된 장소까지 이동된 후, 업/다운 장치(도시 안됨)에 의해 기판(1) 상에 본딩된 하부 반도체칩(10)까지 하강한다. 이러한, 헤드(110)에는 진공압이 형성되는 진공 홀(112) 및 샤프트(120)가 끼워지는 샤프트 홈(114)이 형성되는데, 샤프트 홈(114)은 진공홀(112)과 연통된다.The head 110 is moved from the place where the spacers cut to a predetermined length by the transfer device (not shown) moving left / right to the place where the substrate is placed, and then the substrate (not shown) by the up / down device (not shown). 1) is lowered to the lower semiconductor chip 10 bonded on. The head 110 is formed with a vacuum hole 112 in which a vacuum pressure is formed and a shaft groove 114 into which the shaft 120 is fitted. The shaft groove 114 communicates with the vacuum hole 112.

샤프트(120)는 파이프 형상으로 형성되며, 헤드(110)에 형성된 샤프트 홈(114)에 끼워진다. 샤프트(120)가 헤드(110)의 샤프트 홈(114)에 끼워진 후 샤프트(120)가 헤드(110)로부터 임의로 이탈되는 것을 방지하기 위해 샤프트(120)의 측면에서 나사(도시 안됨)를 이용하여 조인다. 파이프 형상을 갖는 샤프트(120)의 관통공(122)은 헤드(110)의 진공홀(112)과 직접 연통된다.The shaft 120 is formed in a pipe shape and fitted into the shaft groove 114 formed in the head 110. After the shaft 120 is fitted into the shaft groove 114 of the head 110, a screw (not shown) is used on the side of the shaft 120 to prevent the shaft 120 from being randomly released from the head 110. Tighten. The through hole 122 of the shaft 120 having a pipe shape is in direct communication with the vacuum hole 112 of the head 110.

콜렛(130)은 샤프트(120)의 외측면에 결합된다. 콜렛(130)은 일정 길이로 절단된 스페이서를 픽-업하는 역할을 한다. 콜렛(130)은 샤프트(120)의 외측면에 끼워지기 위한 콜렛 고정홈(132)을 포함한다. 콜렛 고정홈(132)은 샤프트(120)의 외측면이 끼워지기에 적합한 치수를 갖는다.The collet 130 is coupled to the outer side of the shaft 120. The collet 130 serves to pick up the spacer cut to a predetermined length. The collet 130 includes a collet fixing groove 132 for fitting to the outer surface of the shaft 120. The collet fixing groove 132 has a dimension suitable for fitting the outer surface of the shaft 120.

콜렛 고정홈(132)에는 진공압을 발생시키기 위한 관통공(134)이 형성되고, 관통공(134)은 콜렛(130)이 샤프트(20)에 끼워진 상태에서 샤프트(120)의 관통공(122)과 연통된다. 따라서, 헤드(110)의 진공홀(112), 샤프트(120)의 관통공(122) 및 콜렛(130)의 관통공(134)은 모두 하나로 연통되고, 이로 인해 진공 홀(112), 샤프트(120)의 관통공(122) 및 콜렛(130)의 관통공(134)에는 모두 진공압이 제공될 수 있다.The collet fixing groove 132 is formed with a through hole 134 for generating a vacuum pressure, the through hole 134 is a through hole 122 of the shaft 120 in a state where the collet 130 is fitted to the shaft 20. ). Accordingly, the vacuum hole 112 of the head 110, the through hole 122 of the shaft 120, and the through hole 134 of the collet 130 are all in communication with each other, so that the vacuum hole 112 and the shaft ( Both the through hole 122 of the 120 and the through hole 134 of the collet 130 may be provided with a vacuum pressure.

도 3은 본 발명에 의한 콜렛의 바닥면을 도시한 평면도이다.3 is a plan view showing the bottom surface of the collet according to the present invention.

도시된 바와 같이, 콜렛(130) 중 스페이서를 픽업하는 바닥면에는 관통공(134)과 연결된 복수개의 진공 홀(138)들이 형성되는데, 예를 들어 진공 홀(138)들은 콜렛(130) 바닥면의 네 모서리 각각과 중앙부분에 형성된다. 상술한 위치에 형성된 진공 홀(138)들은 관통공(134)과 진공 홀(138)들을 상호 연결시키는 연결공(136)에 의해 모두 연결된다. 바람직하게, 연결공(136)은 평면상에서 보았을 때, X 형상을 갖는다.As shown, a plurality of vacuum holes 138 connected to the through hole 134 are formed in the bottom surface of the collet 130 to pick up the spacers. For example, the vacuum holes 138 may be the bottom surface of the collet 130. Four corners of each are formed at the center and in the middle. The vacuum holes 138 formed at the above positions are all connected by the connection holes 136 interconnecting the through holes 134 and the vacuum holes 138. Preferably, the connecting hole 136 has an X shape when viewed in a plane.

다시 도 2 및 도 3을 참조하면, 콜렛(130)의 바닥면 중 진공 홀(138)들이 형성된 부분을 제외한 나머지 전면적에 보이드 제거 핀(140)들이 형성되는데, 보이드 제거 핀(140)들은 서로 일정간격 이격되고, 콜렛(130)의 바닥면으로부터 일정 길이로 돌출 형성된다.Referring to FIGS. 2 and 3 again, void removal pins 140 are formed on the entire surface of the bottom surface of the collet 130 except for the portion where the vacuum holes 138 are formed, and the void removal pins 140 are fixed to each other. Spaced apart from each other, protruding from the bottom surface of the collet 130 to a predetermined length.

도 4는 본 발명에 의한 보이드 제거 핀의 확대도이다.4 is an enlarged view of the void removing pin according to the present invention.

바람직하게, 보이드 제거 핀(140)은 원뿔 형상으로 형성되며, 보이드 제거 핀(140)의 길이는 스페이서(20)의 두께보다 길게 형성되어 스페이서(20)가 하부 반도체칩(10) 상부면에 부착할 때 보이드 제거 핀(140)들이 스페이서(20)를 관통할 수 있도록 한다. 그리고, 도시된 바와 같이, 보이드 제거 핀(140)의 팁 직경(A)은 3㎛∼7㎛로 미세하게 형성하여, 보이드 제거 핀(140)의 관통으로 인해 스페이서(20)에 형성된 공기 배출 구멍(24; 도 5e 참조)이 열에 의해 수축되어 쉽게 매꿔 질 수 있도록 한다.Preferably, the void removal pin 140 is formed in a conical shape, the length of the void removal pin 140 is formed longer than the thickness of the spacer 20 so that the spacer 20 is attached to the upper surface of the lower semiconductor chip 10 When the void removal pins 140 can penetrate the spacer 20. And, as shown, the tip diameter (A) of the void removal pin 140 is finely formed to 3㎛ ~ 7㎛, air discharge hole formed in the spacer 20 due to the penetration of the void removal pin 140 (24; see FIG. 5E) is contracted by heat so that it can be easily tied up.

이와 같이 콜렛(130)의 바닥면에 형성된 보이드 제거 핀들은 진공압, 또는 업다운 장치(도시 안됨)에 의해 도 5b에 도시된 바와 같이 반도체칩(10) 및 스페이서(20)를 픽업할 때는 콜렛의 내부로 밀려들어가 콜렛의 내부에 위치하는 것이 바람직하다.As such, the void removing pins formed on the bottom surface of the collet 130 may collect the semiconductor chip 10 and the spacer 20 as shown in FIG. 5B by a vacuum pressure or an up-down device (not shown). It is preferable to be pushed in and placed inside the collet.

이와 같이 구성된 어태치 장치를 이용하여 스페이서 및 반도체칩들을 적층시키는 과정에 대해 5a 내지 도 5f를 참조하여 개략적으로 설명하면 다음과 같다.A process of stacking spacers and semiconductor chips using the attach device configured as described above will be described below with reference to FIGS. 5A to 5F.

도 5a는 기판 상에 하부 반도체칩이 접착된 상태를 나타낸 도면이다.5A is a view illustrating a state in which a lower semiconductor chip is adhered to a substrate.

도시된 바와 같이. 접착부재(5)를 매개로 실장 부재, 예를 들어 기판(1)의 상부면에 마련된 칩 부착 영역에 하부 반도체칩(10)을 부착하고, 도전성 와이어(40)를 이용하여 하부 반도체칩(10)과 기판(1)을 전기적으로 연결시킨다.As shown. The lower semiconductor chip 10 is attached to a mounting member, for example, a chip attaching region provided on the upper surface of the substrate 1 via the adhesive member 5, and the lower semiconductor chip 10 is formed using the conductive wire 40. ) And the substrate 1 are electrically connected.

여기서, 기판(1)의 상부면 중 칩 부착 영역의 외측에는 전극 단자(2)들이 배열되고, 기판(1)의 하부면에는 전극 단자(2)들과 전기적으로 연결된 볼 랜드(4)들이 배열된다. 그리고, 하부 반도체칩(10)에서 접착 부재(5)가 부착되지 않는 하부 반도체칩(10)의 상부면에는 전극 단자(2)들과 대응하여 본딩패드(12)들이 배열되며, 본딩패드(12)들은 상술한 도전성 와이어(40)에 의해 기판(1)의 전극 패드(2)들과 전기적으로 연결된다.Here, the electrode terminals 2 are arranged outside the chip attaching region of the upper surface of the substrate 1, and the ball lands 4 electrically connected to the electrode terminals 2 are arranged on the lower surface of the substrate 1. do. In addition, bonding pads 12 are arranged on the upper surface of the lower semiconductor chip 10 to which the adhesive member 5 is not attached in the lower semiconductor chip 10 to correspond to the electrode terminals 2. ) Are electrically connected to the electrode pads 2 of the substrate 1 by the conductive wire 40 described above.

도 5b는 본 발명에 의한 어태치 장치를 이용하여 스페이서를 픽업하고 하부 반도체칩으로 이송하는 상태를 나타낸 단면도이다.5B is a cross-sectional view illustrating a state in which a spacer is picked up and transferred to a lower semiconductor chip by using the attaching apparatus according to the present invention.

도시된 바와 같이, 기판(1)의 상부면에 하부 반도체칩(10)이 부착되고, 하부 반도체칩(10) 및 기판(1)에 도전성 와이어(40)가 본딩되면, 도 5b에 도시된 바와 같이 어태치 장치(100)에 진공압을 발생시킨다. 이때, 보이드 제거 핀(140)들은 진공압, 또는 업다운 장치(도시안됨)에 의해 콜렛(130)의 내부로 밀려들어가 콜렛(130)의 바닥면은 평평하게 된다. As shown, when the lower semiconductor chip 10 is attached to the upper surface of the substrate 1, and the conductive wire 40 is bonded to the lower semiconductor chip 10 and the substrate 1, as shown in Figure 5b Similarly, a vacuum pressure is generated in the attach device 100. At this time, the void removal pins 140 are pushed into the collet 130 by a vacuum pressure or an up-down device (not shown) so that the bottom surface of the collet 130 is flat.

이와 같이, 보이드 제거 핀(140)들이 콜렛(130)의 바닥면에서 콜렛(130)의 내부로 밀려들어가고 콜렛(130)에 진공압이 발생되면, 진공압이 콜렛(130)의 관통공(134) 및 연결공(136)을 통해 콜렛(130)의 바닥면에 형성된 진공 홀(138)까지 전달되어 콜렛(130)의 바닥면에 스페이서(120)가 흡착된다. 콜렛(130)의 바닥에 스페이서(20)가 픽업되면, 어태치 장치(100)를 하부 반도체칩(10)이 부착된 위치까지 이송시킨다. 그리고, 어태치 장치(100)를 하부 반도체칩(10) 쪽으로 하강시킨다.As such, when the void removal pins 140 are pushed into the inside of the collet 130 from the bottom surface of the collet 130 and the vacuum pressure is generated in the collet 130, the vacuum pressure is a through hole 134 of the collet 130. And the connection hole 136 is transferred to the vacuum hole 138 formed on the bottom surface of the collet 130 to adsorb the spacer 120 to the bottom surface of the collet 130. When the spacer 20 is picked up at the bottom of the collet 130, the attach device 100 is transferred to the position where the lower semiconductor chip 10 is attached. Then, the attach device 100 is lowered toward the lower semiconductor chip 10.

도 5c는 보이드가 발생되게 스페이서가 하부 반도체칩의 상부면에 부착된 상태를 나타낸 단면도이다.5C is a cross-sectional view illustrating a state in which a spacer is attached to an upper surface of a lower semiconductor chip to generate voids.

어태치 장치(100)가 하부 반도체칩(10) 쪽으로 하강하여 도 5c에 도시된 바와 같이 하부 반도체칩(10)의 상부면에 스페이서(20)가 접촉되면 접착성을 갖는 스페이서(20)는 하부 반도체칩(10)의 상부면에 부착된다. 이때, 접착성이 있는 스페이서(20)의 에지(edge) 부분이 스페이서(20)의 중앙 부분보다 먼저 하부 반도체칩(10) 상부면에 부착될 경우, 도 5c에 도시된 바와 같이 스페이서(20) 및 하부 반도체칩(10)의 사이에 빈 공간인 보이드(22)가 발생된다. When the attaching device 100 descends toward the lower semiconductor chip 10 and the spacer 20 contacts the upper surface of the lower semiconductor chip 10 as shown in FIG. 5C, the spacer 20 having adhesiveness may be lowered. It is attached to the upper surface of the semiconductor chip 10. In this case, when the edge portion of the adhesive spacer 20 is attached to the upper surface of the lower semiconductor chip 10 before the center portion of the spacer 20, as shown in FIG. 5C, the spacer 20 may be formed. And a void 22, which is an empty space, between the lower semiconductor chips 10.

도 5c에 도시된 바와 같이 보이드(22)가 발생되도록 스페이서(20)가 부착되면, 후속 공정에서 스페이서(20)의 상부에 배치되는 상부 반도체칩(30)은 보이 드(22)에 의하여 하부 반도체칩(10)에 대하여 기울어지게 배치될 수밖에 없다(도 1참조).When the spacer 20 is attached so that the void 22 is generated as shown in FIG. 5C, the upper semiconductor chip 30 disposed on the upper portion of the spacer 20 in a subsequent process may be formed by the lower semiconductor. It is inevitably arranged to be inclined with respect to the chip 10 (see Fig. 1).

이와 같이 보이드(22)로 인해 상부 반도체칩(30)이 하부 반도체칩(10)에 대하여 기울어지게 배치될 경우 상부 반도체칩(30)에 와이어 본딩 공정을 진행할 때 지정된 위치에 도전성 와이어가 본딩되지 않아 와이어 본딩 불량이 유발되고, 하부 반도체칩(10) 및 스페이서(20) 사이의 발생된 보이드(22)가 고온 공정에서 터져 하부 반도체칩(10)의 크랙 또는 손상을 발생시킬 수 있다.As such, when the upper semiconductor chip 30 is inclined with respect to the lower semiconductor chip 10 due to the void 22, the conductive wire is not bonded to the designated position when the wire bonding process is performed on the upper semiconductor chip 30. Bad wire bonding may be caused, and the generated void 22 between the lower semiconductor chip 10 and the spacer 20 may burst in a high temperature process to cause cracking or damage of the lower semiconductor chip 10.

도 5c에 도시된 바와 같이 하부 반도체칩(10)의 상부에 스페이서(20)가 부착되면, 콜렛(130)에 인가된 진공압이 해제되면서, 보이드 제거 핀(140)들이 콜렛의 바닥면으로 돌출된다. 이와 다르게, 스페이서(20)를 하부 반도체칩(10)에 부착시키는 어태치 공정에서는 보이드 제거 핀(140)을 콜렛(130)의 내부로 업시키고, 어태치 공정이 완료되면, 보이드 제거 핀(140)들을 콜렛(130)의 바닥면으로 다운시키는 업다운 장치에 의해서 보이드 제거 핀(140)들이 콜렛(130)의 바닥면으로 돌출될 수 있다.As shown in FIG. 5C, when the spacer 20 is attached to the upper portion of the lower semiconductor chip 10, the vacuum removal force applied to the collet 130 is released, and the void removing pins 140 protrude to the bottom surface of the collet. do. Alternatively, in the attach process for attaching the spacer 20 to the lower semiconductor chip 10, the void removing pin 140 is raised into the collet 130, and when the attach process is completed, the void removing pin 140 is completed. The void removal pins 140 may protrude to the bottom surface of the collet 130 by an up-down device that moves the bottoms to the bottom surface of the collet 130.

도 5d는 스페이서에 보이드 제거 핀이 관통되어 보이드가 제거된 상태를 나타낸 단면도이다.5D is a cross-sectional view illustrating a state in which a void is removed through a spacer and a void is removed.

하부 반도체칩(10)과 스페이서(20)사이에 발생된 보이드(22)를 제거하기 위해서 상술한 방법에 의해 콜렛(130)의 바닥면으로 보이드 제거 핀(140)들이 돌출되면, 어태치 장치(100)를 하부 반도체칩(10) 쪽으로 계속 하강시킨다. 그러면, 도 5d에 도시된 바와 같이 콜렛(130)의 바닥면에 형성된 보이드 제거 핀(140)들이 스 페이서(20)를 가압하여 스페이서(20)를 뚫고 들어가 보이드 제거 핀(140)들이 스페이서(20)를 관통하게 된다. 이와 같이 보이드 제거 핀(140)들이 스페이서(20)를 관통하게 되면, 스페이서(20)에 공기를 배출시키는 구멍(24; 도 5e 참조)이 형성되어 도 5c에 도시된 바와 같이 하부 반도체칩(10)과 스페이서(20) 사이에 발생되었던 보이드(22) 내의 공기가 공기 배출 구멍(24)을 통해 외부로 빠져나간다. 따라서, 도 5d에 도시된 바와 같이 보이드(22)가 제거되어 스페이서(20)는 평평하게 하부 반도체칩(10)의 상부면에 부착된다.When the void removing pins 140 protrude to the bottom surface of the collet 130 by the above-described method to remove the voids 22 generated between the lower semiconductor chip 10 and the spacer 20, the attachment device ( 100 is continuously lowered toward the lower semiconductor chip 10. Then, as shown in FIG. 5D, the void removing pins 140 formed on the bottom surface of the collet 130 pressurize the spacer 20 to penetrate the spacer 20, and the void removing pins 140 may enter the spacer ( 20). As such, when the void removing pins 140 pass through the spacer 20, holes 24 (see FIG. 5E) for discharging air are formed in the spacer 20 to form the lower semiconductor chip 10 as shown in FIG. 5C. ) And the air in the void 22 generated between the spacer 20 is drawn out through the air outlet hole (24). Accordingly, as shown in FIG. 5D, the voids 22 are removed, and the spacers 20 are attached to the upper surface of the lower semiconductor chip 10 flatly.

도 5e는 스페이서에서 어태치 장치가 제거된 상태를 나타낸 단면도이고, 도 5f는 스페이서의 상부면에 상부 반도체칩을 부착시킨 단면도이다.5E is a cross-sectional view illustrating a state in which an attach device is removed from a spacer, and FIG. 5F is a cross-sectional view of an upper semiconductor chip attached to an upper surface of the spacer.

하부 반도체칩(10)의 상부면에 스페이서(20)를 부착한 후 어태치 장치(100)를 상승시키면, 보이드 제거 핀(140)들의 관통으로 인해 도시된 바와 같이 스페이서(20)에 공기 배출 구멍(24)의 자국이 남게 된다.After attaching the spacer 20 to the upper surface of the lower semiconductor chip 10 and then raising the attaching device 100, air discharge holes are formed in the spacer 20 as shown due to the penetration of the void removing pins 140. (24) marks remain.

그러나, 스페이서(22)에 발생된 공기 배출 구멍(24) 자국은 스페이서(20)를 하부 반도체칩(10) 상에 부착하는 공정이 진행되는 동안 계속적으로 가해지는 고온(150℃)의 열 및 도 5f에 도시된 바와 같이 스페이서(20)의 상부면에 상부 반도체칩(30)을 부착하는 공정이 진행되는 동안 가해지는 고온의 열로 인해 수축되면서 매꿔진다. 따라서, 스페이서(20)의 상부면에 상부 반도체칩(30)을 부착하는 공정이 완료되면, 도 5f에 도시된 바와 같이 보이드 제거 핀(140)의 관통으로 인해 스페이서(20)에 발생된 공기 배출 구멍(24)은 존재하지 않게 된다.However, the traces of the air discharge holes 24 generated in the spacer 22 may be applied to the high temperature (150 ° C.) heat and heat continuously applied during the process of attaching the spacer 20 to the lower semiconductor chip 10. As shown in 5f, the upper semiconductor chip 30 is attached to the upper surface of the spacer 20 while shrinking due to the high temperature heat applied during the process. Therefore, when the process of attaching the upper semiconductor chip 30 to the upper surface of the spacer 20 is completed, as shown in FIG. 5F, air generated in the spacer 20 due to the penetration of the void removing pin 140 is discharged. The hole 24 is not present.

본 발명에서는 스페이서를 부착할 때 발생되는 보이드를 제거하는 것에 대해 서만 설명하였지만, 본 발명에 의한 어태치 장치는 기판 상에 반도체칩을 부착하기 위해 기판 상에 테이프 타입의 접착제를 부착할 때도 접착제와 기판 사이에 발생되는 보이드를 제거하는 목적으로 사용될 수도 있다.In the present invention, only the removal of the voids generated when the spacer is attached is described, but the attaching apparatus according to the present invention is used to attach the adhesive even when the tape-type adhesive is attached on the substrate to attach the semiconductor chip on the substrate. It may be used for the purpose of removing voids generated between the substrates.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서 상세하게 설명한 바와 같이, 본 발명은 스페이서를 픽업하여 반도체칩의 상부면에 부착하는 어태치 장치에 보이드 제거 핀을 형성하면, 반도체칩에 스페이서를 부착하는 공정을 진행하는 동안 보이드 제거 핀이 스페이서를 관통하여 반도체칩 및 스페이서 사이에 발생된 보이드를 제거함으로써, 보이드로 인한 와이어 본딩 불량 및 반도체칩의 크랙을 방지할 수 있다. As described in detail above, in the present invention, when the void removing pin is formed in the attaching apparatus for picking up the spacer and attaching the upper surface of the semiconductor chip, the void removing pin is removed during the process of attaching the spacer to the semiconductor chip. By removing the voids generated between the semiconductor chip and the spacer through the spacer, it is possible to prevent wire bonding defects and cracks of the semiconductor chip due to the void.

Claims (4)

반도체칩이 부착될 기판의 상부면 및 반도체칩의 상부면에 접착성을 갖는 절연 부재를 부착하는 어태치 장치에 있어서, An attach apparatus for attaching an insulating member having an adhesive property to an upper surface of a substrate to which a semiconductor chip is attached and an upper surface of the semiconductor chip, 특정 구간을 왕복 운동하는 헤드;A head reciprocating a specific section; 상기 헤드와 결합되고, 상기 기판 및 상기 반도체칩과 마주보는 하부면에 진공홀이 형성되어 상기 절연 부재를 픽업하는 콜렛; 및A collet coupled to the head and having a vacuum hole formed in a lower surface facing the substrate and the semiconductor chip to pick up the insulating member; And 상기 콜렛의 하부면 중 진공홀이 형성된 부근을 제외한 나머지 영역에 복수개 형성되며, 상기 반도체칩 및 상기 기판 상에 상기 절연 부재를 부착할 때 상기 절연 부재를 관통하여 공기를 배출시키는 구멍을 형성하는 보이드 제거 핀들을 포함하는 것을 특징으로 하는 어태치 장치. A plurality of voids are formed in the remaining area of the lower surface of the collet except for the vicinity where the vacuum hole is formed, and when forming the insulating member on the semiconductor chip and the substrate, a void is formed through the insulating member to discharge air. Attachment device comprising removal pins. 제1항에 있어서, 상기 보이드 제거 핀들은 상기 보이드 제거 핀들을 업다운 시키는 업다운 장치 및 진공압의 발생과 해제에 의해 상기 절연 부재를 픽업할 때는 상기 콜렛의 내부로 유입되고, 공기를 배출시켜 보이드를 제거할 때는 상기 콜렛의 바닥면으로 돌출되는 것을 특징으로 하는 어태치 장치. The void removal pins of claim 1, wherein the void removal pins are introduced into the collet when picking up the insulation member by the generation and release of vacuum pressure and an up-down device for up and down the void removal pins, and the air is discharged to release the voids. Attachment device characterized in that protruding to the bottom surface of the collet when removing. 제1항에 있어서, 상기 보이드 제거 핀의 길이는 상기 절연 부재의 높이보다 긴 것을 특징으로 하는 어태치 장치.The attaching apparatus according to claim 1, wherein a length of the void removing pin is longer than a height of the insulating member. 제1항에 있어서, 상기 보이드 제거 핀의 팁부분 지름은 3∼7㎛인 것을 특징으로 하는 어태치 장치.The attaching device according to claim 1, wherein the diameter of the tip portion of the void removing pin is 3 to 7 µm.
KR1020070030524A 2007-03-28 2007-03-28 Attaching apparatus KR20080088103A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101332986B1 (en) * 2011-03-23 2013-11-25 가부시끼가이샤 히다찌 하이테크 인스트루먼츠 Die bonder
US9698117B2 (en) 2014-02-10 2017-07-04 Samsung Electronics Co., Ltd. Die bonding apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101332986B1 (en) * 2011-03-23 2013-11-25 가부시끼가이샤 히다찌 하이테크 인스트루먼츠 Die bonder
US9698117B2 (en) 2014-02-10 2017-07-04 Samsung Electronics Co., Ltd. Die bonding apparatus

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