KR20080085525A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to increase the electric capacity of a capacitor by increasing a height of a storage electrode region. An interlayer dielectric is formed on an upper portion of a semiconductor substrate(200) having a landing plug and a storage electrode contact plug(230). A hard mask layer pattern defining a storage electrode region(270) is formed on an upper portion of the interlayer dielectric. The interlayer dielectric is etched by using the hard mask layer pattern as an etching mask to form the storage electrode region. Two storage electrodes are formed at every one storage electrode contact plug by overlapping with predetermined regions. The hard mask layer pattern is removed. A lower conductive layer(280) is formed on an upper portion of the whole structure including the storage electrode region. An etch back process is performed until the interlayer dielectric is exposed to form a lower electrode.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100, 200: semiconductor substrate 105, 205: device isolation film

110, 210: Gate pattern 113, 213: Gate spacer

115, 215: landing plug contact 120, 220: first interlayer insulating film

125, 225: bit line spacer 127, 227: bit line

130 and 230: storage electrode contact plugs 145 and 245: etch stop layer

150, 250: second interlayer insulating film 155, 255: third interlayer insulating film

160 and 260: hard mask layer pattern 170 and 270: storage electrode region

180, 280: lower conductive film 257: fourth interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a PSG film is further deposited on an interlayer insulating film, and a storage electrode height and capacitance are applied by applying a dual storage electrode structure in which two storage electrodes overlap on one storage electrode contact plug. Can be increased.

In addition, by omitting the process of forming the MPS layer, a technique for improving the characteristics of the device by preventing the bridge between the resulting storage electrodes is disclosed.

In recent years, as the semiconductor device becomes extremely fine and highly integrated, the overall chip area is increased in proportion to the increase in memory capacity, but the area of the cell area where the pattern of the semiconductor device is formed is decreasing.

Such a reduction in cell area is accompanied by a reduction in the area of the cell capacitor, a decrease in sensing margin and a sensing speed, and a problem in that durability against soft errors caused by particles is degraded.

Therefore, there is a demand for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is represented by ε × As / d. Is the permittivity, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

1A to 1E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.

Referring to FIG. 1A, the gate pattern 110 is formed on the semiconductor substrate 100 having the device isolation layer 105, and then gate spacers 113 are formed on both sides of the gate pattern 110.

Next, a landing plug contact 115 is formed between the gate patterns 110, a bit line contact hole (not shown) is formed, and the bit line spacer is disposed over the entire portion including the bit line contact hole (not shown). Form 125.

The bit line contact hole (not shown) is buried to form a bit line 127.

Next, after forming the first interlayer insulating layer 120 on the resultant, the first interlayer insulating layer 120 is etched to form a storage electrode contact hole (not shown).

In addition, the storage electrode contact hole (not shown) is buried to form a storage electrode contact plug (SNC) 130.

Referring to FIG. 1B, an etch stop layer 145, a second interlayer insulating layer 150, and a third interlayer insulating layer 155 are sequentially formed on the semiconductor substrate 100 provided with the storage electrode contact plug.

Here, the etch stop layer 145 is a nitride layer, and the second interlayer insulating layer 150 and the third interlayer insulating layer 155 are preferably PSG (Phosphorus Silicate Glass) and PE-TEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) films, respectively. Do.

Referring to FIG. 1C, a hard mask layer (not shown) is formed on the third interlayer insulating layer 155, and a photoresist pattern (not shown) defining a storage electrode region is formed on the hard mask layer (not shown). Form.

Next, the hard mask layer (not shown) is etched using the photoresist pattern (not shown) as a mask to form a hard mask layer pattern 160 defining a storage electrode region.

Then, the photoresist pattern (not shown) is removed.

Referring to FIG. 1D, the storage electrode region 170 is formed by sequentially etching the third interlayer insulating layer 155 and the second interlayer insulating layer 150 using the hard mask layer pattern 160 as an etching mask.

In this case, the etching process may be performed until the etch stop layer 145 is exposed.

Next, the etch stop layer 145 exposed by the storage electrode region is etched and then the hard mask layer pattern 160 is removed.

Referring to FIG. 1E, a lower conductive layer 180 having a predetermined thickness is formed on the entire upper portion including the storage electrode region 170.

Next, an etch back process is performed to remove a lower conductive layer (not shown) on the third interlayer insulating layer 155 to form a lower electrode.

The lower conductive layer 180 may be any one of titanium (Ti), titanium nitride (TiN), and a combination thereof.

In the above-described method of manufacturing a semiconductor device, a method of increasing a surface area by growing a hemispherical metastable polysilicon (MPS) layer inside a storage electrode region has been proposed to improve capacitance. However, in the etching process for forming the storage electrode region, there is a problem in that the MPS layer causes a bridge due to a non-uniform etching profile, thereby deteriorating characteristics of the device.

In order to solve the above problem, the PSG film is further deposited on the interlayer insulating film, and the height and capacitance of the storage electrode are increased by applying a dual storage electrode structure in which two storage electrodes overlap on one storage electrode contact plug.

In addition, it is an object of the present invention to provide a method for manufacturing a semiconductor device by omitting the MPS layer forming step, thereby preventing the bridge between the storage electrodes generated thereby to improve the characteristics of the device.

Method for manufacturing a semiconductor device according to the present invention

Forming an interlayer insulating film on the semiconductor substrate including the landing plug and the storage electrode contact plug;

Forming a hard mask layer pattern defining a storage electrode region on the interlayer insulating layer;

Forming a storage electrode region by etching the interlayer insulating layer using the hard mask layer pattern as an etch mask, wherein two storage electrode regions are overlapped with one storage electrode contact plug;

Removing the hard mask layer pattern;

Forming a lower conductive film having a predetermined thickness on the entire upper portion including the storage electrode region;

And forming a lower electrode by performing an etch back process until the interlayer insulating film is exposed.

The interlayer insulating film may be any one selected from PSG (Phosphorus Silica Glass), PE-TEOS, and a combination thereof.

The interlayer insulating film is formed of a laminated structure of a first PSG film, a PE-TEOS film, and a second PSG film;

The first PSG film is formed to a thickness of 7000 to 8000 kPa,

The PE-TEOS film is formed to a thickness of 14000 ~ 16000Å,

The second PSG film is formed to a thickness of 500 to 6000 GPa,

The second PSG film is formed to a thickness of 4500 to 5500Å,

The lower conductive film is any one of titanium (Ti), titanium nitride film (TiN), and a combination thereof.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

Referring to FIG. 2A, the gate pattern 210 is formed on the semiconductor substrate 200 having the device isolation layer 205, and then gate spacers 213 are formed on both sides of the gate pattern 210.

Next, a landing plug contact 215 is formed between the gate patterns 210, a bit line contact hole (not shown) is formed, and the bit line spacer is disposed over the entire portion including the bit line contact hole (not shown). 225 is formed.

The bit line contact hole (not shown) is buried to form a bit line 227.

Next, after forming the first interlayer insulating layer 220 on the resultant, the first interlayer insulating layer 220 is etched to form a storage electrode contact hole (not shown).

In addition, the storage electrode contact hole (not shown) is buried to form the storage electrode contact plug SNC 230.

Referring to FIG. 2B, an etch stop layer 245, a second interlayer insulating layer 250, a third interlayer insulating layer 255, and a fourth interlayer insulating layer 257 are sequentially formed.

Herein, the second interlayer insulating film 250, the third interlayer insulating film 255, and the fourth interlayer insulating film 257 may be formed of PSG (Phosphorus Silicate Glass), PE-TEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, and combinations thereof. It is preferable to form using any one, and more preferably, respectively, sequentially stacking a first PSG (Phosphorus Silicate Glass), a PE-TEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film and a second PSG (Phosphorus Silicate Glass) film To form.

In this case, the first PSG (Phosphorus Silicate Glass) film is preferably formed to a thickness of 7000 to 8000 Å, the PE-TEOS film is preferably formed to a thickness of 14000 to 16000 Å, the second PSG film of 500 to 6000 Å It is preferable to form in thickness.

Further, the second PSG film is more preferably formed to a thickness of 4500 to 5500 kPa.

Referring to FIG. 2C, a photoresist pattern (not shown) defining a hard mask layer (not shown) and a storage electrode region is formed on the fourth interlayer insulating layer 257.

Next, a hard mask layer (not shown) is etched using the photoresist pattern (not shown) as a mask to form a hard mask layer pattern 260 defining a storage electrode region.

Then, the photoresist pattern (not shown) is removed.

Referring to FIG. 2D, the storage layer 270 is formed by etching the fourth interlayer insulating layer 257, the third interlayer insulating layer 255, and the second interlayer insulating layer 250 using the hard mask layer pattern 260 as a mask. do.

Here, the storage electrode region 270 may be formed such that two storage electrode regions 270 overlap one storage electrode contact plug 230.

In this case, the etching process may be performed until the etch stop layer 245 is exposed.

Next, the etch stop layer 245 exposed by the storage electrode region 270 is etched.

Referring to FIG. 2E, after removing the hard mask layer pattern 260, a lower conductive layer 280 having a predetermined thickness is formed on the entire upper portion including the storage electrode region 270.

Here, the lower conductive film 280 is preferably formed using any one of titanium (Ti), titanium nitride film (TiN), and a combination thereof.

 Next, the lower conductive layer 280 is separated by performing an etch back process until the fourth interlayer insulating layer 257 is exposed to form a lower electrode having a dual storage electrode structure.

In the method of manufacturing a semiconductor device according to the present invention, by increasing the height of the storage electrode region, the capacitance of the capacitor may be increased to form a stable and efficient device, and the capacitance of the DRAM may be increased due to the increased capacitance of the capacitor. The S / A Off Set characteristic, which is an essential element, is improved, thereby improving the characteristics of the device.

In addition, it is possible to prevent the bridge phenomenon between the storage electrodes generated when forming a conventional MPS (Metastable Poly Silicon) layer.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

Forming an interlayer insulating layer on the semiconductor substrate including the landing plug and the storage electrode contact plug; Forming a hard mask layer pattern defining a storage electrode region on the interlayer insulating layer; Forming a storage electrode region by etching the interlayer insulating layer using the hard mask layer pattern as an etching mask, wherein the storage electrode contact plug is formed by overlapping two storage electrode regions with a predetermined region; Removing the hard mask layer pattern; Forming a lower conductive film having a predetermined thickness on the entire upper portion including the storage electrode region; And Forming a lower electrode by performing an etch back process until the interlayer insulating film is exposed; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The interlayer insulating film is a method of manufacturing a semiconductor device, characterized in that any one selected from PSG (Phosphorus Silica Glass), PE-TEOS and combinations thereof. The method of claim 1, The interlayer insulating film is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of the first PSG film, PE-TEOS film and the second PSG film. The method of claim 3, wherein And the first PSG film is formed to a thickness of 7000 to 8000 kPa. The method of claim 3, wherein The PE-TEOS film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 14000 ~ 16000Å. The method of claim 3, wherein The second PSG film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 500 to 6000 GHz. The method of claim 3, wherein The second PSG film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 4500 to 5500 5. The method of claim 1, The lower conductive layer is any one of titanium (Ti), titanium nitride (TiN), and a combination thereof.

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