KR20080080612A - A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device - Google Patents

Abstract

There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.

Description

A method of forming a layer on a surface of a first material embedded in a second material in a structure for a semiconductor device.

The present invention relates to a method of forming a layer on the surface of a first material embedded in a second material in a structure for a semiconductor device. However, in particular, the present invention relates only to a method of forming a diffusion barrier in an interconnect structure covering a metal wire embedded in a dielectric.

In a standard copper interconnect integration configuration for an integrated circuit mold, a dielectric barrier is deposited over the interlevel dielectric (ILD) after the chemical mechanical polishing (CMP) step and on the full sheet over the copper wire. The barrier has two roles: 1) to prevent copper diffusion into the dielectric, and 2) to function as a via etch stop.

A common problem with known SiN and SiC barriers is the weak interface between the copper wire and the covered barrier. This weak interface leads to a lack of initial reliability due to the reduced electromigration resistance. In addition, the electric field concentration is closest to the upper portion of the copper wire, thereby improving local copper migration and pressure induced voiding.

The ability to deposit material at selected locations only during fabrication of integrated circuits is advantageous because it obviates the need for expensive patterning steps to define the deposition area. For example, prior to Cu double damascene treatment, a so-called self-aligned barrier (SAB) is expected to replace the dielectric barrier film for covering the metal line. SAB (CoWP, etc.) is mainly applied to improve electromigration resistance and reduce capacitive coupling between adjacent metal wires.

Current integrated schemes for self-aligning barriers are optionally used in electroless processes based on catalytic activation of metal surfaces to be covered. First, the catalyst, generally palladium, is mainly deposited on metal wires, and a barrier is deposited on the wires in a substantially electroless plating bath. Palladium promotes selective self-aligned growth of barriers on the line. To avoid excessive current leakage from the line during use, any palladium deposited between metal lines must be removed correctly. Since palladium activation for copper is not 100% selective, the activation and cleaning steps are very important for integration. In this approach, selectivity is achieved by reacting the metal part of the surface to catalysis. The disadvantage of this approach is that only a metal film can be deposited on top of the metal surface.

Known electroless CoWP deposition processes result in an increase in line height that causes any gain in capacitance to be partially lost. In addition, the electroless growth film tends to grow in the horizontal direction, thereby reducing the dielectric space. This leads to an increase in capacitive coupling between lines, which reduces the reliability. These processes may also cause metal deposition between metal wires, leading to degradation of leakage current characteristics.

It is also known in the art to use physical vapor deposition (PVD) to deposit metal TaN / Ta barriers over copper wire. To date, two different approaches are known. In short, the first approach involves lithographic patterning of the metal barrier to remove the metal barrier between the copper wires. The second approach involves creating recesses in the copper wire to fill these areas with barriers. The first approach requires expensive extra masking steps. Also, some misalignment errors result in complete barrier removal on one side of the line. In a second approach, recesses are created in the copper wire by CMP over polish or wet chemical etching. The PVD barrier is then deposited over the dielectric and metal wires. In the second CMP step, the barrier on the field is removed leaving the TaN / Ta barrier cap on the recess of the copper wire. The single junction of this approach is: 1) Cu recesses are particularly difficult to control with different line widths, 2) Cu etchback consumes Cu space to increase resistivity, 3) costly in two CPM steps, and 4) The chipback step is to spread / break the low-k properties of the intermetallic dielectric.

It is desirable to provide a new selective deposition process that selectively grows a metal film or nonmetal film or metal on the dielectric and alleviates at least some of the problems discussed above.

According to the present invention, a method of forming a layer on a surface of a first material embedded in a second material in a structure for a semiconductor device, the method comprising selectively depositing a layer on the surface of the first material by a vapor deposition step, and vapor deposition step The surface of the second material is treated prior to the vapor deposition step so that no layer is deposited on the second material during.

In a preferred embodiment, the vapor deposition step comprises an atomic layer deposition step.

The treatment step converts the surface of the second material from a hydrophilic surface to a hydrophobic surface.

In one embodiment, the treating step converts the surface of the dielectric, second material, from a hydrophilic surface to a hydrophobic surface.

Prior to the treatment step the surface of the second material is substantially terminated with hydroxyl groups and after the treatment step the surface of the second material is substantially terminated with methyl groups.

This can be accomplished by exposing the surface of the second material to hexamethyl disilazane (HMDS) vapor.

In another embodiment the surface of the second material is treated with acidic cleaning, such as HF wet cleaning or HF steam cleaning, to render the surface hydrophobic.

In another embodiment, the treating step deposits a layer of resist material on the surface of the first material and on the surface of the second material and irradiates the layer of resist material with lithographic flux, due to reflection of the flux by the first material One of the resist materials present substantially above the second material, prior to developing at least one region of the resist material present substantially above the second material; And removing the region of the resist material which is substantially above the first material without removing the above region.

The invention is particularly useful for the deposition of diffusion barrier layers over metal lines in interconnect structures for semiconductor devices.

Embodiments of the present invention will be described below by way of example with reference to the accompanying drawings.

1 (a) to 1 (f) are schematic diagrams illustrating a manufacturing process of a structure for a semiconductor device;

2 shows the HMDS vapor to be deposited on the surface;

3 is a graph showing the amount of Ta as a function of the number of cycles deposited by ALD for various surface types,

4 is a graph showing the surface coverage of an ALD film as a function of different surface treatments,

5 (a) to 5 (k) are schematic diagrams illustrating a manufacturing process of a structure for a semiconductor device.

In a preferred embodiment of the present invention, atomic layer deposition (ALD) is used to selectively deposit the barrier layer on the metal interconnects of the semiconductor substrate. ALD is a deposition technique known to be uniform, suitable and very controllable in the deposition state. ALD technology involves sequential pulses of gaseous reactants (or precursors) that simultaneously react with the wafer surface. The growth of the layer is self limiting by the absorption of reactants at the surface reaction sites available during the precursor pulse. ALD depends largely on the density of ligands, availability, accessibility and reactivity with ALD reactants at the wafer surface.

Selective atomic layer deposition is made possible by locally deactivating the absorbing surface, i.e., preventing selected portions of the absorbing surface from chemically reacting with the supplied precursor.

Many ALD precursors are very reactive to hydrophilic groups such as hydroxyl groups and amines based on ligands naturally present on the dielectric surface. Prior to ALD application, these hydrophilic groups on the dielectric surface are converted to hydrophobic groups that do not react to the ALD precursor. Thus, when ALD is applied, local growth does not occur on the dielectric surface, but only on the metal surface.

Referring to FIGS. 1A-1F, the partially formed double inlay structure 1 includes a dielectric layer 2, a metal via 3 formed in the dielectric layer 2, a dielectric layer 2, and a metal via 3. It has a metal diffusion barrier (4) to separate the. This structure 1 may be formed according to standard practice.

After the metal vias 3 are deposited in accordance with standard practice and chemical mechanical polishing (CMP) is carried out, the corrosion inhibitor 5 is removed by plasma treatment, for example hydrogen based plasma treatment.

Plasma treatment exposes to hydrophobic groups such as hydroxyl-based amines or amines, and the dielectric layer 2 terminates. In a preferred embodiment, the exposed hydroxyl groups are passivated / deactivated by exposing the dielectric layer 2 to hexamethyl disilazane (HMDS) vapor. As shown in FIG. 2, HMDS vapor 20 replaces hydroxyl group 21 with Si-methyl ligand 23 at the dielectric surface and does not react to various ALD precursors at the normal temperatures used in ALD.

In addition, atomic layer deposition is preferably performed using pentakis-dimethylamidotantalum (PDMAT) and NH ₃ as precursors in a temperature range between 200 and 275 ° C. The precursor exposure time is generally at least 0.5 seconds per pulse to allow saturation of all reaction sites. After exposure near 40 cycles, a Ta ₃ N ₅ barrier 6 of approximately 2 nm in thickness is obtained in the metal via, which is sufficient for the purpose of covering. Because of the high selectivity to the metal, the metal wire can be substantially covered with the barrier 6. Only a very small amount of barrier 6a is deposited between the metal lines on the dielectric (<1e15at / cm2).

The growth state of the barrier depends on the density of the reaction groups on the surface. As shown in FIG. 3, after 20-100 cycles of sequential precursor exposure, the amount of Ta deposited on the Cu surface was observed to be 50-20 times greater than in methylated, eg, CVD SiOC type materials.

The selectivity of precursor absorption is due to the low amount of reactive surface groups on the SiOC surface (the presence of methyl groups that do not react significantly). However, during the initial stages of growth, less precursor molecules are chemisorbed on the methylated surface compared to copper, thus the selectivity of the ALD process will be explained. If the number of cycles applied to the SiOC is large, the deposition will predominantly occur on the already deposited material and island-like growth conditions will occur. Lower initial densities of activated surface groups will increase the number of cycles before the islands touch each other. In Figure 4, the surface coverage shows ALD membranes as a function of different surface pretreatments. Application of argon or hydrogen plasma can increase the number of initial absorption sites. The growth rate per cycle will be low while avoiding any plasma surface treatment.

Referring again to FIGS. 1A-1F, the final HF immersion is used to remove any barrier 6a deposited on the dielectric to avoid the formation of potential leakage paths. Finally, a dielectric layer 7 is further deposited in a standard manner over the first dielectric layer 2 and the barrier 6.

In another embodiment without using HMDS, dielectric layer 2 is in fact hydrophobic, but has a hydrophilic surface, for example as a result of plasma treatment. In this embodiment, the dielectric layer 2 is treated with an acid such as HF wet cleaning or steam cleaning prior to deposition of the barrier 6 to render the surface of the dielectric layer 2 hydrophobic. The barrier 6 can then be selectively deposited over the metal wire as described above.

Covering the line with the ALD barrier in this way has several advantages, particularly the ALD barrier on the metallic surface with good selectivity compared to hydrophobic surfaces. Additional advantages of ALD include the suitability of the deposition and control process at the atomic stage of growth rate. In addition, very thin barriers can be used compared to CoWP, minimizing form and capacitance increase. The growth of barriers is also minimized.

Now, another embodiment of the present invention will be described a process based on local resin phenomena on reflective metal lines to create self-aligned opening regions for barrier deposition. Self-aligned resist development takes advantage of the difference in reflectance between the metal wire and the intermetallic dielectric layer. During the maskless illumination step, the threshold of development reaches locally over the metal line due to light reflection ("local double exposure") at the metal resin interface. The threshold dose of development is adjusted over the metal wire so that the illumination dose is insufficient between the metal wires where light is absorbed. A preferred resist that is capable of reaching the development threshold and allowing the resist to be removed is a standard 193 nm negative resist. After resist removal, an optional metal or dielectric barrier is preferably deposited using an ALD deposition method. Residual resist does not react to the ALD precursor, so barrier growth mainly occurs above the metal line.

This process will be described in more detail with reference to Figs. 5 (a) -5 (k). In a first step of forming the interconnect structure, an antireflective dielectric material layer 101 is deposited over a layer of dielectric 100, such as a low-K insulator. Antireflective dielectric materials, such as bottom anti-reflecting coatings (BARC), are well known as materials that substantially absorb rather than reflect photolithographic light flow. The hard mask 102 is then deposited in a standard manner over the antireflective dielectric material layer 101.

Mask 103 is used to deposit a pattern of resist negative 104 on hardmask 102 in a standard resist rotation step, and photolithography exposure is performed.

The resist pattern is transferred through the hard mask 102 in a standard manner to form one or more vias 105, and the resist pattern 104 is removed by, for example, plasma etching.

The diffusion barrier layer 106 is formed in a standard manner over the sidewalls of the vias 105 and the hardmask 102. Next, a metal layer 107, in this example copper, is deposited to fill the vias 105. This is accomplished in a standard manner by depositing the initial copper seed layer and then filling the vias 105 with copper by electrochemical plating.

If the copper over the via 105 becomes excessive, a portion of the barrier layer 106 over the hard mask 102 and the hard mask 102 itself are removed in a standard manner by chemical mechanical polishing (CMP).

Following this, a conventional 193 nm negative resist layer 108 is deposited over the antireflective dielectric material layer 101 and copper 107. Next, the negative resist layer 108 is exposed to the lithographic light flux 109 without using a mask. As shown in FIG. 6 (h), the flux enters the layer 108 substantially perpendicularly. Flux that travels across the negative resist layer 108 and enters the copper line 107 is reflected back through the layer 108. However, flux that travels through the negative resist layer 108 and enters the antireflective dielectric material 101 is absorbed by that material. As a result, the area of the negative resist layer 108 that is substantially directly above the copper vias 107 is exposed to flow more than the area of the negative resist layer 108 that is substantially above the antireflective dielectric material 101. The intensity and duration of the incident light flux 109 reaches a portion where the development threshold for the negative resist layer 108 is substantially directly above the copper wire 107 but substantially above the antireflective dielectric material 101. It is chosen not to.

Next, in a standard manner, the portion of the resist layer 108 developed to expose the copper wire 107 is removed. ALD is then used to selectively deposit barrier layer 110 over copper wire 107. The regions of the resist layer 108 do not react to the ALD precursor and little or no growth occurs over these regions. The conditions for applying the ALD, see Figures 1 to 4 may be the same as the above-described embodiment, that is, pentakis in the temperature range between 200 to 275 ℃ - to FIG tantalum (PDMAT) and NH ₃ dimethylamido When used as a precursor, it can generally be made into the precursor exposure time of 0.5 second or more per pulse.

Thereafter, the remaining regions of the resist layer 108 are removed, for example by plasma etching or wet chemical means, and the barrier 110 is left locally over the copper wire 107 so that the barrier has only small lateral protrusions.

Finally, another dielectric layer (not shown) may be deposited over the first dielectric layer 100 and the barrier 110 in a standard manner.

According to this approach, the barriers with only minor lateral growth are well aligned and well defined. The resist and any residues can be easily removed after selective barrier deposition to avoid the formation of potential leakage paths. In addition, the capacitance between metal vias is reduced because no SiC or SiCN capping and / or etch stop layer and USG hardmask are used, as in known approaches. Moreover, this approach results in significant improvements in dielectric reliability and electromigration lifetime due to the full metal coating of the wire.

It will be appreciated that other vapor deposition techniques such as CVD may be used instead of ALD in embodiments of the present invention. While the above embodiments relate to the deposition of diffusion barriers in interconnect structures, it will be appreciated that embodiments of the present invention may be used to deposit other types of layers in various structures of semiconductor devices.

Therefore, the present invention will be described with reference to the preferred embodiments, the embodiments are only representative, and as described in the appended claims and their equivalents, those skilled in the art can make modifications and changes within the spirit and scope of the invention. It will be understood that it can be added. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The words "including", "including", and the like do not exclude the presence of elements or steps that are not listed in any claim or in the specification as a whole. The sign of a single component does not exclude the sign of a plurality of components.

Those skilled in the art will readily recognize that various parameters disclosed in the detailed description of the invention may be modified, and that various embodiments disclosed and / or claimed may be combined within the scope of the invention.

Claims (19)

A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device, the method comprising: Selectively depositing the layer on the surface of the first material by a vapor deposition step, And treating the surface of the second material prior to the vapor deposition step such that the layer is not deposited on the second material during the vapor deposition step. The method of claim 1, The vapor deposition step includes atomic layer deposition (ALD). The method of claim 1, And wherein said treating step causes said surface of said second material to be substantially insensitive to at least one chemical component used in said vapor deposition step. The method of claim 3, wherein Said treating step converts the surface of said second material from a hydrophilic surface to a hydrophobic surface. The method of claim 1, And wherein the surface of the second material is substantially terminated in hydroxyl groups before the treatment step and the surface of the second material is substantially terminated with a methyl group after the treatment step. The method of claim 1, Said treating step exposes a surface of said second material to HMDS vapor. The method of claim 1, Wherein said treating step comprises cleaning the surface of said second material. The method of claim 7, wherein The cleaning step comprises an acidic wet clean or an acidic vapor clean. The method of claim 8, Wherein said cleaning step comprises HF wet cleaning or HF steam cleaning. The method of claim 1, Said treating step comprises depositing a third material on the surface of said second material that does not react to at least one component used in said vapor deposition step. The method of claim 1, The processing step, Depositing a layer of resist material on the surface of the first material and the surface of the second material, Irradiating the layer of resist material with a lithographic flux, prior to the one or more regions of the resist material that are substantially above the second material, due to reflection of the flux by the first material More substantially allowing a region of the resist material present above to develop, Removing the region of the resist material that is substantially above the first material without removing one or more regions of the resist material that are substantially above the second material Layer formation method. The method of claim 11, And a layer of antireflective material disposed between the second material and the layer of resist material. The method of claim 1, And the first material is a metal. The method of claim 13, And the metal is copper. The method according to any one of claims 1 to 14, And the second material is a dielectric. The method of claim 15, And the second material is an ultra low k material. The method of claim 1, Wherein said layer is a diffusion barrier. The method of claim 2, Precursors used in ALD are PDMAT and NH ₃ . The method of claim 1, And the structure is an interconnect structure.

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