CN104835778B - A kind of preparation method of semiconductor devices - Google Patents
A kind of preparation method of semiconductor devices Download PDFInfo
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- CN104835778B CN104835778B CN201410045985.XA CN201410045985A CN104835778B CN 104835778 B CN104835778 B CN 104835778B CN 201410045985 A CN201410045985 A CN 201410045985A CN 104835778 B CN104835778 B CN 104835778B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of preparation method of semiconductor devices, and the preparation method includes：Step 1: provide Semiconductor substrate；Step 2: low k dielectric and the copper interconnection structure in the low k dielectric are formed on the semiconductor substrate；Step 3: the surface that first gas source handles the copper interconnection structure and the low k dielectric is introduced, to form heavy polymer layer；Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；Step 6: deposition forms dielectric capping layers on the boundary layer.In accordance with the invention it is possible to improve Cu/ dielectric passivation interfacial characteristicses, to improve electromigration characteristic, and then the reliability and yields of device are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of preparation method of semiconductor devices.
Background technology
With the development of integrated circuit, characteristic size constantly reduces, and the current density that plain conductor is passed through steeply rises；Together
When, the raising of chip integration causes unit area power consumption to increase, and therefore, the reliability of metal connecting line is always IC designs and system
Make major issue of concern.In plain conductor, the electronics and the metal ion that are moved along electric field opposite direction carry out momentum-exchange, lead
Metal ion is caused to produce by spreading leading mass transportation, this phenomenon is referred to as electromigration.In the mutual link of semiconductor devices
Electromigration is important metal failure mechanism in structure.Failure has two kinds caused by electromigration, is interconnection line short circuit and open circuit respectively.
With the electromigration of Cu ions, atom loss can occur near negative electrode, localised tension gradually increases, after reaching critical value,
Cavity will be formed, so as to cause the increase of resistance, ultimately results in interconnection line open circuit.And in anode atom accumulation region, local pressure
Power constantly increases so that there may be metal protrusion in the region, if the metal of protrusion and the metal interconnection neighbouring with it contact,
It may result in interconnection line short circuit.
Electromigration can have a plurality of diffusion path, such as surface, interface, grain boundary decision, lattice diffusion.Research table in recent years
Bright, electromigration is mainly as caused by the diffusion of Cu/ dielectric overlays bed boundary and Cu/ barrier layers interface, and Cu/ dielectric overlays
Bed boundary is the most important diffusion path of electromigration, and therefore, Cu/ dielectric overlays bed boundary is for the corresponding electrical property of control and reliably
Property performance is vital, can suppress the diffusion phenomena of Cu/ dielectric passivations interface by improving interface performance, change
Kind electromigration characteristic.Various processing technology of interface are widely used as the method that can improve Cu/ dielectric overlays bed boundary
With research.
Therefore, it is proposed to a kind of interface processing method that can improve Cu/ dielectric passivation interfacial characteristicses, existing to solve
The deficiency of technology.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices,
Including step：
Step 1: provide Semiconductor substrate；
Step 2: low k dielectric and the copper-connection knot in the low k dielectric are formed on the semiconductor substrate
Structure；
Step 3: the surface that first gas source handles the copper interconnection structure and the low k dielectric is introduced, to form height
Molecular weight polymerized nitride layer；
Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；
Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；
Step 6: deposition forms dielectric capping layers on the boundary layer.
Further, it is additionally included in and the surface of the copper interconnection structure and the low k dielectric is handled to be formed
Before stating heavy polymer layer, the step of the top surface exposed using copper interconnection structure described in ammonia or nitrogen treatment.
Further, the first gas source is the mixed gas of three silicon substrate nitrogen (TSA) and ammonia.
Further, the first gas source is introduced to soak the surface of the copper interconnection structure and the low k dielectric
Profit and cleaning treatment, to form the heavy polymer layer.
Further, the second gas source is trimethyl silane or tetramethylsilane.
Further, second gas source described in radio frequency processing, with formed can with the heavy polymer layer react etc.
Gas ions.
Further, the interlayer materials are SiCN.
Further, the thickness predetermined value of the boundary layer is 2~5nm.
Further, formed with etching stop layer between the low k dielectric and the Semiconductor substrate.
Further, the dielectric capping layers material is the silicon nitride of silicon nitride or carbon dope.
It is to sum up shown, according to the manufacturing process of the present invention using processing technology of interface to the copper interconnection structure and described low
The interface of k dielectric layer is handled, and improves Cu/ dielectric passivation interfacial characteristicses, to improve electromigration characteristic, and then improves device
Reliability and yields.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 C are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 2 is, and according to the method for exemplary embodiment of the present to be TSA send out on the surface of copper interconnection structure and low k dielectric
The schematic diagram of the high molecular polymer formed after raw adsorption reaction；
Fig. 3 is the covering feelings in copper interconnection structure surface corner boundary layer according to the method for exemplary embodiment of the present
The close-up schematic view of condition；
Fig. 4 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Manufacturing process of the invention using processing technology of interface at the interface of the copper interconnection structure and the low k dielectric
Manage to form the coating with the covering of good turning.Obviously, execution of the invention is not limited to the technology of semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
Below, when reference picture 1A- Fig. 1 C implement copper wiring technique to describe method according to an exemplary embodiment of the present invention
The detailed step of coating is formed on copper interconnection layer.
First, as shown in Figure 1A, it illustrates form first copper interconnection layer on a semiconductor substrate 100 according to prior art
The schematic cross sectional view of device after layer 103.According to prior art preferred embodiment, using dual damascene process
Form copper interconnection layer 103.
As shown in Figure 1A, there is provided Semiconductor substrate 100, the Semiconductor substrate 100 may include any semi-conducting material, this
Semi-conducting material may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V
Or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate 100 includes various isolation structures, such as shallow trench isolation.Semiconductor substrate
100 can also include organic semiconductor or such as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator
Layered semiconductor.Deposition forms etching stop layer 101 on a semiconductor substrate 100, and its material is carbon containing silicon nitride (NDC),
Chemical vapor deposition (CVD) can be selected in the method for preparation.As an example, when carrying out chemical vapor deposition, power 200
~400W, heating make the temperature in cavity to 300~400 DEG C, and the pressure in cavity is 2~5Torr, the trimethyl silane of use
The gas flow of (3MS) or tetramethylsilane (4MS) is 100~200 cc/mins (sccm), He gas flow
For 350~450 cc/mins (sccm), NH3Gas flow is 300~500 cc/mins (sccm), during deposition
Between continue 3s.Then, deposition forms low k dielectric 102 on etching stop layer 101, and its dielectric constant k is less than 3, generally use
It is prepared by chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique, its material can be silica glass (FSG),
Silica (silicon oxide), carbonaceous material, porous material (porous-like material) or homologue.As
One example, low k dielectric 102 are that porous material includes pore-foaming agent, and pore-foaming agent can be any suitable material for producing hole
Material, porogen material can be hydrocarbon, acrylates (acrylate) race containing resist polymer, be fluorinated
Polymer etc..It can solidify in a furnace or by other process implementings, such as ultraviolet curing, rapid thermosetting, flash of light
Lamp solidification, laser curing etc..Etching low k dielectric 102 forms groove to expose Semiconductor substrate 100.In the trench according to
It is secondary that physical vapor can be selected and sink formed with diffusion impervious layer (not shown) and copper metal layer, the wherein preparation method of diffusion impervious layer
Product (PVD), barrier layer can be in the temperature between -40 DEG C~400 DEG C and about between 0.1 millitorr (mTorr)~100 millitorr
(mTorr) formed under pressure.Diffusion barrier material be metal or metal compound layer material for example tantalum, tantalum nitride, titanium,
Titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its constituent.In addition, diffusion impervious layer may also include it is more
Individual film layer.It is preferred that one layer of cobalt (Co) enhancement layer (enhancement layer) (not shown) is initially formed on the diffusion barrier, so
After re-form copper crystal seed layer (not shown).Cobalt enhancement layer can improve the electromigration immunity of copper-connection, can simultaneously be effectively add
Copper filling capacity in smaller geometry groove/structure by force.On copper crystal seed layer copper gold is formed using electrochemistry electric plating method
Belong to layer, by the way that stable electroplating technology can be maintained to the instant analysis of organic matter and inorganic matter water-bath composition and supply, wherein
Preferable copper electroplating chemical additive and current waveform can complete the gap filling to 0.07um~0.1um.Then, using change
Mechanical lapping (CMP) PROCESS FOR TREATMENT copper metal layer is learned, to remove unnecessary copper metal layer, until exposing low k dielectric 102, is made
Copper metal layer 103 flushes with the top of low k dielectric 102, stops cmp.
Using ammonia (NH3) or nitrogen plasma treatment copper metal layer 103, the ammonia being passed through or nitrogen reduction interconnection
Cupric oxide in structure, the final cupric oxide removed in interconnection structure.As an example, using ammonia (NH3) plasma
Copper metal layer is handled, the flow of gas is 200~300 cc/mins (sccm), and reaction room pressure can be 5~10 millis
Hold in the palm (mTorr), power is 900W~1100W, and the time of corona treatment is 5s~10s.
As shown in Figure 1B, the mixed gas of ammonia and three silicon substrate nitrogen (TSA) is passed through in reative cell, to the copper metal layer
Infiltrated and cleaned with the surface of low k dielectric, Chemisorption occurs on surface, forms the polymerization with HMW
Nitride layer.The molecular formula of used three silicon substrates nitrogen is Si3H9N, the high-molecular-weight poly formed after surface reacts as shown in Figure 2
The schematic diagram of compound.Next, being passed through trimethyl silane (3MS) or tetramethylsilane (4MS) in reative cell, radio frequency is opened
(RF) power supply, glow discharge, it is passed through gas ionization and occurs into plasma, caused plasma with heavy polymer layer
Reaction generation SiCN, is repeatedly alternately repeated above-mentioned two step, until generating the SiCN boundary layers 105 with the covering of preferable turning.
As an example, the thickness predetermined range of SiCN boundary layers is 2~5nm, shows in Fig. 3 and is turned on copper interconnection structure surface
The coverage condition of SiCN boundary layers 105 at angle 104.As seen from the figure due to the addition of boundary layer, Step Coverage can be improved, especially
Covering around the corner has clear improvement.
It is believed that the surface used in physical absorption, absorption, absorption or chemisorbing monolayer reactant is inhaled on the surface
Gravitation is self-limited type, because because substrate surface has the limited available site of individual reactant, so introducing gas
Only have an individual layer during body source to be deposited on the surface.Once limited individual site occupied by reactant, then reactant enters one
Step deposition will be obstructed.This circulation is repeated to reach the layer of expectation thickness.
Usually, time reaction surface being exposed in gas source every time can be in several microseconds to several milliseconds, by several seconds, very
To in the range of a few minutes.Typically, the sufficiently long time should be kept, during so as to provide sufficient for the reactant of certain volume
Between adsorb/be chemically adsorbed on whole reaction surface, and be formed on compound layer.
As shown in Figure 1 C, the deposit dielectrics coating 106 on SiCN boundary layers 105.The material of dielectric capping layers 106
For the silicon nitride or silicon nitride of carbon dope, preferably SiCN materials.Form the SiCN preferred plasma activated chemical vapour deposition of technique
Technique, its source gas are tetramethylsilane/trimethyl silane, ammonia and nitrogen, and carrier gas is helium.As an example, electricity is situated between
Matter coating has compression, and thickness range is 100 angstroms~500 angstroms.Dielectric capping layers with compression have good attached
Put forth effort, suppress the diffusion of copper and stronger mechanical structure is provided, also there is higher breakdown voltage, good air-tightness and passivation
Copper metal layer.
Reference picture 4, the flow chart for the step of method according to an exemplary embodiment of the present invention is implemented successively is illustrated therein is,
For schematically illustrating the flow of whole manufacturing process.
In step 401, there is provided Semiconductor substrate, form low k dielectric on a semiconductor substrate and positioned at low k dielectric
In copper interconnection structure；
In step 402, the surface of first gas source processing copper interconnection structure and low k dielectric is introduced, to form high score
Sub- weight polymers layer；
In step 403, second gas source processing heavy polymer layer is introduced, to form boundary layer；
In step 404, step 402 and step 403 are alternately repeated, until the thickness of boundary layer reaches predetermined value；
In step 405, deposition forms dielectric capping layers on boundary layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of preparation method of semiconductor devices, including：
Step 1: provide Semiconductor substrate；
Step 2: low k dielectric and the copper interconnection structure in the low k dielectric are formed on the semiconductor substrate；
The surface of the copper interconnection structure and the low k dielectric is infiltrated and cleaned Step 3: introducing first gas source
Processing, to form heavy polymer layer；
Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；
Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；
Step 6: deposition forms dielectric capping layers on the boundary layer.
2. according to the method for claim 1, it is characterised in that be additionally included in and the copper interconnection structure and the low k are situated between
The surface of electric layer is handled with before forming the heavy polymer layer, mutual using copper described in ammonia or nitrogen treatment
The step of linking the top surface that structure exposes.
3. according to the method for claim 1, it is characterised in that the first gas source is three silicon substrate nitrogen (TSA) and ammonia
Mixed gas.
4. according to the method for claim 1, it is characterised in that the second gas source is trimethyl silane or tetramethyl
Silane.
5. according to the method for claim 1, it is characterised in that second gas source described in radio frequency processing, can be with institute with formation
State the plasma of heavy polymer layer reaction.
6. according to the method for claim 1, it is characterised in that the interlayer materials are SiCN.
7. according to the method for claim 1, it is characterised in that the thickness predetermined value of the boundary layer is 2~5nm.
8. the method as described in claim 1, it is characterised in that formed between the low k dielectric and the Semiconductor substrate
There is etching stop layer.
9. according to the method for claim 1, it is characterised in that the dielectric capping layers material is silicon nitride or carbon dope
Silicon nitride.
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| CN105575881B (en) * | 2014-10-11 | 2018-09-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN106505031B (en) * | 2015-09-07 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of copper interconnection structure, copper interconnection structure and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102007022621B4 (en) * | 2007-05-15 | 2017-06-01 | Advanced Micro Devices Inc. | A method of making a dielectric overcoat for copper metallization using a hydrogen-based thermal-chemical treatment |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
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