CN108695237A - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN108695237A CN108695237A CN201710218249.3A CN201710218249A CN108695237A CN 108695237 A CN108695237 A CN 108695237A CN 201710218249 A CN201710218249 A CN 201710218249A CN 108695237 A CN108695237 A CN 108695237A
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- coating
- interlayer dielectric
- dielectric layer
- aln layers
- doping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof, the method includes:Semiconductor substrate is provided;Interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer are formed on the semiconductor substrate;Coating is formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating includes the AlN layers of ion doping.According to the production method of semiconductor devices provided by the invention, during metal interconnection process, AlN layers by forming ion doping on copper interconnection structure surface are used as coating, avoid leakage current and time breakdown problem, ELECTROMIGRATION PHENOMENON is improved, the reliability of semiconductor devices is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof.
Background technology
With the development of integrated circuit, characteristic size constantly reduces, and the current density that plain conductor is passed through steeply rises;Together
When, the raising of chip integration causes unit area power consumption to increase, and therefore, the reliability of metal connecting line is always IC designs and system
Make major issue of concern.In plain conductor, the electronics and the metal ion that are moved along electric field negative direction carry out momentum-exchange, lead
Metal ion is caused to generate by spreading leading mass transportation, this phenomenon is referred to as electromigration (EM).In the mutual of semiconductor devices
Electromigration is important metal failure mechanism in connection structure.There are two types of failures caused by electromigration, be respectively interconnection line open circuit and
Short circuit.With the electromigration of Cu ions, atom loss can occur near cathode, localised tension gradually increases, and reaches critical value
After, cavity will be formed, so as to cause the increase of resistance, eventually leads to interconnection line open circuit.And in anode atom accumulation region, office
Portion's pressure constantly increases so that may have metal protrusion in the region, if the metal of protrusion and metal neighbouring with it interconnection
Contact may result in interconnection line short circuit.
Electromigration can have a plurality of diffusion path, such as surface, interface, grain boundary decision, lattice diffusion.Research table in recent years
Bright, caused by electromigration is mainly the diffusion by the covering bed boundarys Cu/ and the barrier layers Cu/ interface, and Cu/ coverings bed boundary is
The most important diffusion path of electromigration, therefore, it is to pass for controlling corresponding electrical property and reliability performance that Cu/, which covers bed boundary,
Important, the diffusion phenomena of Cu/ coatings interface can be inhibited by improving interface performance, improve electromigration characteristic.Respectively
Kind processing technology of interface is widely used and studies as that can improve the method that Cu/ covers bed boundary.
However, according to the prior art during forming the covering bed boundarys Cu/, the interaction of Cu/ coverings bed boundary,
The problems such as infiltration, attachment fastness, there is still a need for solve and be continuously improved in production practice.
Therefore, in view of the above-mentioned problems, the present invention proposes a kind of new semiconductor devices and preparation method thereof.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices, including:
Semiconductor substrate is provided;
Interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer are formed on the semiconductor substrate;
Coating is formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating packet
Include the AlN layers of ion doping.
Further, the ion of doping includes Ge.
Further, the coating is formed using atom deposition method.
Further, it includes AlCH to form AlN layers of the source gas3。
Further, the source gas for carrying out the Ge ion dopings includes GeH4。
Further, the coating further includes undoped AlN layers above the AlN layers of ion doping.
Further, wherein the thickness of the AlN layers of the ion doping is the 1/2-2/3 of coating overall thickness.
Further, the doping concentration of Ge ions is gradually reduced from the bottom to top.
Further, further include copper interconnection structure surface described in corona treatment before forming the coating to remove
The step of copper oxide.
Further, further include the steps that annealing is executed to the coating after forming the coating.
In addition, the present invention also provides a kind of semiconductor devices comprising:
Semiconductor substrate;
The interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer being formed in semiconductor substrate;
The coating being formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating
AlN layers including ion doping.
Further, the ion of doping includes Ge.
Further, the coating further includes undoped AlN layers above the AlN layers of ion doping, wherein institute
The thickness for stating the AlN layers of ion doping is the 1/2-2/3 of coating overall thickness.
Further, CuGe-AlN alloy-layers are also formed between the copper interconnection structure and the coating.
Further, the doping concentration of Ge ions is gradually reduced from the bottom to top.
According to the production method of semiconductor devices provided by the invention, during metal interconnection process, by mutual in copper
The AlN layers that ion doping is even formed on body structure surface are used as coating, avoid leakage current and time breakdown problem, improve
ELECTROMIGRATION PHENOMENON improves the reliability of semiconductor devices.
Description of the drawings
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, the above and other purposes of the present invention,
Feature and advantage will be apparent.Attached drawing is used for providing further understanding the embodiment of the present invention, and constitutes explanation
A part for book is not construed as limiting the invention for explaining the present invention together with the embodiment of the present invention.In the accompanying drawings,
Identical reference label typically represents same parts or step.
In attached drawing:
Fig. 1 is a kind of schematic flow of the production method of one semiconductor devices according to an exemplary embodiment of the present
Figure.
Fig. 2A -2E are the devices that the step of according to an exemplary embodiment of the present one method is implemented successively obtains respectively
Schematic cross sectional view.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
In the interconnection structure of semiconductor devices, electromigration (EM) is important metal failure mechanism.Electromigration can have
A plurality of diffusion path, such as surface, interface, grain boundary decision, lattice diffusion.Recent studies indicate that electromigration is mainly by Cu/
Caused by the diffusion for covering bed boundary and the barrier layers Cu/ interface, and Cu/ coverings bed boundary is the most important diffusion road of electromigration
Diameter, therefore, it is vital for controlling corresponding electrical property and reliability performance that Cu/, which covers bed boundary, can pass through improvement
Interface performance inhibits the diffusion phenomena of Cu/ coatings interface, improves electromigration characteristic.Various processing technology of interface are as energy
The method for enough improving Cu/ coverings bed boundary is widely used and studies.
Aluminium nitride (AlN) can either be effectively improved electromigration (EM) as a kind of brand-new material for copper interconnection structure
Phenomenon, while also there is etching selectivity more higher than traditional etching stop layer.But in existing production technology, before Al
It drives body easily to penetrate into interlayer dielectric layer, causes leakage current and time breakdown (TDDB) problem, seriously affect semiconductor devices
Reliability.
Therefore, it is necessary to propose a kind of production method of semiconductor devices, the electricity of Cu/ coverings bed boundary can effectively be avoided to move
It moves, while ensureing that the performance of semiconductor is stablized.
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices, including:
Semiconductor substrate is provided;
Interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer are formed on the semiconductor substrate;
Coating is formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating packet
Include the AlN layers of ion doping.
Wherein, the ion of doping includes Ge;The coating is formed using atom deposition method;It is formed AlN layers described
Source gas include AlCH3;The source gas for carrying out the Ge ion dopings includes GeH4;The coating further includes being located at ion
Undoped AlN layers above the AlN layers of doping;The thickness of the AlN layers of the wherein described ion doping is the 1/ of coating overall thickness
2-2/3;The doping concentration of Ge ions is gradually reduced from the bottom to top;Further include corona treatment before forming the coating
The step of copper interconnection structure surface is to remove copper oxide;Further include being held to the coating after forming the coating
The step of row annealing.
According to the production method of semiconductor devices provided by the invention, during metal interconnection process, by mutual in copper
The AlN layers that ion doping is even formed on body structure surface are used as coating, avoid leakage current and time breakdown problem, improve
ELECTROMIGRATION PHENOMENON improves the reliability of semiconductor devices.
[Embodiment Yi ]
It is a kind of according to an exemplary embodiment of the present one semiconductor device below with reference to Fig. 1 and Fig. 2A -2E, wherein Fig. 1
The schematic flow chart of the production method of part, Fig. 2A -2E are that according to an exemplary embodiment of the present one method is implemented successively
The schematic cross sectional view for the device that step obtains respectively.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step packet of the preparation method
It includes:
Step S101:Semiconductor substrate is provided;
Step S102:It forms interlayer dielectric layer on the semiconductor substrate and copper in the interlayer dielectric layer is mutual
Link structure;
Step S103:Coating is formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein described
Coating includes the AlN layers of ion doping.
In the following, being described in detail to the specific implementation mode of the production method of the semiconductor devices of the present invention.
First, it executes step S101 and provides semiconductor substrate 200 as shown in Figure 2 A.
Illustratively, in the present invention the semiconductor substrate 200 can be in the following material being previously mentioned at least one
Kind:Monocrystalline silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI) on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, the composition of semiconductor substrate 200
Material selection monocrystalline silicon.Isolation structure is also formed in semiconductor substrate 200, the isolation structure is shallow trench isolation
(STI) structure or selective oxidation silicon (LOCOS) isolation structure, it is different active that isolation structure, which divides semiconductor substrate 200,
Area can form various semiconductor devices, such as NMOS and PMOS etc. in active area.It is also formed in semiconductor substrate 200
Various trap (well) structures, to put it more simply, being omitted in diagram.
It is also formed with etching stop layer 201 on semiconductor substrate 200, material is carbon containing silicon nitride (NDC), is prepared
Method can be selected chemical vapor deposition (CVD).As an example, when carrying out chemical vapor deposition, power be 200~
400W, heating make the temperature in cavity to 200~400 DEG C, and the pressure in cavity is 2~5Torr, the trimethyl silane of use
The gas flow of (3MS) or tetramethylsilane (4MS) is 200~200 cc/mins (sccm), the gas flow of He
For 350~450 cc/mins (sccm), NH3Gas flow is 200~500 cc/mins (sccm), when deposition
Between continue 3s.
Then, step S102 is executed, as shown in Figure 2 B, forms 202 He of interlayer dielectric layer in the semiconductor substrate 200
Copper interconnection structure 203 in the interlayer dielectric layer 202.
Illustratively, the material of the interlayer dielectric layer 202 can be that (formation is interlayer dielectric to low k dielectric
Layer), or ultra low k dielectric materials (formation is super interlayer dielectric layer).In general, low k dielectric refers to dielectric
Constant (k values) is less than 4 dielectric material, and ultra low k dielectric materials refer to the dielectric material that dielectric constant (k values) is less than 2.Usually adopt
It is prepared with chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique, material can be silica glass
(FSG), silica (silicon oxide), carbonaceous material, porous material (porous-like material) or similar
Object.As an example, interlayer dielectric layer 202 is low k dielectric, and the low k dielectric includes for porous material
Pore-foaming agent, pore-foaming agent can be any suitable materials for generating hole, and porogen material can be hydrocarbon, contain resist
Acrylates (acrylate) race polymer, fluorinated polymer etc..It can in a furnace or to pass through other techniques real
Apply solidification, such as ultraviolet curing, rapid thermosetting, flash lamp solidification, laser curing etc..
Next, etching the interlayer dielectric layer 202 and etching stop layer 201, to expose semiconductor substrate 200, formed
Groove.It is sequentially formed with diffusion impervious layer (not shown) and copper metal layer 203, the wherein system of diffusion impervious layer in the trench
Preparation Method can be selected physical vapour deposition (PVD) (PVD), barrier layer can between -40 DEG C~400 DEG C temperature with about between 0.1 millitorr
(mTorr)~200 it is formed under the pressure of millitorr (mTorr).Diffusion barrier material is the material of metal or metal compound layer
Such as tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its constituent.In addition, diffusion
Barrier layer also may include multiple film layers.It is preferred that being initially formed one layer of cobalt (Co) enhancement layer (enhancement on the diffusion barrier
Layer then) (not shown) re-forms copper seed layer (not shown).The electromigration immunity that cobalt enhancement layer can improve, while can
Effectively to reinforce the copper filling capacity in smaller geometry groove/structure.The side being electroplated using electrochemistry on copper seed layer
Method forms copper metal layer 203, by that can maintain stabilization to organic matter and inorganic matter water-bath ingredient and the instant analysis of supply
Electroplating technology, wherein preferred copper electroplating chemical additive and current waveform can be completed to fill out the gap of 0.07um~0.1um
It fills.
Then, using chemical mechanical grinding (CMP) process copper metal layer 203, to remove extra copper metal layer, directly
To interlayer dielectric layer 202 is exposed, so that copper metal layer 203 and the top of interlayer dielectric layer 202 is flushed, stop chemical mechanical grinding.
Since air oxidation causes the surface of copper metal layer 203 to generate copper oxide by oxidation.Using ammonia (NH3) or nitrogen (N2) etc. from
Daughter handles copper metal layer 203, the ammonia (NH being passed through3) or nitrogen (N2) copper oxide in reduction interconnection structure, final removal is mutual
Link the copper oxide in structure.As an example, using ammonia (NH3) corona treatment copper metal layer, the flow of gas is
200~200 cc/mins (sccm), reaction room pressure can be 5~20 millitorrs (mTorr), power be 900W~
The time of 1200W, corona treatment are 5s~20s.
Then, step S103 is executed, as shown in Figure 2 C, in the copper interconnection structure 203 and the interlayer dielectric layer 202
Coating 204 is formed on surface, wherein the coating includes the AlN layers of ion doping.
Illustratively, any technology well known to those skilled in the art may be used in the formation process of the coating 204,
Such as physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) etc..As an example,
It is preferable to use atomic layer deposition method (ALD) progress for the deposition process.In the ald process, it is only deposited in each growth cycle single
The film of atomic layers thick can realize large area homoepitaxial and good Step Coverage energy although the speed of ALD is slower
Power, and the content for forming film impurities is relatively low.
Specifically, depositing temperature is 350 DEG C, cavity indoor pressure 3Torr, the flow control of reactant gas 200~
500sccm.First, it is passed through AlCH3Gas 0.5-2s.Then, Ar gas 6s are imported, reaction chamber is rinsed and take away extra reaction
Gas, with reactant separation.Then it is passed through GeH4Gas 15s.Then, Ar gases 6s is imported with reactant separation.Then, it imports
NH3/N2Gas 20s.Then, Ar gases 6s is imported with reactant separation.So far a reaction time is completed.It can be every by controlling
A GeH reaction time4The flow or sputtering time of gas control the doping concentration of Ge in generated AlGeN layers 204a.Show
Example property, when being passed through GeH4When gas time is 15s, the thickness for the AlGeN layers 204a that this reaction time obtains is 0.73 angstrom,
Middle Ge doping concentrations are 8.5atom%.After the AlGeN layers 204a for generating target thickness, it can make to be passed through GeH4Gas time is 0s
Continue to react, to generate AlN layers of 204b.Illustratively, the thickness of the AlN layers 204b obtained in a reaction time is
0.46 angstrom.This period certain number is repeated, to obtain the AlN layers 204b of target thickness.Illustratively, the doping concentration of Ge ions
It is gradually reduced from the bottom to top.Illustratively, the thickness for the AlN layers 204a that the ion doping is formed is 204 overall thickness of coating
1/2-2/3.As an example, the thickness of the AlGeN layers of 204a is about the 2/3 of overburden cover, the AlN layers of 204b
Thickness be about the 1/3 of overburden cover.
Next, further including being moved back to the execution of the coating 204 after forming the coating 204 as shown in Figure 2 D
The step of fire processing.As an example, annealing temperature is 300~400 DEG C.By annealing, copper-connection metal layer
CuGe-AlN alloy-layer 204c can be formed between 203 and above-mentioned coating 204, by the combination of CuGe-AlN, can effectively be carried
The adhesion strength of high coating 204.Simultaneously compared with using Si doping, Ge Doped ions have lower diffusion relative to copper
Rate, and CuGe has lower resistivity, to improve the performance of device.The doping concentration of Ge is from the bottom to top in the coating
It gradually reduces, it is seen that realize the balance reduced between resistivity and improvement ELECTROMIGRATION PHENOMENON.Method according to the invention it is possible to aobvious
Write the performance that ground improves copper interconnection structure.
Further include forming dielectric capping layers on the coating 204 as shown in Figure 2 E after above-mentioned annealing steps
205 the step of.Illustratively, the material of dielectric capping layers 205 includes the silicon nitride or silicon nitride of carbon dope, preferably silicon nitride
Material.It can prevent copper to be diffused into dielectric layer between the low k layer of surrounding, adhesiveness, physical property and the electricity of dielectric capping layers
Gas performance performances such as the air-tightness of dielectric layer and metal layer, internal stress and elasticity modulus and reliable between the low k layer of its lower layer
Property is very important.As an example, it is 100 angstroms~500 angstroms that dielectric capping layers, which have compression, thickness range,.
[Embodiment Er ]
The structure of semiconductor devices provided in an embodiment of the present invention is described in 2E below in conjunction with the accompanying drawings.The semiconductor
Device includes semiconductor substrate 200, the interlayer dielectric layer 202 that is formed in semiconductor substrate 200 and is located at the interlayer dielectric
Copper interconnection structure 203 in layer 202, and be formed on the surface of the copper interconnection structure 203 and the interlayer dielectric layer 202
Coating 204.Wherein:
The semiconductor substrate 200 can be following at least one of the material being previously mentioned:Monocrystalline silicon, silicon-on-insulator
(SOI), silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..As an example, the constituent material of semiconductor substrate 200 selects monocrystalline
Silicon.Isolation structure is also formed in semiconductor substrate 200, the isolation structure is shallow trench isolation (STI) structure or office
Portion's silica (LOCOS) isolation structure, isolation structure divide semiconductor substrate 200 for different active areas, can be in active area
Form various semiconductor devices, such as NMOS and PMOS etc..Various traps (well) knot is also formed in semiconductor substrate 200
Structure, to put it more simply, being omitted in diagram.Be also formed with etching stop layer 201 on semiconductor substrate 200, material be containing
The silicon nitride (NDC) of carbon.
The material of the interlayer dielectric layer 202 can be low k dielectric (formation is interlayer dielectric layer), or
Ultra low k dielectric materials (formation is super interlayer dielectric layer).It is less than in general, low k dielectric refers to dielectric constant (k values)
4 dielectric material, ultra low k dielectric materials refer to the dielectric material that dielectric constant (k values) is less than 2.As an example, interlayer is situated between
Electric layer 202 is low k dielectric, and the low k dielectric is porous material.
The copper interconnection structure 203 is copper metal layer.
The coating 204 includes the AlN layers 204a of ion doping.Wherein, the ion of doping includes Ge, the Ge
The thickness for the AlGeN layers 204a that ion doping is formed is the 1/2-2/3 of 204 overall thickness of coating, and the doping concentration of Ge ions
It is gradually reduced from the bottom to top.As an example, the thickness of the AlGeN layers of 204a is about the 2/3 of overburden cover, described
The thickness of AlN layers of 204b is about the 1/3 of overburden cover.
CuGe-AlN alloy-layers 204c is also formed between the copper interconnection structure 203 and the coating 204.Pass through
The combination of CuGe-AlN can effectively improve the adhesion strength of coating 204.Simultaneously with using Si doping compared with, Ge adulterate from
Son has lower diffusivity relative to copper, and CuGe has lower resistivity, to improve the performance of device.
Dielectric capping layers 205 are also formed on the coating 204.Illustratively, the material of dielectric capping layers 205
Material includes the silicon nitride or silicon nitride of carbon dope, preferably silicon nitride material.
According to semiconductor devices provided by the invention, during metal interconnection process, by copper interconnection structure surface
The upper AlN layers for forming ion doping are used as coating, avoid leakage current and time breakdown problem, and it is existing to improve electromigration
As improving the reliability of semiconductor devices.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of production method of semiconductor devices, which is characterized in that include the following steps:
Semiconductor substrate is provided;
Interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer are formed on the semiconductor substrate;
Form coating on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating include from
The AlN layers of son doping.
2. the method as described in claim 1, which is characterized in that the ion of doping includes Ge.
3. the method as described in claim 1, which is characterized in that form the coating using atom deposition method.
4. the method as described in claim 1, which is characterized in that it includes AlCH to form AlN layers of the source gas3。
5. method as claimed in claim 2, which is characterized in that the source gas for carrying out the Ge ion dopings includes GeH4。
6. the method as described in claim 1, which is characterized in that the coating further includes on the AlN layers of ion doping
Undoped AlN layers of side.
7. method as claimed in claim 6, which is characterized in that the thickness of the AlN layers of the wherein described ion doping is coating
The 1/2-2/3 of overall thickness.
8. method as claimed in claim 2, which is characterized in that the doping concentration of Ge ions is gradually reduced from the bottom to top.
9. the method as described in claim 1, which is characterized in that before forming the coating further include corona treatment
The step of copper interconnection structure surface is to remove copper oxide.
10. the method as described in claim 1, which is characterized in that after forming the coating further include to the covering
Layer executes the step of annealing.
11. a kind of semiconductor devices, which is characterized in that including:
Semiconductor substrate;
The interlayer dielectric layer and the copper interconnection structure in the interlayer dielectric layer being formed in semiconductor substrate;
The coating being formed on the surface of the copper interconnection structure and the interlayer dielectric layer, wherein the coating includes
The AlN layers of ion doping.
12. device as claimed in claim 11, which is characterized in that the ion of doping includes Ge.
13. device as claimed in claim 11, which is characterized in that the coating further includes the AlN layers positioned at ion doping
Undoped AlN layers of top, wherein the thickness of the AlN layers of the ion doping is the 1/2-2/3 of coating overall thickness.
14. device as claimed in claim 12, which is characterized in that also formed between the copper interconnection structure and the coating
There are CuGe-AlN alloy-layers.
15. device as claimed in claim 12, which is characterized in that the doping concentration of Ge ions is gradually reduced from the bottom to top.
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| CN201710218249.3A CN108695237B (en) | 2017-04-05 | 2017-04-05 | Semiconductor device and manufacturing method thereof |
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| CN201710218249.3A CN108695237B (en) | 2017-04-05 | 2017-04-05 | Semiconductor device and manufacturing method thereof |
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| CN108695237A true CN108695237A (en) | 2018-10-23 |
| CN108695237B CN108695237B (en) | 2020-12-15 |
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| US20040207093A1 (en) * | 2003-04-17 | 2004-10-21 | Sey-Shing Sun | Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| US20160307766A1 (en) * | 2014-11-26 | 2016-10-20 | Asm Ip Holding B.V. | Cyclic doped aluminum nitride deposition |
| CN106876325A (en) * | 2015-12-11 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
| CN108122821A (en) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040207093A1 (en) * | 2003-04-17 | 2004-10-21 | Sey-Shing Sun | Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| US20160307766A1 (en) * | 2014-11-26 | 2016-10-20 | Asm Ip Holding B.V. | Cyclic doped aluminum nitride deposition |
| CN106876325A (en) * | 2015-12-11 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
| CN108122821A (en) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
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