CN105575881B - A kind of production method of semiconductor devices - Google Patents
A kind of production method of semiconductor devices Download PDFInfo
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- CN105575881B CN105575881B CN201410534793.5A CN201410534793A CN105575881B CN 105575881 B CN105575881 B CN 105575881B CN 201410534793 A CN201410534793 A CN 201410534793A CN 105575881 B CN105575881 B CN 105575881B
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Abstract
The present invention provides a kind of production method of semiconductor devices, and the production method includes：Step 1: providing semiconductor substrate；Step 2: forming low k dielectric and the copper interconnection structure in the low k dielectric on the semiconductor substrate；Step 3: the surface that first gas source handles the copper interconnection structure and the low k dielectric is introduced, to form heavy polymer layer；Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；Step 6: deposition forms dielectric capping layers on the boundary layer.According to the method for the present invention, Cu/ dielectric passivation interfacial characteristics can be improved, to improve electromigration characteristic, and then improve the reliability and yields of device.
Description
Technical field
The present invention relates to semiconductor fabrication process more particularly to a kind of production methods of semiconductor devices.
Background technology
With the development of integrated circuit, characteristic size constantly reduces, and the current density that plain conductor is passed through steeply rises；Together
When, the raising of chip integration causes unit area power consumption to increase, and therefore, the reliability of metal connecting line is always IC designs and system
Make major issue of concern.In plain conductor, the electronics and the metal ion that are moved along electric field negative direction carry out momentum-exchange, lead
Metal ion is caused to generate by spreading leading mass transportation, this phenomenon is referred to as electromigration.In the mutual connection of semiconductor devices
Electromigration is important metal failure mechanism in structure.There are two types of failures caused by electromigration, is interconnection line short circuit and open circuit respectively.
With the electromigration of Cu ions, atom loss can occur near cathode, localised tension gradually increases, after reaching critical value,
Cavity will be formed, so as to cause the increase of resistance, eventually leads to interconnection line open circuit.And in anode atom accumulation region, part is pressed
Power constantly increases so that there may be metal protrusion in the region, if the metal of protrusion and the metal interconnection neighbouring with it contact,
It may result in interconnection line short circuit.
Electromigration can have a plurality of diffusion path, such as surface, interface, grain boundary decision, lattice diffusion.Research table in recent years
It is bright, caused by electromigration is mainly the diffusion by Cu/ dielectric overlays bed boundary and the barrier layers Cu/ interface, and Cu/ dielectric overlays
Bed boundary is the most important diffusion path of electromigration, and therefore, Cu/ dielectric overlays bed boundary is for the corresponding electrical property of control and reliably
Property performance be vital, the diffusion phenomena of Cu/ dielectric passivations interface can be inhibited by improving interface performance, changed
Kind electromigration characteristic.Various processing technology of interface are widely used as the method that can improve Cu/ dielectric overlays bed boundary
With research.
Therefore, it is proposed to which a kind of interface processing method that can improve Cu/ dielectric passivation interfacial characteristics, existing to solve
The deficiency of technology.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices,
Including step：
Step 1: providing semiconductor substrate；
Step 2: forming low k dielectric and the copper-connection knot in the low k dielectric on the semiconductor substrate
Structure；
Step 3: the surface that first gas source handles the copper interconnection structure and the low k dielectric is introduced, to form height
Molecular weight polymerized nitride layer, first gas source include hexamethyldisilazane or other containing CH3, N and Si organic polymer
Close object and ammonia；
Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；
Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；
Step 6: deposition forms dielectric capping layers on the boundary layer.
Further, further include being handled on the surface to the copper interconnection structure and the low k dielectric to be formed
Before stating heavy polymer layer, using described in ammonia or nitrogen treatment copper interconnection structure expose top surface the step of.
Further, the first gas source is the mixed gas of hexamethyldisilazane and ammonia.
Further, the first gas source is introduced to soak the surface of the copper interconnection structure and the low k dielectric
Profit and cleaning treatment, to form the heavy polymer layer.
Further, the second gas source is trimethyl silane or tetramethylsilane.
Further, second gas source described in radio frequency processing, with formed can be reacted with the heavy polymer layer etc.
Gas ions.
Further, the interlayer materials are SiCN.
Further, the thickness predetermined value of the boundary layer is 2~5nm.
Further, it is formed with etching stop layer between the low k dielectric and the semiconductor substrate.
Further, the dielectric capping layers material is the silicon nitride of silicon nitride or carbon dope.
Shown in sum up, manufacturing process according to the present invention is using processing technology of interface to the copper interconnection structure and described low
The interface of k dielectric layer is handled, and Cu/ dielectric passivation interfacial characteristics are improved, and to improve electromigration characteristic, and then improves device
Reliability and yields.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 C are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
It is that hexamethyldisilazane is situated between in copper interconnection structure and low k that Fig. 2, which is according to the method for exemplary embodiment of the present,
The schematic diagram of the high molecular polymer formed after adsorption reaction occurs for the surface of electric layer；
Fig. 3 is the covering feelings in copper interconnection structure surface corner boundary layer according to the method for exemplary embodiment of the present
The close-up schematic view of condition；
Fig. 4 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
The present invention manufacturing process using processing technology of interface to the interface of the copper interconnection structure and the low k dielectric at
Reason is to form the coating covered with good turning.Obviously, execution of the invention is not limited to the technology of semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment]
In the following, when A- Fig. 1 C implement copper wiring technique to describe method according to an exemplary embodiment of the present invention referring to Fig.1
The detailed step of coating is formed on copper interconnection layer.
First, as shown in Figure 1A, it illustrates form first copper interconnection layer on a semiconductor substrate 100 according to the prior art
The schematic cross sectional view of device after layer 103.A preferred embodiment according to prior art, using dual damascene process
Form copper interconnection layer 103.
As shown in Figure 1A, semiconductor substrate 100 is provided, the semiconductor substrate 100 may include any semi-conducting material, this
Semi-conducting material may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP and other III-V
Or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate 100 includes various isolation structures, such as shallow trench isolation.Semiconductor substrate
100 can also be including organic semiconductor or such as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator
Layered semiconductor.
Deposition forms etching stop layer 101 on a semiconductor substrate 100, and material is carbon containing silicon nitride (NDC), is prepared
Method can be selected chemical vapor deposition (CVD).As an example, when carrying out chemical vapor deposition, power be 200~
400W, heating make the temperature in cavity to 300~400 DEG C, and the pressure in cavity is 2~5Torr, the trimethyl silane of use
The gas flow of (3MS) or tetramethylsilane (4MS) is 100~200 cc/mins (sccm), the gas flow of He
For 350~450 cc/mins (sccm), NH3Gas flow is 300~500 cc/mins (sccm), when deposition
Between continue 3s.
Then, deposition forms low k dielectric 102 on etching stop layer 101, and dielectric constant k is less than 3, generally use
It is prepared by chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique, material can be silica glass (FSG),
Silica (silicon oxide), carbonaceous material, porous material (porous-like material) or homologue.As
One example, low k dielectric 102 are that porous material includes pore-foaming agent, and pore-foaming agent can be any suitable material for generating hole
Material, porogen material can be hydrocarbon, acrylates (acrylate) race containing resist polymer, fluorinated
Polymer etc..It can cure in a furnace or by other process implementings, such as ultraviolet curing, rapid thermosetting, flash of light
Lamp solidification, laser curing etc..
Etching low k dielectric 102 forms groove to expose semiconductor substrate 100.It is sequentially formed with expansion in the trench
Barrier layer (not shown) and copper metal layer are dissipated, physical vapour deposition (PVD) (PVD), resistance can be selected in the wherein preparation method of diffusion impervious layer
Barrier can be between -40 DEG C~400 DEG C of temperature and about under the pressure of 0.1 millitorr (mTorr)~100 millitorr (mTorr)
It is formed.Diffusion barrier material be metal or metal compound layer material for example tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride,
Titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its constituent.In addition, diffusion impervious layer also may include multiple film layers.It is preferred that
It is initially formed one layer of cobalt (Co) enhancement layer (enhancement layer) (not shown) on diffusion impervious layer, then re-forms copper crystalline substance
Kind layer (not shown).Cobalt enhancement layer can improve the electromigration immunity of copper-connection, can simultaneously be effectively reinforce in smaller geometry
Copper filling capacity in groove/structure.Copper metal layer is formed using electrochemistry electric plating method on copper seed layer, by having
Machine object and inorganic matter water-bath ingredient and the instant analysis of supply can maintain stable electroplating technology, wherein preferred copper is electroplating
The gap filling to 0.07um~0.1um can be completed by learning additive and current waveform.Then, using chemical mechanical grinding
(CMP) process copper metal layer, until exposing low k dielectric 102, makes copper metal layer 103 to remove extra copper metal layer
It is flushed with the top of low k dielectric 102, stops chemical mechanical grinding.
Using ammonia (NH3) or nitrogen plasma treatment copper metal layer 103, the ammonia being passed through or nitrogen reduction interconnection
Copper oxide in structure, the final copper oxide removed in interconnection structure.As an example, using ammonia (NH3) plasma
Copper metal layer is handled, the flow of gas is 200~300 cc/mins (sccm), and reaction room pressure can be 5~10 millis
It holds in the palm (mTorr), power is 900W~1100W, and the time of corona treatment is 5s~10s.
As shown in Figure 1B, hexamethyldisilazane and the mixed gas of ammonia are passed through in reative cell, to the copper metal
The surface of layer and low k dielectric is infiltrated and is cleaned, and Chemisorption occurs on surface, is formed poly- with high molecular weight
Close object.The molecular formula of used hexamethyldisilazane is (CH3)6NHSi2, formed after reacting Fig. 2 shows surface
The schematic diagram of heavy polymer.Wherein, can also CH be contained using similar with hexamethyldisilazane3, N and Si
Organic high molecular compound handles the surface of the copper metal layer and low k dielectric, for example, nine methyl, three silazane, in this hair
Preferred hexamethyldisilazane in bright.
Next, being passed through trimethyl silane (3MS) or tetramethylsilane (4MS) in reative cell, radio frequency (RF) is opened
Power supply, glow discharge are passed through gas ionization into plasma, and plasma and the heavy polymer of generation react life
At SiCN, it is repeatedly alternately repeated above-mentioned two step, there is the SiCN boundary layers 105 of ideal turning covering until generating.As one
The thickness predetermined range of a example, SiCN boundary layers 105 is 2~5nm, is shown at copper interconnection structure surface turning in Fig. 3
105 coverage condition of SiCN boundary layers at 104.As seen from the figure due to the addition of boundary layer, Step Coverage can be improved, especially existed
The covering of corner has clear improvement.
It is believed that the surface used in physical absorption, absorption, absorption or chemisorbing monolayer reactant is inhaled on the surface
Gravitation is self-limited type, this is because since substrate surface has limited a available site of reactant, so introducing gas
Only there are one single layers to be deposited on the surface during body source.Once limited a site is occupied by reactant, then reactant into one
Step deposition will be obstructed.This cycle is repeated to reach the layer of expectation thickness.
Usually, reaction surface is exposed to the time in gas source every time can be in several microseconds to several milliseconds, by several seconds, very
To in the range of a few minutes.Generally, the sufficiently long time should be kept, to for certain volume reactant provide abundance when
Between adsorb/be chemically adsorbed on entire reaction surface, and be formed on compound layer.
As shown in Figure 1 C, the deposit dielectrics coating 106 on SiCN boundary layers 105.The material of dielectric capping layers 106
For the silicon nitride or silicon nitride of carbon dope, preferably SiCN materials.Form the preferred plasma activated chemical vapour deposition of technique of SiCN
Technique, source gas are tetramethylsilane/trimethyl silane, ammonia and nitrogen, and carrier gas is helium.As an example, electricity is situated between
It is 100 angstroms~500 angstroms that matter coating, which has compression, thickness range,.Dielectric capping layers with compression have good attached
Put forth effort, inhibit the diffusion of copper and stronger mechanical structure is provided, also there is higher breakdown voltage, good air-tightness and passivation
Copper metal layer.
With reference to Fig. 4, the flow chart for the step of method according to an exemplary embodiment of the present invention is implemented successively is shown,
Flow for schematically illustrating entire manufacturing process.
In step 401, semiconductor substrate is provided, form low k dielectric on a semiconductor substrate and is located at low k dielectric
In copper interconnection structure；
In step 402, the surface for introducing first gas source processing copper interconnection structure and low k dielectric, to form high score
Sub- weight polymers layer；
In step 403, it introduces second gas source and handles heavy polymer layer, to form boundary layer；
In step 404, it is alternately repeated step 402 and step 403, until the thickness of boundary layer reaches predetermined value；
In step 405, deposition forms dielectric capping layers on boundary layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of production method of semiconductor devices, including：
Step 1: providing semiconductor substrate；
Step 2: forming low k dielectric and the copper interconnection structure in the low k dielectric on the semiconductor substrate；
Step 3: the surface that first gas source handles the copper interconnection structure and the low k dielectric is introduced, to form macromolecule
Weight polymers layer, first gas source include hexamethyldisilazane or other containing CH3, N and Si organic high molecular compound
And ammonia；
Step 4: introducing second gas source handles the heavy polymer layer, to form boundary layer；
Step 5: step 3 and step 4 are alternately repeated, until the thickness of the boundary layer reaches predetermined value；
Step 6: deposition forms dielectric capping layers on the boundary layer.
2. according to the method described in claim 1, it is characterized in that, further including being situated between to the copper interconnection structure and the low k
The surface of electric layer is handled with before forming the heavy polymer layer, mutual using copper described in ammonia or nitrogen treatment
The step of linking the top surface that structure exposes.
3. according to the method described in claim 1, it is characterized in that, the first gas source is hexamethyldisilazane and ammonia
Mixed gas.
4. according to the method described in claim 1, it is characterized in that, introduce the first gas source to the copper interconnection structure and
The surface of the low k dielectric carries out infiltration and cleaning treatment, to form the heavy polymer layer.
5. according to the method described in claim 1, it is characterized in that, the second gas source is trimethyl silane or tetramethyl
Silane.
6. according to the method described in claim 1, it is characterized in that, second gas source described in radio frequency processing, with formed can be with institute
State the plasma of heavy polymer layer reaction.
7. according to the method described in claim 1, it is characterized in that, the interlayer materials are SiCN.
8. according to the method described in claim 1, it is characterized in that, the thickness predetermined value of the boundary layer is 2~5nm.
9. according to the method described in claim 1, it is characterized in that, shape between the low k dielectric and the semiconductor substrate
At there is etching stop layer.
10. according to the method described in claim 1, it is characterized in that, the dielectric capping layers material is silicon nitride or mixes
The silicon nitride of carbon.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN104835778A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007022621B4 (en) * | 2007-05-15 | 2017-06-01 | Advanced Micro Devices Inc. | A method of making a dielectric overcoat for copper metallization using a hydrogen-based thermal-chemical treatment |
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- 2014-10-11 CN CN201410534793.5A patent/CN105575881B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN104835778A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
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