CN105575881A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105575881A CN105575881A CN201410534793.5A CN201410534793A CN105575881A CN 105575881 A CN105575881 A CN 105575881A CN 201410534793 A CN201410534793 A CN 201410534793A CN 105575881 A CN105575881 A CN 105575881A
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Abstract
The invention provides a semiconductor device manufacturing method which comprises the steps of a first step, providing a semiconductor substrate; a second step, forming a low-k dielectric layer and a copper interconnection structure in the low-k dielectric layer on the semiconductor substrate; a third step, inputting a first gas source for processing the surfaces of the copper interconnection structure and the low-k dielectric layer, thereby forming a high-molecular-weight polymer layer; a fourth step, inputting a second gas source for processing the high-molecular-weight polymer layer for forming an interfacial layer; a fifth step, alternatively repeating the third step and the fourth step until the thickness of the interfacial layer reaches a preset value; and a sixth step, depositing on the interfacial layer for forming a dielectric covered layer. The semiconductor device manufacturing method according to the invention has advantages of improving the interface characteristic of a Cu/dielectric covered layer, improving electromigration characteristic, and furthermore improving reliability and yield of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
Along with the development of integrated circuit, characteristic size constantly reduces, and the current density that plain conductor passes into sharply rises; Meanwhile, the raising of chip integration causes unit are power consumption to increase, and therefore, the reliability of metal connecting line is the major issue that IC Design and manufacture is concerned about always.In plain conductor, the electronics moved in the other direction along electric field and metal ion carry out momentum interchange, and cause metal ion to produce by the leading mass transportation of diffusion, this phenomenon is called as electromigration.In the interconnection structure of semiconductor device, electromigration is important metal failure mechanism.The inefficacy that electromigration causes has two kinds, is interconnection line short circuit and open circuit respectively.Along with the electromigration of Cu ion, near negative electrode, atom loss can occur, localised tension increases gradually, after reaching critical value, will form cavity, thus cause the increase of resistance, finally cause interconnection line to be opened a way.And in anode atom accumulation region, local pressure constantly increases, make to have in this region metal to protrude, if the metal protruded and contiguous metal interconnectedly contacting with it, interconnection line short circuit will be caused.
Electromigration can have many evolving paths, as surface, interface, grain boundary decision, lattice diffusion.Research in recent years shows, electromigration is mainly caused by the diffusion of Cu/ dielectric overlay bed boundary and interface, Cu/ barrier layer, and Cu/ dielectric overlay bed boundary is the topmost the evolving path of electromigration, therefore, Cu/ dielectric overlay bed boundary is vital for the corresponding electrical property of control and reliability performance, the diffusion phenomena of Cu/ dielectric passivation interface can be suppressed by improving interface performance, improving electromigration characteristic.Various processing technology of interface is widely used and research as the method can improving Cu/ dielectric overlay bed boundary.
Therefore, a kind of interface processing method that can improve Cu/ dielectric passivation interfacial characteristics is proposed, to solve the deficiencies in the prior art.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device,
Comprise step:
Step one, provide Semiconductor substrate;
Step 2, form low k dielectric and be arranged in the copper interconnection structure of described low k dielectric on the semiconductor substrate;
Step 3, introduce the surface of copper interconnection structure and described low k dielectric described in the first gas source process, to form heavy polymer layer;
Step 4, introduce heavy polymer layer described in the second gas source process, to form boundary layer;
Step 5, alternately repetition step 3 and step 4, until the thickness of described boundary layer reaches predetermined value;
Step 6, on described boundary layer deposition formed dielectric capping layers.
Further, be also included in before the surface of described copper interconnection structure and described low k dielectric processed to form described heavy polymer, adopt the step of the end face that copper interconnection structure exposes described in ammonia or nitrogen treatment.
Further, described first gas source is the mist of hexamethyldisiloxane and ammonia.
Further, introduce the surface of described first gas source to described copper interconnection structure and described low k dielectric and infiltrate and clean, to form described heavy polymer layer.
Further, described second gas source is trimethyl silane or tetramethylsilane.
Further, the second gas source described in radio frequency processing, to form the plasma that can react with described heavy polymer.
Further, described interlayer materials is SiCN.
Further, the thickness predetermined value of described boundary layer is 2 ~ 5nm.
Further, etching stop layer is formed with between dielectric layer and described Semiconductor substrate between described low k layer.
Further, described dielectric capping layers material is the silicon nitride of silicon nitride or carbon dope.
To sum up, the interface of processing technology of interface to described copper interconnection structure and described low k dielectric is adopted to process according to manufacturing process of the present invention, improve Cu/ dielectric passivation interfacial characteristics, to improve electromigration characteristic, and then improve reliability and the yields of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 C obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 is the schematic diagram of the method high molecular polymer that to be hexamethyldisiloxane formed after adsorption reaction occurs on the surface of copper interconnection structure and low k dielectric according to an exemplary embodiment of the present invention;
Fig. 3 be according to an exemplary embodiment of the present invention method at the close-up schematic view of the coverage condition of copper interconnection structure surface corner boundary layer;
Fig. 4 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, propose detailed step by following description, so that the manufacturing process of the present invention explaining the present invention's proposition adopts processing technology of interface, the interface to described copper interconnection structure and described low k dielectric processes to be formed the cover layer having good turning and cover.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, reference Figure 1A-Fig. 1 C describes when method implements copper wiring technique according to an exemplary embodiment of the present invention on copper interconnection layer, forms tectal detailed step.
First, as shown in Figure 1A, it illustrates the schematic cross sectional view forming the device after first copper interconnection layer layer 103 according to prior art on a semiconductor substrate 100.According to a preferred embodiment of prior art, dual damascene process is adopted to form copper interconnection layer 103.
As shown in Figure 1A, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate 100 comprises various isolation structure, such as shallow trench isolation.Semiconductor substrate 100 can also comprise organic semiconductor or the layered semiconductor as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator.
Deposition forms etching stop layer 101 on a semiconductor substrate 100, and its material is the silicon nitride (NDC) of carbon containing, and the method for preparation can select chemical vapour deposition (CVD) (CVD).As an example, when carrying out chemical vapour deposition (CVD), power is 200 ~ 400W, heating makes temperature to 300 ~ 400 DEG C in cavity, pressure in cavity is 2 ~ 5Torr, the trimethyl silane (3MS) adopted or the gas flow of tetramethylsilane (4MS) are the gas flow of 100 ~ 200 cc/min (sccm), He is 350 ~ 450 cc/min (sccm), NH
3gas flow is 300 ~ 500 cc/min (sccm), and sedimentation time continues 3s.
Then, on etching stop layer 101, deposition forms low k dielectric 102, its dielectric constant k is less than 3, usual employing chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique preparation, its material can be silex glass (FSG), silica (siliconoxide), carbonaceous material, porous material (porous-likematerial) or homologue.As an example, low k dielectric 102 includes pore-foaming agent for porous material, pore-foaming agent can be the material in any suitable generation hole, and porogen material can be hydrocarbon, the polymer of acrylates (acrylate) race containing resist, the polymer etc. fluoridized.Can solidify in a furnace or by other process implementings, such as ultraviolet curing, rapid thermosetting, photoflash lamp solidification, laser curing etc.
Etching low k dielectric 102, to expose Semiconductor substrate 100, forms groove.Be formed with diffusion impervious layer (not shown) and copper metal layer successively in the trench, wherein the preparation method of diffusion impervious layer can select physical vapour deposition (PVD) (PVD), barrier layer can between-40 DEG C ~ 400 DEG C temperature with about formed under the pressure of 0.1 millitorr (mTorr) ~ 100 millitorr (mTorr).Diffusion barrier material is material such as tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its constituent of metal or metal compound layer.In addition, diffusion impervious layer also may comprise multiple rete.Preferably first form one deck cobalt (Co) enhancement layer (enhancementlayer) (not shown) on the diffusion barrier, and then form copper crystal seed layer (not shown).Cobalt enhancement layer can improve the electromigration immunity of copper-connection, effectively can strengthen the copper filling capacity in less geometry groove/structure simultaneously.Copper crystal seed layer use electrochemistry electric plating method form copper metal layer, by maintaining stable electroplating technology to the instant analysis of organic substance and inorganic matter water-bath composition and supply, wherein preferred copper electroplating chemical additive and current waveform can complete the gap-fill to 0.07um ~ 0.1um.Then, adopt cmp (CMP) PROCESS FOR TREATMENT copper metal layer, to remove unnecessary copper metal layer, until expose low k dielectric 102, copper metal layer 103 is flushed with the top of low k dielectric 102, stops cmp.
Adopt ammonia (NH
3) or nitrogen plasma treatment copper metal layer 103, the cupric oxide that the ammonia passed into or nitrogen reduce in interconnection structure, the final cupric oxide removed in interconnection structure.As an example, adopt ammonia (NH
3) plasma treatment copper metal layer, the flow of gas is 200 ~ 300 cc/min (sccm), reative cell internal pressure can be 5 ~ 10 millitorrs (mTorr), and power is 900W ~ 1100W, and the time of plasma treatment is 5s ~ 10s.
As shown in Figure 1B, in reative cell, pass into the mist of hexamethyldisiloxane and ammonia, the surface of described copper metal layer and low k dielectric is infiltrated and cleaned, on surface, Chemisorption occurs, form the polymer with HMW.The molecular formula of the hexamethyldisiloxane adopted is (CH
3)
6nHSi
2, Fig. 2 shows the schematic diagram of the heavy polymer formed after surface reacts.Wherein, can also adopt similar containing CH with hexamethyldisiloxane
3, N and Si organic high molecular compound process described in the surface of copper metal layer and low k dielectric, such as, nine methyl three silazane, in the present invention preferred hexamethyldisiloxane.
Next, trimethyl silane (3MS) or tetramethylsilane (4MS) is passed in reative cell, open radio frequency (RF) power supply, glow discharge, pass into gas ionization and become plasma, the plasma produced and heavy polymer react and generate SiCN, repeatedly alternately repeat above-mentioned two steps, until generate the SiCN boundary layer 105 having desirable turning and cover.As an example, the thickness predetermined range of SiCN boundary layer 105 is illustrated in 2 ~ 5nm, Fig. 3 at turning 104, copper interconnection structure surface place SiCN boundary layer 105 coverage condition.Adding as seen from the figure due to boundary layer, can improve Step Coverage, covering especially around the corner has clear improvement.
We believe that physical absorption from the teeth outwards, absorption, absorption or chemisorbing monolayer reactant physical attractiveness used is self-limited type, this is because there is limited the available site of reactant due to substrate surface, so only have an individual layer to be deposited on the surface during introducing gas source.Once limited site is occupied by reactant, then the further deposition of reactant will be obstructed.This circulation can be repeated and reach the layer expecting thickness.
Usually, the time in gas source of being at every turn exposed to by reaction surface can in a few microsecond to several milliseconds, by several seconds, even in the scope of a few minutes.Generally, the sufficiently long time should be kept, thus provide the sufficient time to adsorb/be chemically adsorbed on whole reaction surface for the reactant of certain volume, and form compound layer thereon.
As shown in Figure 1 C, deposit dielectrics cover layer 106 on SiCN boundary layer 105.The material of dielectric capping layers 106 is silicon nitride or the silicon nitride of carbon dope, preferred SiCN material.Form the optimal process plasma activated chemical vapour deposition technique of SiCN, its source gas is tetramethylsilane/trimethyl silane, ammonia and nitrogen, and carrier gas is helium.As an example, dielectric capping layers has compression, and thickness range is 100 dust ~ 500 dusts.The dielectric capping layers with compression has good adhesive force, suppresses the diffusion of copper and provide stronger mechanical structure, also has higher puncture voltage, good air-tightness and passivation copper metal layer.
With reference to Fig. 4, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 401, provide Semiconductor substrate, form low k dielectric and the copper interconnection structure being arranged in low k dielectric on a semiconductor substrate;
In step 402, introduce the surface of the first gas source process copper interconnection structure and low k dielectric, to form heavy polymer layer;
In step 403, the second gas source process heavy polymer layer is introduced, to form boundary layer;
In step 404, alternately step 402 and step 403 is repeated, until the thickness of boundary layer reaches predetermined value;
In step 405, on boundary layer, deposition forms dielectric capping layers.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Step one, provide Semiconductor substrate;
Step 2, form low k dielectric and be arranged in the copper interconnection structure of described low k dielectric on the semiconductor substrate;
Step 3, introduce the surface of copper interconnection structure and described low k dielectric described in the first gas source process, to form heavy polymer layer;
Step 4, introduce heavy polymer layer described in the second gas source process, to form boundary layer;
Step 5, alternately repetition step 3 and step 4, until the thickness of described boundary layer reaches predetermined value;
Step 6, on described boundary layer deposition formed dielectric capping layers.
2. method according to claim 1, it is characterized in that, also be included in before the surface of described copper interconnection structure and described low k dielectric processed to form described heavy polymer, adopt the step of the end face that copper interconnection structure exposes described in ammonia or nitrogen treatment.
3. method according to claim 1, is characterized in that, described first gas source is the mist of hexamethyldisiloxane and ammonia.
4. method according to claim 1, is characterized in that, introduces the surface of described first gas source to described copper interconnection structure and described low k dielectric and infiltrates and clean, to form described heavy polymer layer.
5. method according to claim 1, is characterized in that, described second gas source is trimethyl silane or tetramethylsilane.
6. method according to claim 1, is characterized in that, the second gas source described in radio frequency processing, to form the plasma that can react with described heavy polymer.
7. method according to claim 1, is characterized in that, described interlayer materials is SiCN.
8. method according to claim 1, is characterized in that, the thickness predetermined value of described boundary layer is 2 ~ 5nm.
9. method according to claim 1, is characterized in that, is formed with etching stop layer between described low k layer between dielectric layer and described Semiconductor substrate.
10. method according to claim 1, is characterized in that, described dielectric capping layers material is the silicon nitride of silicon nitride or carbon dope.
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| US20080286966A1 (en) * | 2007-05-15 | 2008-11-20 | Joerg Hohage | Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment |
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN104835778A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
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2014
- 2014-10-11 CN CN201410534793.5A patent/CN105575881B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101326630A (en) * | 2005-12-07 | 2008-12-17 | Nxp股份有限公司 | A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device |
| CN101681873A (en) * | 2007-01-31 | 2010-03-24 | 先进微装置公司 | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
| US20080286966A1 (en) * | 2007-05-15 | 2008-11-20 | Joerg Hohage | Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment |
| CN103187266A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Etching stop layer and forming method of copper-connection |
| CN104835778A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
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