KR20080072149A - Liquid crystal display device - Google Patents

Abstract

An LCD device is provided to build a driving IC in an LCD panel while driving the LCD panel with a single driving IC, thereby reducing cost and minimizing the thickness of the LCD device. An LCD(Liquid Crystal Display) device includes an LCD panel(100), an internal gate circuit(120), and a driving IC(Integrated Circuit)(130). The LCD panel is formed in each area defined by n gate lines(GL) and m data lines(DL). Three colors are repeatedly disposed in a data line direction in the LCD panel. The LCD panel has plural pixels(110) that the same color is disposed in a gate line direction. The internal gate circuit is formed in the LCD panel to supply a gate on voltage to the gate lines. The driving IC is built in the LCD panel to drive the internal gate circuit, and inverts the polarity of an image signal in a data line unit and at least three gate line units to supply the inverted image signal to the data lines.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram schematically illustrating the driving integrated circuit shown in FIG. 1. FIG.

3 is a waveform diagram illustrating a driving waveform of a liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B illustrate polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to an exemplary embodiment of the present invention.

5A and 5B are diagrams illustrating polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to another exemplary embodiment of the present invention.

6A and 6B illustrate polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to still another exemplary embodiment of the present invention.

7A and 7B illustrate polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to another exemplary embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

100: liquid crystal panel 102: lower substrate

104: upper substrate 110: pixel cell

112: thin film transistor 114: pixel electrode

120: embedded circuit circuit 130: drive integrated circuit

200: flexible printed circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing manufacturing costs and preventing deterioration in image quality due to uncharged pixel cells.

In general, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

To this end, a liquid crystal display device includes a liquid crystal panel including liquid crystal cells injected between two glass substrates, liquid crystal cells arranged in a matrix form, and switch elements for switching signals supplied to the liquid crystal cells, and a liquid crystal panel. A driving circuit unit for driving and a back light unit for irradiating light to the liquid crystal panel is configured.

Recently, a thin, light and inexpensive liquid crystal display device has been developed by reducing the number of signal lines or circuit components of a liquid crystal panel. Accordingly, Korean Patent Laid-Open Publication No. 2003-39972 proposes a liquid crystal display device without a flexible printed circuit board and a gate printed circuit board, which can reduce the number of parts to reduce size and manufacturing terminals.

However, a liquid crystal display device without a flexible printed circuit board and a gate printed circuit board includes a plurality of data and gate driver integrated circuits and a data printed circuit board, thereby limiting size and manufacturing cost. There is a high problem.

Accordingly, in order to solve the above problems, the present invention is to provide a liquid crystal display device that can reduce the manufacturing cost and prevent the deterioration of the image quality due to the uncharged pixel cells.

According to an exemplary embodiment of the present invention, a liquid crystal display device is formed for each region defined by n gate lines and m data lines, and three colors are repeatedly arranged in the direction of the data line. And a liquid crystal panel having a plurality of pixel cells having the same color disposed in the direction of the gate line, a gate embedded circuit formed on the liquid crystal panel to supply gate-on voltage to the gate lines, and mounted on the liquid crystal panel. And a driving integrated circuit for driving the gate embedded circuit and inverting the polarity of the image signal in units of the data line and at least three gate lines to supply the data lines.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal panel in which pixel cells are formed in regions defined by n gate lines and m data lines, and a gate-on voltage is formed on the liquid crystal panel. A gate integrated circuit to be supplied and a driving integrated circuit mounted on the liquid crystal panel to drive the gate embedded circuit and to supply image signals of different colors to the data line in horizontal lines corresponding to the direction of the gate line. And the driving integrated circuit inverts the polarity of the image signal in units of the data line and at least three gate lines.

The pixel cells may be repeatedly arranged in three colors in the direction of the data line, and the three adjacent pixel cells constitute one unit pixel.

The pixel cell may be configured to include a pixel electrode having a short side length parallel to the data line and a shorter side length parallel to the gate line.

The driving integrated circuit may include a signal relay unit for relaying an input source data signal and a synchronization signal, a first power generator for generating a first power source, and a second power source for generating a second power source using the first power source. Arranging a generation unit, a common voltage generation unit supplying a common voltage to the liquid crystal panel using the second power supply, and a source data signal supplied from the signal relay unit to be suitable for driving the liquid crystal panel. A signal controller for controlling the inside of a driving integrated circuit, a control signal generator for generating a gate driving signal and a data control signal for driving the gate embedded circuit using a synchronization signal supplied through the signal controller, A boosting circuit for boosting the voltage level of the gate driving signal by using a power supply to supply the gate embedded circuit; A gradation voltage generation unit for generating a plurality of gradation voltages using a circle, and a data conversion for converting the sorted data signal supplied from the signal controller using the plural gradation voltages into the image signal according to the data control signal. Characterized in that it comprises a part.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention is formed for each region defined by the plurality of data lines DL and the gate lines GL, and is formed in the direction (vertical direction) of the data line. The liquid crystal panel 100 includes a plurality of pixel cells 110 in which the colors are repeatedly arranged and the same color is arranged in the direction of the gate line (horizontal direction), and the gate lines GL are formed on the liquid crystal panel 100. Gate integrated circuit 120 driving the gate embedded circuit 120 and driving integrated circuit 130 mounted on the liquid crystal panel 100 to drive the gate embedded circuit 120 and supply image signals to the data lines DL. And a flexible printed circuit 200 attached to the liquid crystal panel 100 and connecting the liquid crystal panel 100 to an external driving system (not shown).

The liquid crystal panel 100 includes a lower substrate 102 and an upper substrate 104 bonded together to face each other, a spacer (not shown) for maintaining a constant cell gap between the two substrates 102 and 104, and a spacer. It is configured to include a liquid crystal layer (not shown) filled in the liquid crystal space provided.

The lower substrate 102 includes a display area corresponding to the upper substrate 104 and a non-display area excluding the display area.

In the display area of the lower substrate 102, a plurality of data lines DL formed in parallel in the first direction to have a predetermined distance, and a plurality of data lines DL formed in parallel in the second direction crossing the first direction to have a predetermined distance. And a pixel cell 110 formed in each region defined by the gate line GL and the plurality of data lines DL and the gate lines GL. In this case, the data lines DL to which the image signal is supplied are formed to have a smaller number than the gate lines GL to which the gate on voltage is supplied.

Each of the pixel cells 110 includes a thin film transistor 112 connected to a gate line GL and a data line DL, and a pixel electrode 114 connected to the thin film transistor 112.

The thin film transistor 112 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the pixel electrode 114. Accordingly, each of the thin film transistors 112 is switched according to the gate-on voltage supplied to the gate line GL to supply an image signal from each data line DL to each pixel electrode 114.

The length of the short side parallel to the data line DL is formed to be shorter than the long side parallel to the gate line GL. Accordingly, the pixel electrode 114 has a horizontal stripe shape.

The gate embedded circuit 120 connected to each of the plurality of gate lines GL is formed in the non-display area of the lower substrate 102, and the driving integrated circuit 130 is mounted.

The upper substrate 104 includes a color filter, a common electrode, a light shielding layer, and the like. The common electrode may be formed on the lower substrate 102 according to the liquid crystal formed in the liquid crystal layer.

In the color filter, a red (R) color filter, a green (G) color filter, and a blue (B) color filter are repeatedly formed in the direction of the data line DL and have the same color along the direction of the gate line GL. do.

The common electrode may be formed on the entire surface of the upper substrate 104 to face the pixel electrode 114 to form a vertical electric field in the liquid crystal layer, or may be formed in a line shape. The common electrode may be formed on the lower substrate 102 to be parallel to the pixel electrode 114 to form a horizontal electric field in the liquid crystal layer.

The light blocking layer is formed on the upper substrate 104 to overlap the remaining region except for the opening region overlapping the pixel electrode 114.

The pixel cells of red (R), green (G), and blue (B) on which the red (R) color filter, the green (G) color filter, and the blue (B) color filter are formed, respectively, display one color image. Constitute a unit pixel.

The flexible printed circuit 200 is provided in the non-display area of the lower substrate 102 and attached to the pad portion. The flexible printed circuit 200 transmits the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the driving system to the driving integrated circuit 130.

The driving integrated circuit 130 is mounted on an integrated circuit mounting unit in which a plurality of input / output pads are formed in a non-display area of the lower substrate 102. Accordingly, each of the plurality of input / output bumps provided in the driving integrated circuit 130 is mounted to be electrically connected to each of the input / output pads of the integrated circuit mounting unit.

The driving integrated circuit 130 uses one of the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the flexible printed circuit 200 to determine one horizontal section corresponding to one period of the horizontal synchronization signal Hsync. A gate driving signal and a data control signal for driving by dividing into first to third sub-sections are generated.

In addition, the driving integrated circuit 130 aligns the source data signal Data with the red data R, the green data G, and the blue data B corresponding to each of the first to third sub-sections, and then the analog signal. The image signal is converted into an in-image signal and supplied to the data lines DL. At this time, the polarity of the image signal is inverted in units of data lines and at least three gate lines and inverted in units of frames.

To this end, the driving integrated circuit 130 may include the signal relay 310, the first power generator 320, the clock generator 322, the reference voltage setting unit 324, and the second as shown in FIG. 2. The power generator 326, the common voltage generator 328, the signal controller 330, the control signal generator 340, the booster circuit 350, the gray voltage generator 360, and the data converter 380 It is configured to include.

The signal relay 310 relays the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the flexible printed circuit 200 to the signal controller 330.

The clock generator 322 generates a clock for driving the first and second power generators 320 and 326.

The first power generator 320 uses the input power Vin supplied from the flexible printed circuit 200 to generate a first power, that is, a first and second reference according to a clock supplied from the clock generator 322. Generate voltages VSP and VSN. In this case, the passive elements such as the resistor 210, the capacitor 220, and the inductor 220 mounted on the flexible printed circuit 200 may be connected to the first power generator 320 through the power signal lines 321a, 321b, and 321c. ) Is used to bias the first and second reference voltages VSP and VSN generated by the first power generator 320 or to set an option function of the driving integrated circuit 130.

The second power generator 326 may generate a second power source, ie, a second power source, required to drive the liquid crystal panel 100 using the first and second reference voltages VSP and VSN generated by the first power generator 320. The first and second driving voltages Vdd and Vss, the integrated circuit driving voltage Vcc, the gate on voltage Von, and the gate off voltage Voff are generated.

The reference voltage setting unit 324 sets the levels of the first and second reference voltages VSP and VSN supplied from the first power generator 320 to the gray voltage generator 360.

The common voltage generator 328 uses the first and second driving voltages Vdd and Vss supplied from the second power generator 326 through the passive element of the flexible printed circuit 200 to form the liquid crystal panel 100. Generates a common voltage to be supplied to the common electrode. In this case, the flexible printed circuit 200 may include a common voltage variable part (not shown) for varying the common voltage Vcom generated by the common voltage generator 328 using at least one of a resistor and a capacitor (not shown). It is configured to include.

The signal controller 330 controls driving of the signal relay 310 and controls internal circuit blocks of the driving integrated circuit 130.

The signal controller 330 supplies the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the signal relay 310 to the control signal generator 340.

The signal controller 330 may transmit the red data R, the green data G, and the blue color so that the source data signal Data of one horizontal section supplied from the signal relay 310 corresponds to each of the first to third sub-sections. Sort by data (B). The signal controller 330 supplies the red data R arranged during the first subdivision of one horizontal section to the data converter 380 and the green data G arranged during the second subdivision of one horizontal section. ) Is supplied to the data converter 380, and blue data B aligned during the third sub-section of one horizontal section is supplied to the data converter 380.

The control signal generator 340 uses the at least one of the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the signal controller 330 to control the data control signals DST, DSC, DOE, and DPS and the gate driving signal ( RVst, RCLK1 to RCLKi).

The data control signals DST, DSC, DOE, and DPS include a data start signal DST, a data shift clock DSC, a data output signal DOE, and a data polarity signal for controlling the data converter 380. DPS). Here, the control signal generator 340 inverts the polarity of the image signal in units of adjacent data lines DL and three gate lines, and also generates a data polarity signal DPS for inverting in units of frames.

The gate driving signals RVst and RCLK1 to RCLKi include the gate start signal RVst for driving the gate embedded circuit 120 and the first to i th clock signals RCLK1 to RCLKi. At this time, each of the first to i th clock signals RCLK1 to RCLKi is sequentially delayed in phase so as to have a pulse width for turning on the thin film transistor in each sub-section. In addition, the first to i th clock signals RCLK1 to RCLKi may be any one of two phases, four phases, six phases, eight phases, and ten phases, depending on the gate embedded circuit 120.

The booster circuit 350 is provided with the gate driving signals RVst and RCLK1 supplied from the control signal generator 340 using the gate-on voltage Von and the gate-off voltage Voff supplied from the second power generator 326. To the voltage level of RCLKi). Here, the gate on voltage Von is a voltage for turning on the thin film transistor 112 of each pixel cell 110, and the gate off voltage Voff is a voltage for turning off the thin film transistor 112. . The booster circuit 350 supplies the boosted gate drive signals Vst and CLK1 to CLKi to the gate embedded circuit 120 through the gate drive signal transmission line 140 formed in the non-display area of the lower substrate 102. do.

The gray voltage generator 360 divides the first and second reference voltages VSP and VSN supplied from the first power generator 320 to generate a plurality of gray voltages, and supplies them to the data converter 380. . Here, the plurality of gray voltages generate 2 ^N gray voltages of positive polarity (+) and gray voltages of negative polarity (−) when the source data signal Data is N bits.

The data converter 380 includes a shift register 381, a latch 383, a digital-analog converter 385, a buffer 387, and a selector 389.

The shift register 381 sequentially shifts the data start signal DST according to the data shift clock DSC supplied from the control signal generator 340 to generate the shift signal SS. In this case, the shift register 381 may be a bidirectional shift register driven in both directions according to the direction signal supplied from the signal controller 330.

The latch unit 383 sequentially latches data RGB of one sub-section supplied from the signal controller 330 according to the shift signal SS supplied from the shift register 381. The latch unit 383 supplies the data RData of one sub-section latched according to the data output signal DOE supplied from the control signal generator 340 to the digital-analog converter 385.

The digital-analog converter 385 analogizes the latched data RData supplied from the latch unit 383 using the plurality of positive and negative gray voltages supplied from the gray voltage generator 360. The signal is converted into positive and negative image signals PVS and NVS as signals. At this time, the digital-analog converter 385 selects one gray voltage corresponding to the gray value of the data RData latched from the plurality of positive gray voltages as the positive image signal PVS and at the same time a plurality of gray level voltages. One gray voltage corresponding to the gray value of the data RData latched in the negative gray voltages is selected as the negative image signal NVS.

The buffer unit 387 uses the first and second driving voltages Vdd and Vss supplied from the first power generator 320 to the passive element of the flexible printed circuit 200 to form a positive and negative image. Each of the signals PVS and NVS is buffered. At this time, the buffer unit 387 amplifies and outputs each of the positive and negative image signals PVS and NVS in consideration of the load of the data line DL.

The selector 389 selects the positive or negative image signals PVS and NVS supplied from the buffer unit 387 according to the data polarity signal DPS supplied from the control signal generator 340 to output each output channel. The data lines DL are supplied to the data lines DL. At this time, the polarity of the image signal selected and output by the selection unit 389 is inverted in accordance with the data polarity signal DPS.

In FIG. 1, the gate embedded circuit 120 is formed in the non-display area of the lower substrate 102 to be connected to each of the plurality of gate lines GL together with the process of forming the thin film transistor 112. The gate embedded circuit 120 generates a gate-on voltage for each sub-section according to the boosted gate driving signals Vst and CLK1 to CLKi supplied from the driver integrated circuit 130, and sequentially generates the gate-on voltage to the gate lines GL. To supply. In this case, the driving integrated circuit 130 receives the gate driving signals Vst and CLK1 to CLKi boosted through the plurality of gate driving signal transmission lines 140 formed in the non-display area of the lower substrate 102. Is supplied.

3 is a waveform diagram illustrating a driving waveform of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3 and FIG. 1, the driving of the liquid crystal display according to the exemplary embodiment of the present invention will be described.

First, in the first sub-section of the first horizontal section, a red image signal R + having a positive polarity (+) is applied to each of the data lines DL so that the gate-on voltage is supplied to the first gate line GL1. Supplied. Accordingly, each pixel cell 110 of the first horizontal line displays a red image corresponding to the positive red image signal R +.

Next, in the second sub-section of the first horizontal section, the positive green image signal G + is supplied to each of the data lines DL to be synchronized with the supply of the gate-on voltage to the second gate line GL2. Accordingly, each pixel cell 110 of the second horizontal line displays a green image corresponding to the positive green image signal G +.

Subsequently, in the third sub-section of the first horizontal section, the positive blue image signal B + is supplied to each of the data lines DL to be synchronized with the supply of the gate-on voltage to the third gate line GL3. Accordingly, each pixel cell 110 of the third horizontal line displays a blue image corresponding to the positive blue image signal B +.

In the first horizontal section divided into the first to third subdivisions, one color image is displayed by mixing red, green, and blue images sequentially by each subdivision.

In the first sub-section of the second horizontal section, the red image signal R- of negative polarity (-) is supplied to each of the data lines DL so as to be synchronized with the supply of the gate-on voltage to the fourth gate line GL4. . Accordingly, each pixel cell 110 of the fourth horizontal line displays a red image corresponding to the negative red image signal R−.

Subsequently, in the second sub-section of the second horizontal section, the negative green image signal G- is supplied to each of the data lines DL so as to be synchronized with the supply of the gate-on voltage to the fifth gate line GL5. . Accordingly, each pixel cell 110 of the fifth horizontal line displays a green image corresponding to the negative green image signal G-.

Next, in the third sub-section of the second horizontal section, the negative blue image signal B− is supplied to each of the data lines DL so as to be synchronized with the supply of the gate-on voltage to the sixth gate line GL6. Accordingly, each pixel cell 110 of the sixth horizontal line displays a blue image corresponding to the negative blue image signal B−.

In the second horizontal section divided into the first to third subdivisions, one color image is displayed by sequentially mixing red, green, and blue images by each subdivision.

Similarly, one color image is displayed on each pixel cell of each horizontal section after the second horizontal section in the same manner as the first and second horizontal sections described above. Then, in the next frame and as described above, the polarity of the image signal is reversed.

As a result, the polarity pattern of the image signal supplied to each pixel cell 110 of the liquid crystal panel 100 during N frames is inverted in units of adjacent data lines and inverted in units of three gate lines as shown in FIG. 4A. .

In addition, since the data polarity signal DPS is inverted in the N + 1 frame, the polarity pattern of the image signal supplied to each pixel cell 110 of the liquid crystal panel 100 is equal to the polarity pattern of the N frame as shown in FIG. 4B. Inverted form.

Accordingly, the liquid crystal display according to the exemplary embodiment of the present invention can drive the liquid crystal panel with one driving integrated circuit and reduce the unit cost by minimizing the thickness of the liquid crystal display by embedding the driving integrated circuit in the liquid crystal panel. have. In addition, the liquid crystal display according to the exemplary embodiment of the present invention minimizes the polarity change of the image signal by reversing the polarity of the image signal in units of data lines and three gate lines (unit pixel units), thereby securing the charging time of the image signal. You can improve the picture quality.

5A and 5B are diagrams illustrating polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to another exemplary embodiment of the present invention.

5A and 5B are combined with FIG. 1, the liquid crystal display according to another exemplary embodiment has the same configuration except for the polar pattern of the image signal displayed on the liquid crystal panel. The description will be replaced by the above description.

That is, the driving integrated circuit 130 of the liquid crystal display according to another exemplary embodiment of the present invention inverts the polarity of the image signal in units of the data line DL and the four gate lines GL to each data line DL. Supply. Accordingly, the liquid crystal display according to another exemplary embodiment may improve the image quality by minimizing the polarity change of the image signal to further secure the charging time of the image signal.

6A and 6B are diagrams illustrating polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to still another exemplary embodiment of the present invention.

6A and 6B are combined with FIG. 1, the liquid crystal display according to another exemplary embodiment has the same configuration except for the polar pattern of the image signal displayed on the liquid crystal panel. Description of the above will be replaced by the above description.

That is, the driving integrated circuit 130 of the liquid crystal display according to an exemplary embodiment of the present invention inverts the polarity of the image signal by the data line DL and the half of the n gate lines by n / 2. It is supplied to the data line DL. Therefore, the liquid crystal display according to the exemplary embodiment of the present invention changes the polarity of the image signal by the data line DL and the half of the n gate lines (n / 2) to further improve the charging time of the image signal. The image quality can be improved by securing it.

7A and 7B are diagrams illustrating polar patterns of image signals displayed on a liquid crystal panel in a liquid crystal display according to another exemplary embodiment.

7A and 7B are combined with FIG. 1, the liquid crystal display according to another exemplary embodiment has the same configuration except for the polar pattern of the image signal displayed on the liquid crystal panel. The description will be replaced by the above description.

That is, the driving integrated circuit 130 of the liquid crystal display according to another exemplary embodiment of the present invention inverts the polarity of the image signal in the data line DL unit and the frame unit and supplies the reversed polarity of the image signal to each data line DL. Accordingly, the liquid crystal display according to another exemplary embodiment may improve the image quality by securing the charging time of the image signal by changing the polarity of the image signal in units of data lines DL and frames.

As a result, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel in which one driving integrated circuit is integrated, and inverts the polarity of the image signal in units of data lines and at least three gate lines using the driving integrated circuit. As a result, the manufacturing cost can be reduced and the image quality deterioration due to the uncharged pixel cell can be prevented.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those skilled in the art.

The liquid crystal display according to the exemplary embodiment of the present invention as described above provides the following effects.

First, by driving the liquid crystal panel with one driving integrated circuit and by embedding the driving integrated circuit in the liquid crystal panel, the unit cost can be reduced and the thickness of the liquid crystal display device can be minimized.

Second, power consumption can be reduced by reversing the polarity of the image signal in units of data lines and at least three gate lines, and the image quality can be improved by securing the charging time of the pixel cells.

Third, the number of data lines can be reduced to 1/3 by disposing each pixel cell in the horizontal direction.

Fourth, it is possible to minimize the size of the flexible printed circuit by reducing the size of the flexible printed circuit by driving the liquid crystal panel with only one integrated circuit.

Fifth, the gate driver for driving the gate lines may be embedded in the liquid crystal panel to remove the gate driver integrated circuit, the gate flexible printed circuit, and the gate printed circuit board.

Sixth, the manufacturing process of the liquid crystal panel, the process of mounting the driving integrated circuit, and the process of attaching the flexible printed circuit may be manufactured to simplify the manufacturing process and minimize the defect rate.

Claims (12)

A liquid crystal panel is formed for each region defined by n gate lines and m data lines and has a plurality of pixel cells in which three colors are repeatedly arranged in the direction of the data line and the same color is arranged in the direction of the gate line. and, A gate embedded circuit formed in the liquid crystal panel and supplying a gate-on voltage to gate lines; And a driving integrated circuit mounted on the liquid crystal panel to drive the gate embedded circuit and to invert the polarity of the image signal in units of the data line and at least three gate lines to supply the data lines to the data lines. Liquid crystal display device. a liquid crystal panel in which pixel cells are formed in respective regions defined by n gate lines and m data lines; A gate embedded circuit formed in the liquid crystal panel and supplying a gate-on voltage to gate lines; And a driving integrated circuit mounted on the liquid crystal panel to drive the gate embedded circuit and supply image signals of different colors to the data line in units of horizontal lines corresponding to the direction of the gate line. And the driving integrated circuit inverts the polarity of the image signal in units of the data line and at least three gate lines. The method of claim 2, Wherein the pixel cells are repeatedly arranged in three colors in the direction of the data line, and three adjacent pixel cells constitute one unit pixel. The method according to claim 1 or 3, And the pixel cell includes a pixel electrode having a short side length parallel to the data line and a shorter side length parallel to the gate line. The method of claim 4, wherein The driving integrated circuit, A signal relay unit for relaying an input source data signal and a synchronization signal; A first power generating unit generating a first power; A second power generator configured to generate a second power using the first power; A common voltage generator supplying a common voltage to the liquid crystal panel using the second power supply; A signal controller for aligning the source data signal supplied from the signal relay to be suitable for driving the liquid crystal panel and controlling the inside of the driving integrated circuit; A control signal generator for generating a gate driving signal and a data control signal for driving the gate embedded circuit using the synchronization signal supplied through the signal controller; A boosting circuit for boosting the voltage level of the gate driving signal using the second power supply and supplying the voltage to the gate embedded circuit; A gray voltage generator for generating a plurality of gray voltages using the first power source; And a data converter converting the aligned data signal supplied from the signal controller into the image signal according to the data control signal using the plurality of gray voltages. The method of claim 5, wherein The driving integrated circuit, A clock generator which generates a clock for driving the first and second power sources; And a level setting unit for setting a voltage level of the first power supplied from the first power generation unit to the gray level voltage generation unit. The method of claim 5, wherein The signal controller divides one horizontal section into first to third subsections, and arranges the source data signal of the first horizontal section into data of first to third colors so as to correspond to each subsection. Display. The method of claim 7, wherein The data converter, A shift register for generating a shift signal, A latch unit for latching the aligned data signal according to the shift signal; A digital-to-analog converter for converting the latched data signal into positive and negative image signals using the plurality of gray voltages; A buffer unit for buffering the positive and negative image signals; And a selector for selecting the positive and negative image signals according to the data polarity signals supplied from the control signal generator and supplying the positive and negative image signals to the data lines through a plurality of output channels. . The method of claim 8, And the control signal generation unit generates the data polarity signal for inverting the polarity of the image signal selected and output from the selection unit by the data line and at least three gate lines. The method according to claim 1 or 3, And a flexible printed circuit connecting the liquid crystal panel to an external driving system. The method of claim 10, And the flexible printed circuit includes a passive element including at least one of a resistor, a capacitor, and an inductor for biasing the first power supply or for an optional function of the driving integrated circuit. The method of claim 10, The flexible printed circuit may include a common voltage varying part including at least one of a resistor and a capacitor for varying the common voltage.

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