KR20080066439A - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent generation of leakage current into a bulk part of an active region except for a source/drain junction region by forming a leakage current prevention layer in a moat region of a boundary between an isolation layer and an active region. An isolation layer(108) is formed on a semiconductor substrate(100) of a sense amplifier region to define an active region(106). A moat region(M) is formed in a boundary between the active region and the isolation layer. A leakage current prevention layer is formed in the moat region. A gate is formed at an upper part of the semiconductor substrate. A source/drain junction region(112) is formed at a lower part of the semiconductor substrate corresponding to a lateral surface of the gate. An interlayer dielectric(114) including a bitline contact plug is formed at the upper part of the semiconductor substrate.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1 is a plan view showing a semiconductor device according to the prior art.

2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

3 is a cross-sectional view illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing leakage current of a bit line sense amplifier.

In general, a shallow trench isolation (STI) method is used for forming a device isolation layer in a semiconductor device, particularly a DRAM. In this STI method, after forming a trench, a high density plasma (HDP) oxide film is deposited so that the trench is gap filled, and the device isolation layer is formed by planarization using a chemical mechanical polishing (CMP) process. It is made by the process.

However, in the device isolation film forming process to which the STI method is applied, a moat in which a corner portion of the device isolation film is formed is generated. Such a mote may cause a deterioration of operating characteristics of the semiconductor device. In particular, many problems occur such as reducing the threshold voltage of the transistor to increase the amount of current IDD2 in the off state.

1 is a plan view showing a semiconductor device according to the prior art.

Referring to FIG. 1, an isolation layer 18 defining an active region 16 is formed on a semiconductor substrate 10 in a sense amplifier region. A gate 19 is formed on the semiconductor substrate 10, and the bit line 26 is connected through a bit line contact plug 24 connected to the active region 16.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art, and is shown along a cutting line AA ′ of FIG. 1.

2, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 10.

Next, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 10 having a predetermined depth are etched by a photolithography process using a mask defining an active region to form a device isolation trench (not shown).

Next, a sidewall oxidation process is performed on the sidewalls and the bottom of the device isolation trench to form a sidewall oxide film 12.

Next, a liner nitride film 14 is formed on the entire surface including the sidewall oxide film 12.

Next, an insulating film, for example, a high density plasma (HDP) oxide film is deposited on the liner nitride film 14 so as to completely fill the trench for device isolation, and the annealing process is performed to densify the film quality.

At this time, the liner nitride film 14 and the high density plasma oxide film react with each other during the annealing process, and thus the surface of the liner nitride film 14 is oxidized. That is, since the thickness of the liner nitride layer 14 is reduced, the liner nitride layer 14 may not function as an etch barrier.

Next, a planarization process is performed to expose the pad nitride layer, and the pad nitride layer and the pad oxide layer are removed to form an isolation layer 18 defining an active region 16.

In this case, the liner nitride layer 14 is partially lost during the wet etching and cleaning process for removing the pad nitride layer and the pad oxide layer.

As a result, a portion of the sidewall oxide film 12 and the insulating film formed on both sides of the liner nitride film 14 are also partially lost, and a moat region M deep between the active region 16 and the device isolation layer 18 is formed. ) Occurs.

Next, a gate oxide film (not shown) is formed on the semiconductor substrate 10.

Next, a gate silicon film (not shown), a gate metal film (not shown), and a gate hard mask film (not shown) are sequentially formed on the gate oxide film.

Next, a gate (not shown) is formed by etching the gate hard mask layer, the gate metal layer, and the gate silicon layer by a photolithography process using a gate mask.

Next, an impurity is implanted into the lower portion of the semiconductor substrate 10 on the side of the gate to form a source / drain junction region 20.

Next, after forming a gate spacer (not shown) on the sidewall of the gate, an interlayer insulating film 22 is formed over the entire surface.

Next, a photoresist layer (not shown) is formed on the interlayer insulating layer 22, and the photoresist layer is exposed and developed with a bit line contact mask to form a photoresist pattern (not shown).

Next, the interlayer insulating layer 22 is etched using the photoresist pattern as a mask to form a bit line contact hole (not shown).

Next, a bit line contact plug 24 is formed by filling a conductive film in the bit line contact hole.

3 is a cross-sectional view illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 3, as the size of the semiconductor device decreases, the contact resistance Rc increases. As the contact resistance increases, the current decreases relatively, resulting in deterioration of the characteristics of the sense amplifier, resulting in insufficient sensing margin. In order to solve this problem, a method of increasing the area of the active region 16 or reducing the size of the bit line contact plug 24 is used.

However, the method of increasing the area of the active region 16 has a problem in that a bridge occurs due to a reduction in the distance between the active region and the adjacent active region. In addition, the method of reducing the size of the bit line contact plug 24 reduces the contact resistance by only a small amount compared to the extent of the area of the active region 16, but the contact resistance of the bit line contact plug 24 and the active is reduced. There is a problem in that the overlap margin with the region 16 is insufficient.

As a result, the bit line contact plug 24 is not formed only on the source / drain junction region 20, but partially extends on the mote region M of the device isolation layer 18.

Therefore, a leakage current (arrow direction) is generated in the bulk portion of the active region 16 except for the source / drain junction region 20, so that the threshold voltage Vt of the transistor cannot be set to a desired level, and thus it is turned off. There is a problem that the amount of current in the state is increased to cause a defect.

The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing a leakage current of a transistor constituting a bit line sense amplifier.

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming a device isolation layer defining an active region on the semiconductor substrate of the sense amplifier region, wherein a moat region is formed at a boundary between the active region and the device isolation layer;

Forming a leakage current prevention film inside the moat region;

Forming a gate over the semiconductor substrate, and forming a source / drain junction region under the semiconductor substrate on the side of the gate;

Forming an interlayer insulating film including a bit line contact plug on the semiconductor substrate;

Characterized in that it comprises a.

In addition, the method of manufacturing a semiconductor device according to the present invention

Forming an isolation trench in the semiconductor substrate in the sense amplifier region;

Forming a liner nitride film inside the device isolation trench;

Performing an annealing process on the liner nitride film;

Forming a leakage current prevention film on the liner nitride film;

Forming an isolation layer defining an active region by filling an insulating layer in the isolation trench;

Forming a gate over the semiconductor substrate, and forming a source / drain junction region under the semiconductor substrate on the side of the gate;

Forming an interlayer insulating film including a bit line contact plug on the semiconductor substrate;

Characterized in that it comprises a.

In the method for manufacturing a semiconductor device according to the present invention,

And performing a cleaning process of removing the liner nitride film after performing the annealing process.

The leakage current prevention film is formed of a nitride film,

The leakage current prevention film is characterized in that it is formed to a thickness of 50 ~ 100Å.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 4, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 100 in the sense amplifier region.

Subsequently, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 100 having a predetermined depth are etched by a photolithography process using a mask defining an active region to form a device isolation trench (not shown).

Next, a sidewall oxidation process is performed on the sidewalls and the bottom of the isolation trench to prevent stress and loss of the semiconductor substrate 100 exposed by the etching process for forming the isolation trench. The side wall oxide film 102 is formed.

Next, a liner nitride film 104 is formed on the sidewall oxide film 102 and the pad nitride film.

In this case, the liner nitride layer 104 serves as a buffer layer to relieve stress applied to the inside of the device isolation trench.

Next, an insulating film (not shown) is formed over the entire surface, and annealing is performed to densify the film quality of the insulating film.

In this case, the insulating film is preferably formed of a high density plasma (HDP) oxide film.

Next, a planarization process is performed to expose the pad nitride layer, and the pad nitride layer and the pad oxide layer are removed to form an isolation layer 108 defining an active region 106.

In this case, the liner nitride layer 104 is partially lost during the wet etching and cleaning process for removing the pad nitride layer and the pad oxide layer.

As a result, a portion of the sidewall oxide layer 102 and the insulating layer formed on both sides of the liner nitride layer 104 are also lost, and a moat region M deep between the active region 106 and the device isolation layer 108 is formed. ) Occurs.

Then, a leakage current prevention film (not shown) is formed over the entire surface.

At this time, the leakage current prevention film is formed of a nitride film, it is preferable to form a thickness of 50 ~ 100Å.

Next, the planarization process is performed on the leakage current prevention layer until the semiconductor substrate 100 is exposed.

Accordingly, the leakage current prevention layer pattern 110 is formed inside the moat region M. As shown in FIG.

Next, a gate oxide film (not shown) is formed on the semiconductor substrate 100.

Next, a gate silicon film (not shown), a gate metal film (not shown), and a gate hard mask film (not shown) are sequentially formed on the gate oxide film.

Next, a gate (not shown) is formed by etching the gate hard mask layer, the gate metal layer, and the gate silicon layer by a photolithography process using a gate mask.

Next, an impurity is implanted into the lower portion of the semiconductor substrate 100 on the side of the gate to form a source / drain junction region 112.

Next, after forming a gate spacer (not shown) on the sidewall of the gate, an interlayer insulating film 114 is formed over the entire surface.

In a subsequent process, a photoresist layer (not shown) is formed on the interlayer insulating layer 114, and the photoresist layer is exposed and developed with a bit line contact mask to form a photoresist pattern (not shown).

Next, the interlayer insulating layer 114 is etched using the photoresist pattern as a mask to form a bit line contact hole (not shown).

Next, a conductive film is filled in the bit line contact hole to form a bit line contact plug (not shown).

In this case, even when the bit line contact plug is formed to partially cover the mote region M of the device isolation layer 108, the active circuit except for the source / drain junction region 112 may be formed by the leakage current prevention layer pattern 110. It is possible to prevent the leakage current from occurring in the bulk portion of the region 106.

5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 5, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 200 in the sense amplifier region.

Subsequently, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 200 having a predetermined depth are etched by a photolithography process using a mask defining an active region to form a device isolation trench (not shown).

Next, a sidewall oxidation process is performed on the sidewalls and the bottom of the isolation trench to prevent stress and loss of the semiconductor substrate 100 exposed by the etching process for forming the isolation trench. A sidewall oxide film 202 is formed.

A liner nitride film 204 is formed on the sidewall oxide film 202 and the pad nitride film.

In this case, the liner nitride layer 204 serves as a buffer layer to relieve stress applied to the inside of the device isolation trench.

Next, an annealing process is performed on the liner nitride film 204.

At this time, the surface of the liner nitride film 204 is oxidized. That is, since the thickness of the liner nitride film 204 is reduced, the liner nitride film 204 cannot serve as an etch barrier.

Next, a leakage current prevention layer 206 is formed on the liner nitride layer 204.

At this time, the leakage current prevention film 206 is to compensate for the reduced thickness by oxidizing the liner nitride film 204, it is preferable to form a nitride film of 50 ~ 100 Å thickness.

Although not shown in the drawings, the cleaning method may further include a cleaning process of removing the oxidized liner nitride layer 204 before forming the leakage current prevention layer 206.

Next, an insulating film (not shown) is formed over the entire surface.

In this case, the insulating film is preferably formed of a high density plasma (HDP) oxide film.

Next, a planarization process is performed to expose the pad nitride layer, and the pad nitride layer and the pad oxide layer are removed to form an isolation layer 210 defining an active region 208.

In this case, the leakage current prevention layer 208 is partially lost during the wet etching and cleaning processes for removing the pad nitride layer and the pad oxide layer.

However, even when the leakage current prevention layer 208 is partially lost, since the thickness is sufficiently thick, it may serve as an etching barrier.

Accordingly, even when a deep moat region M is generated due to partial loss of the insulating layer formed on one side of the leakage current prevention layer 208, the active region 208 and the device are prevented by the leakage current prevention layer 208. Insulation characteristics may be maintained between the separators 210.

Next, a gate (not shown) is formed on the semiconductor substrate 200, and impurities are injected into the lower portion of the semiconductor substrate 200 on the side of the gate to form a source / drain junction region 212.

Next, after forming a gate spacer (not shown) on the gate sidewall, an interlayer insulating film 214 is formed over the entire surface.

In a subsequent process, a photoresist layer (not shown) is formed on the interlayer insulating layer 214, and the photoresist layer is exposed and developed using a bit line contact mask to form a photoresist pattern (not shown).

Next, the interlayer insulating layer 214 is etched using the photoresist pattern as a mask to form a bit line contact hole (not shown).

Next, a conductive film is filled in the bit line contact hole to form a bit line contact plug (not shown).

In this case, even when the bit line contact plug is formed to partially cover the mote region M of the device isolation layer 210, the active region excluding the source / drain junction region 212 by the leakage current prevention layer 208. It is possible to prevent the leakage current from occurring in the bulk portion 208.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a leakage current prevention layer pattern is formed inside the mote region M generated at the boundary between the active region and the element isolation layer, or a leakage current prevention layer is formed inside the isolation trench. By further forming, leakage current can be prevented from occurring in the bulk portion of the active region except for the source / drain junction region.

Therefore, the transistor constituting the bit line sense amplifier can be normally operated to improve the reliability.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the bit line contact plug and the active region are misaligned or the bit line contact plug is formed by forming a leakage current prevention layer inside the moat region of the device isolation layer and the active region boundary. Even if the size of the circuit becomes large, leakage current is prevented from occurring in the bulk portion of the active region except for the source / drain junction region, thereby improving the reliability of the bit line sense amplifier.

In addition, the present invention provides an effect of maintaining an insulating property between the active region and the device isolation film by performing an annealing process in advance and further forming a leakage current prevention film inside the device isolation trench.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (7)

Forming an isolation layer defining an active region on the semiconductor substrate of the sense amplifier region, wherein a moat region is formed at a boundary between the active region and the isolation layer; Forming a leakage current prevention film inside the moat area; Forming a gate over the semiconductor substrate and forming a source / drain junction region under the semiconductor substrate on the side of the gate; And Forming an interlayer insulating film including a bit line contact plug on the semiconductor substrate; Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the leakage current prevention film is formed of a nitride film. The method of claim 1, wherein the leakage current prevention film is formed to a thickness of 50 ~ 100kW. Forming an isolation trench in the semiconductor substrate in the sense amplifier region; Forming a liner nitride film inside the device isolation trench; Performing an annealing process on the liner nitride film; Forming a leakage current prevention layer on the liner nitride layer; Forming an isolation layer defining an active region by filling an insulating layer in the isolation trench; Forming a gate over the semiconductor substrate and forming a source / drain junction region under the semiconductor substrate on the side of the gate; And Forming an interlayer insulating film including a bit line contact plug on the semiconductor substrate; Method of manufacturing a semiconductor device comprising a. The method of claim 4, further comprising performing a cleaning process of removing the liner nitride layer after performing the annealing process. The method of manufacturing a semiconductor device according to claim 4, wherein the leakage current prevention film is formed of a nitride film. The method of manufacturing a semiconductor device according to claim 4, wherein the leakage current prevention film is formed to a thickness of 50 to 100 mA.

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