KR20080062048A - Transistor and method of fabricating the same - Google Patents

Abstract

A transistor and a manufacturing method thereof are provided to form a channel having a width smaller than a width of a gate electrode by using etch selectivity of an insulating layer. A gate insulating layer(62) is formed on a semiconductor substrate(50). A gate electrode(64) is formed on the gate insulating layer. An undercut region is formed at lower ends of both sides of the gate electrode. A contact area having a width smaller than an upper width is formed at an interface between the gate electrode and the gate insulating layer. A source/drain region(66) is formed at both sides of the contact area. The gate insulating layer is extended in both sides of the contact area on the semiconductor substrate.

Description

Transistor and Method of Fabricating the Same

1 is a cross-sectional view of a general MOS transistor.

2 is a cross-sectional view of a transistor in accordance with an embodiment of the present invention.

3 to 7 are process cross-sectional views illustrating a method of forming a transistor according to an embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a transistor and a method for forming the same.

Currently, MOS transistors are used as the switching elements in the integrated circuits because of the stabilization of the manufacturing process, the miniaturization of devices, and the easy control of electrical characteristics. However, as the degree of integration of integrated circuit devices is increased and the gate line width is reduced to 100 nanometers or less, there is a limit in forming a gate electrode having a smaller line width.

1 is a cross-sectional view showing a conventional MOS transistor.

Referring to FIG. 1, in a typical MOS transistor, a gate electrode 24 is disposed on a semiconductor substrate 10 through a gate insulating layer 22, and spacer patterns 30 are formed on both sides of the gate electrode 24. The source region and the drain region 26 are formed in the lower substrate.

In the MOS transistor, the gate electrode may be patterned through a photolithography process after forming a gate conductive layer to have a predetermined width, and a channel defined in the semiconductor substrate between the source and drain regions in proportion to the width of the gate electrode 24. The length of the area is determined. Therefore, in order to pattern the gate electrode 24 having a small line width, an exposure apparatus having the same resolution and a photoresist film having etching resistance while the gate electrode having a small line width are etched are required.

However, due to the optical limitations of the exposure equipment, it is limited to reduce the width of the gate electrode, and as the line width becomes smaller, it becomes increasingly difficult to stably form a thick photoresist film.

The present invention provides a transistor having a small channel length and a method of forming the same without depending on the process limitation of the photolithography process.

The present invention provides a transistor having a large width and a relatively small channel length, and a method of forming the same.

In order to achieve the above technical problem, the present invention provides a transistor including a gate electrode having an undercut. The transistor of the present invention includes a semiconductor substrate, a gate insulating film formed on a semiconductor substrate, a gate insulating film formed on the gate insulating film, and having a undercut region at both lower ends thereof, and having a contact surface having a width smaller than an upper width at an interface with the gate insulating film. And a source region and a drain region respectively formed in the semiconductor substrate on both sides of the contact surface. In the present invention, the gate electrode may have a channel length relatively shorter than the width of the gate electrode by having an undercut at the lower end.

According to an aspect of the present invention, there is provided a method of forming a first insulating film and a second insulating film on a semiconductor substrate, and etching the second insulating film to a predetermined thickness to expose the first insulating film at a central portion thereof. Forming a trench, etching the exposed first insulating film to expose the semiconductor substrate, forming a gate insulating film on the exposed semiconductor substrate, and forming a gate electrode filling the trench on the gate insulating film. Include. In the present invention, the bottom surface of the gate electrode is formed in the opening by exposing the semiconductor substrate to the opening formed in the central portion of the trench bottom. Thus, a transistor having a channel length shorter than the width of the gate electrode can be formed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example)

2 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.

2, a gate insulating layer 62 is formed on a semiconductor substrate 50, and a gate electrode 64 is formed on the gate insulating layer 62. The gate electrode 64 has a gate insulating film 62 and a contact surface 64s. The contact surface of the gate electrode 64 corresponds to a part of the upper surface of the gate insulating film 62, and the gate insulating film extends laterally to both sides of the contact surface 64s.

The gate electrode 64 has an upper end extending laterally from the contact surface 64s and extending laterally. Accordingly, the gate electrode 64 has a structure in which the contact surface 64s having a width smaller than that of the upper end is formed by narrowing the width while having the undercut 64s at the lower end.

The gate insulating layer 62 may extend a predetermined width in the lateral direction from the contact surface 64s of the gate electrode, and an insulating layer different from the gate insulating layer 62 may be formed on the substrate on both sides of the gate insulating layer 62. Preferably, the gate insulating film 62 may be formed of a thermal oxide film, and both insulating films 52 may be formed of a CVD oxide film.

An impurity is implanted into the semiconductor substrate on both sides of the contact surface 64s of the gate electrode to form the source region and the drain region 66. The source region and the drain region 66 may have a single diffusion structure or a double diffusion structure such as LDD or DDD.

As shown in the drawing, the gate electrode 64 has a structure in which the lower width is relatively smaller than the upper width, and the short width of the lower portion of the gate electrode 64 is shorter than the width of the gate electrode. Can be formed.

3 to 7 are process cross-sectional views illustrating a method of forming a transistor according to an embodiment of the present invention.

Referring to FIG. 3, a first insulating film 52 and a second insulating film 54 are formed on the semiconductor substrate 50. The first insulating film 52 and the second insulating film 54 are formed of a material having etch selectivity with each other. The thickness of the gate insulating layer may be determined according to the thicknesses of the first insulating layer 52 and the second insulating layer 54. Thus, when the thickness of the gate insulating film is selected, the first insulating film is formed to a thickness suitable for it.

The photoresist pattern 56 is formed on the second insulating film 54. The photoresist pattern 56 has a region where a portion of the second insulating layer 54 is exposed. In a typical transistor planar structure, the gate electrode has a line shape across the top of the active region defined in the semiconductor substrate. Accordingly, the photoresist pattern 56 may define an exposed area of the line-shaped second insulating film.

Referring to FIG. 4, a portion of the exposed portion of the second insulating layer 54 is etched using the photoresist pattern 56 as an etching mask. By controlling the etching time so that the second insulating film 54 is not completely removed from the exposed area, a residue of the second insulating film 54 having a predetermined thickness may be left on the first insulating film 52 in the exposed area.

In this case, since the thickness of the lower end and the upper end of the gate electrode may be determined according to the etching depth of the second insulating layer 54 and the thickness of the residue of the second insulating layer, the etching conditions may be appropriately adjusted according to the desired cross section. In order to lower the resistance of the gate electrode without affecting the channel length, it is preferable that the depth of the gate trench 54g from which the second insulating layer 54 is removed is deep.

Subsequently, referring to FIG. 4, the photoresist pattern 56 is removed to expose the second insulating film 54, and a conformal spacer insulating film is formed on the entire surface of the substrate on which the second insulating film 54 is exposed. The spacer insulating film is anisotropically etched to form the spacer pattern 58 on the side wall of the gate trench 54g. The spacer pattern 58 is formed of a material having an etch selectivity with respect to the second insulating film 54. Accordingly, the second insulating layer 54 is anisotropically etched using the spacer pattern 58 as an etching mask to form an opening 60 in which a portion of the first insulating layer is exposed. Since the spacer pattern 58 is formed on both side walls of the gate trench 54g, an opening 60 parallel to the gate trench may be formed at the bottom center of the gate trench 54g.

Referring to FIG. 5, the spacer pattern 58 formed on the sidewall of the gate trench 54g is removed to expose the sidewall and the bottom surface of the gate trench 54g. The spacer pattern 58 may be removed by isotropic etching. When using an etchant having an etching characteristic with respect to the spacer pattern 58 and the first insulating film 52, the first insulating film 52 is removed from the portion exposed to the opening 60 while the spacer pattern 58 is removed. Can be removed together. The first insulating layer 52 may be etched from a portion exposed to the opening 60 and isotropically etched laterally to form an undercut region 52u under the second insulating layer 54.

Referring to FIG. 6, the substrate from which the spacer pattern 58 and the first insulating film 52 are removed is thermally oxidized and exposed to the undercut region 52u of the first insulating film under the opening of the second insulating film 52. A gate insulating film 62 is formed on the semiconductor substrate. The gate insulating layer 62 may be filled in the undercut region under the second insulating layer 52 by appropriately adjusting the growth thickness.

A gate conductive film filling the opening 60 and the gate trench 54g is formed on the entire surface of the substrate on which the gate insulating film 62 is formed, and the gate conductive film is polished using a chemical mechanical polishing process to fill the gate trench 54g. Electrode 64 is formed.

Referring to FIG. 7, the second insulating layer 52 around the gate electrode 64 is removed to expose the gate electrode 64 having the upper width and the undercut region 64u at the lower portion thereof. The second insulating film 52, the first insulating film 52, and the gate insulating film 62 are formed of insulating films having different etching characteristics, so that the first insulating film 52 and the gate insulating film in the etching solution with respect to the second insulating film 52. It is preferred that 62) is not etched.

Subsequently, although not shown, an ion implantation process is performed to form source and drain regions in the substrates on both sides of the gate electrode 64. The source region and the drain region 66 of FIG. 2 may be formed in a single structure or a double structure.

The source drain region having a single structure can be formed by implanting impurity ions into the semiconductor substrate 50 using the gate electrode 64 as an ion implantation mask.

When forming a source drain region having a dual structure, the upper end portion of the gate electrode 64 serves as an ion implantation mask so that the first impurity ions are implanted into the semiconductor substrate 50, and the first impurity region is diffused into the gate electrode 64. ) And the lower portion of the contact surface between the gate insulating layer 62 and the first impurity region and the second impurity region may be formed by implanting the second impurity ions into the semiconductor substrate 50 in the same manner to control the diffusion distance. Can be.

The present invention can reduce the channel length by forming a lower end portion having a width smaller than the width of the gate electrode patterned by the photolithography process using the etching selectivity of the insulating film.

As described above, according to the present invention, the gate electrode, which is difficult to form a pattern due to the exposure limit, has a width smaller than the width of the gate electrode by reducing the width of only the lower end portion defining the channel region by using the etching selectivity of the insulating film. A transistor having a channel length of can be manufactured.

Claims (10)

Semiconductor substrates; A gate insulating film formed on the semiconductor substrate; A gate electrode formed on the gate insulating film, the gate electrode having an undercut region at both lower ends thereof, and having a contact surface having a width smaller than an upper width at an interface with the gate insulating film; And And a source region and a drain region respectively formed on the semiconductor substrate on both sides of the contact surface. In claim 1, And the gate insulating film extends on both sides of the contact surface and formed on the semiconductor substrate. In claim 1, And an insulating film formed on the substrate on both sides of the gate insulating film. In claim 3, The gate insulating film is a thermal oxide film, And the insulating films on both sides of the gate insulating film are CVD oxide films. In claim 1, And the undercut region has a predetermined thickness and the contact surface is an end portion of a portion extending downward from an upper end portion of the gate electrode. In claim 1, And the undercut region is positioned at both ends of the lower end of the gate electrode and extends in parallel with the gate electrode. Forming a first insulating film and a second insulating film on the semiconductor substrate; Etching the second insulating layer to a predetermined thickness to form a trench having an opening in which a first insulating layer is exposed at a central portion thereof; Etching the exposed first insulating film to expose a semiconductor substrate; Forming a gate insulating film on the exposed semiconductor substrate; And Forming a gate electrode filling the trench on the gate insulating film. In claim 7, Forming the trench, Etching the second insulating layer to a predetermined thickness to form a trench in which a portion of the second insulating layer remains; Forming a spacer pattern on both sidewalls of the trench; Forming an opening by using the spacer pattern as an etch mask to remove remaining portions of the second insulating layer; And Removing the spacer pattern. In claim 7, And isotropically etching the spacer pattern and isotropically etching the exposed first insulating film to expose the semiconductor substrate. In claim 9, Isotropically etching the first insulating film to form an undercut region in which a semiconductor substrate is exposed under the second insulating film, wherein the gate insulating film is formed on the exposed semiconductor substrate.

Images