KR20080057397A - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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KR20080057397A
KR20080057397A KR1020060130623A KR20060130623A KR20080057397A KR 20080057397 A KR20080057397 A KR 20080057397A KR 1020060130623 A KR1020060130623 A KR 1020060130623A KR 20060130623 A KR20060130623 A KR 20060130623A KR 20080057397 A KR20080057397 A KR 20080057397A
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polysilicon layer
gate insulating
manufacturing
semiconductor device
insulating film
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KR1020060130623A
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Korean (ko)
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KR100842504B1 (en
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정민호
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

A method for manufacturing a semiconductor device is provided to prevent the pollution of a gate insulating layer caused by a dopant gas by preventing the contact between the gate insulating layer and a doped polysilicon layer. A gate insulating layer(103) is formed on a semiconductor substrate(101). An undoped polysilicon layer(104) is formed on the gate insulating layer under an SiH4 atmosphere. A doped polysilicon layer is deposited on the undoped polysilicon layer under a dopant gas atmosphere. Wherein, the undoped polysilicon layer is formed as the thickness of 80 to 120 Å.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

도 1a 내지 도 1d는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

101 : 반도체 기판 102 : 소자분리막101 semiconductor substrate 102 device isolation film

103 : 게이트 절연막 104 : 언도프드 폴리실리콘층103 gate insulating film 104 undoped polysilicon layer

105 : 도프드 폴리실리콘층 106 : 단일화된 도프드 폴리실리콘층105: doped polysilicon layer 106: unified doped polysilicon layer

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체 기판상에 형성되는 도프드 폴리실리콘층이 게이트 절연막에 접촉되는 것을 차단함으로써 게이트 절연막이 불순물에 의해 오염되는 것을 방지하는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device. It relates to a manufacturing method.

일반적으로, 반도체 기판상에 게이트 절연막을 형성한 다음, 게이트 절연막에 도프드 폴리실리콘(doped polysilicon)을 인시튜(in-situ)로 증착할 경우 반도체 기판을 실리콘 소오스 가스(silicon source gas)가 공급되는 프로세스챔 버(process chamber)내에서 일정 온도로 가열시킴으로써 반도체 기판의 게이트 절연막에 도프드 폴리실리콘이 증착되도록 한다.Generally, when a gate insulating film is formed on a semiconductor substrate and then doped polysilicon is deposited in-situ on the gate insulating film, a silicon source gas is supplied to the semiconductor substrate. The doped polysilicon is deposited on the gate insulating film of the semiconductor substrate by heating to a predetermined temperature in the process chamber.

이러한 도프드 폴리실리콘의 증착공정은 실리콘 소오스 가스로, SiH4를 도펀트(dopant)로 PH3, B2H6 등을 해당 공정 온도, 약 595도씨 정도에서 서로 혼합시켜서 반도체 기판상의 게이트 절연막에 폴리실리콘을 증착하게 된다. The deposition process of the doped polysilicon is a silicon source gas, SiH 4 as a dopant, and PH 3 , B 2 H 6 , and the like are mixed with each other at a corresponding process temperature, about 595 degrees Celsius, to a gate insulating film on a semiconductor substrate. Polysilicon is deposited.

그러나, 이와 같이 종래의 반도체 소자를 제조하기 위한 공정에서 도프드 폴리실리콘을 인시튜로 증착하는 레시피(recipe)를 보면, 원하는 기본 압력(base pressure)으로 감압한 후에 증착 단계에서 가스를 플로우(flow)해 주는데, 이 때 증착 단계에 들어가자마자 SiH4와 불순물 가스가 동시에 플로우되면, 게이트 절연막까지 형성된 웨이퍼는 불순물 가스와 접하게 되므로 오염물을 발생시키는 문제점을 가지고 있었다.However, the recipe for depositing doped polysilicon in situ in the process for manufacturing a conventional semiconductor device as described above, the gas flow in the deposition step after reducing the pressure to the desired base pressure (base pressure) At this time, if SiH 4 and the impurity gas were flowed at the same time as soon as the deposition step, the wafer formed to the gate insulating film was in contact with the impurity gas had a problem of generating contaminants.

그러므로, 반도체 소자를 제조하기 위한 공정에서 도프드 폴리실리콘의 증착공정에서 도펀트 가스인 불순물과 게이트 절연막과의 접촉을 막아 오염을 방지할 필요가 있다. Therefore, it is necessary to prevent contamination by preventing contact between the dopant gas impurity and the gate insulating film in the deposition process of the doped polysilicon in the process for manufacturing a semiconductor device.

본 발명은 상술한 종래의 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 반도체 기판상에 형성되는 도프드 폴리실리콘층이 게이트 절연막에 접촉되는 것을 차단함으로써 도프드 폴리실리콘층의 도펀트 가스인 불순물이 게이트 절연막에 접촉하여 오염시키는 것을 방지하는 반도체 소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to prevent the doped polysilicon layer from being contacted with the gate insulating film to prevent the doped polysilicon layer from being impurity. The present invention provides a method for manufacturing a semiconductor device that prevents contamination by contact with a gate insulating film.

이와 같은 목적을 실현하기 위한 본 발명은, 반도체 소자의 제조방법에 있어서, 반도체 기판상에 게이트 절연막을 형성시키는 단계와, 게이트 절연막상에 SiH4 분위기하에서 언도프드 폴리실리콘층을 형성시키는 단계와, 언도프드 폴리실리콘층상에 도펀트 가스 분위기하에서 도프드 폴리실리콘층을 증착 형성시키는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a gate insulating film on a semiconductor substrate, forming an undoped polysilicon layer on a gate insulating film in an SiH 4 atmosphere, And depositing a doped polysilicon layer on the undoped polysilicon layer under a dopant gas atmosphere.

이하, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 본 발명의 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 더욱 상세히 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

도 1a 내지 도 1d는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다. 도시된 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판상에 게이트 절연막을 형성시키는 단계와, 게이트 절연막상에 언도프드 폴리실리콘층을 형성시키는 단계와, 언도프드 폴리실리콘층상에 도프드 폴리실리콘층을 증착 형성시키는 단계를 포함한다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. As shown, the method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate insulating film on the semiconductor substrate, forming an undoped polysilicon layer on the gate insulating film, doped on the undoped polysilicon layer Depositing a polysilicon layer.

도 1a에 도시된 바와 같이, 반도체 기판상에 게이트 절연막을 형성시키는 단계는 반도체 기판(101)의 소정영역에 STI(Shallow Trench Isolation) 구조를 가지는 소자분리막(102)을 형성한다. 여기서 소자분리막(102)은 반도체 기판(101)에 소정깊이를 갖는 트랜치를 형성한 후, 트랜치 내부에 갭-필(Gap-fill) 물질을 매립하여 형성한다.As shown in FIG. 1A, in the forming of the gate insulating film on the semiconductor substrate, an isolation layer 102 having a shallow trench isolation (STI) structure is formed in a predetermined region of the semiconductor substrate 101. The device isolation layer 102 is formed by forming a trench having a predetermined depth in the semiconductor substrate 101 and then filling a gap-fill material in the trench.

그런 다음, 소자분리막(102)을 포함한 반도체 기판(101)의 전면에 게이트 절연막(103)을 형성한다.Then, the gate insulating film 103 is formed on the entire surface of the semiconductor substrate 101 including the device isolation film 102.

도 1b에 도시된 바와 같이, 게이트 절연막상에 언도프드 폴리실리콘층을 형성시키는 단계는 게이트 절연막(103)이 형성된 웨이퍼를 프로세스챔버로 로딩하여 SiH4를 플로우시켜서 SiH4 분위기하에서 언도프드 폴리실리콘층(104)을 형성시킨다.As shown in FIG. 1B, forming the undoped polysilicon layer on the gate insulating film loads the wafer on which the gate insulating film 103 is formed into the process chamber to flow SiH 4 to flow the SiH 4 undoped polysilicon layer under an SiH 4 atmosphere. 104 is formed.

이 때, 언도프드 폴리실리콘층(104)은 80 내지 120Å, 바람직하게는 100Å의 두께를 가지도록 형성함으로써 게이트 절연막(103)과 후술하게 될 도프드 폴리실리콘층(105; 도 1c에 도시)간의 접촉을 효과적으로 방지함과 아울러 어닐(anneal) 공정시 도프드 폴리실리콘층(105; 도 1c에 도시)의 불순물이 언도프드 폴리실리콘층(104)으로 주입되어 도프드 폴리실리콘층(105)과 언도프드 폴리실리콘층(104)이 단일화된 일체를 이루도록 한다.At this time, the undoped polysilicon layer 104 is formed to have a thickness of 80 to 120 GPa, preferably 100 GPa, so that the gap between the gate insulating film 103 and the doped polysilicon layer 105 (shown in FIG. In addition to effectively preventing contact, impurities of the doped polysilicon layer 105 (shown in FIG. 1C) are implanted into the undoped polysilicon layer 104 during an annealing process to undo the doped polysilicon layer 105. Pudded polysilicon layer 104 to form a unitary unity.

도 1c에 도시된 바와 같이, 언도프드 폴리실리콘층상에 도프드 폴리실리콘층을 형성시키는 단계는 언도프드 폴리실리콘층(104)상에 도펀트 가스 분위기하에서 도프드 폴리실리콘층(105)을 CVD 공정 등에 의해 증착 형성시키게 된다.As shown in FIG. 1C, the step of forming the doped polysilicon layer on the undoped polysilicon layer may be performed by performing a CVD process or the like on the undoped polysilicon layer 104 under a dopant gas atmosphere. By vapor deposition.

이 때, 언도프드 폴리실리콘층(104)이 형성된 반도체 기판(101)에 도펀트 가스로서 SiH4와 PH3를 혼합하여 플로우시켜서 인시튜(in-situ) 도프드 폴리실리콘을 증착함으로써 도프드 폴리실리콘층(105)을 형성시키게 된다.At this time, SiH 4 and PH 3 are mixed and flowed as a dopant gas to the semiconductor substrate 101 on which the undoped polysilicon layer 104 is formed to deposit in-situ doped polysilicon to deposit doped polysilicon. Layer 105 will be formed.

한편, 도 1d에 도시된 바와 같이, 도프드 폴리실리콘층을 형성시키는 단계이후 어닐(anneal) 단계를 실시할 수 있는데, 이러한 어닐 단계는 도프드 폴리실리콘 층(105; 도 1c에 도시)을 형성한 반도체 기판(101)을 RTA 등에 의해 일정 온도로 가열함으로써 도프드 폴리실리콘층(105; 도 1c에 도시)의 도펀트가 언도프드 폴리실리콘층(104; 도 1b 및 도 1c에 도시)으로 확산되도록 함으로써 이들이 단일화된 도프드 폴리실리콘층(106)이 되도록 한다.On the other hand, as shown in Figure 1d, after the step of forming the doped polysilicon layer may be subjected to an anneal (annealing), this annealing step forms a doped polysilicon layer 105 (shown in Figure 1c) The semiconductor substrate 101 is heated to a predetermined temperature by RTA or the like so that the dopant of the doped polysilicon layer 105 (shown in FIG. 1C) diffuses into the undoped polysilicon layer 104 (shown in FIGS. 1B and 1C). Thereby making them a unified doped polysilicon layer 106.

이후 단계에 대해서 도시하지 않았으나, 반도체 기판(101)상에 형성된 하나의 도프드 폴리실리콘층(106)을 사진석판술 및 식각공정을 실시하여 선택적으로 패터닝함으로써 소자분리막(102)사이의 반도체 기판(101)상에 게이트 전극을 형성하게 되며, 이 후 게이트 전극의 양측에 LDD(Lightly Doped Drain)영역을 형성함과 아울러 게이트 전극 양측면에 측벽 스페이서를 형성한 다음 게이트 전극 양측의 반도체 기판(101) 표면내에 LDD영역과 연결되는 소오스/드레인 불순물 확산영역을 형성하게 된다.Although not shown in the subsequent steps, a single doped polysilicon layer 106 formed on the semiconductor substrate 101 is selectively patterned by performing photolithography and etching processes to form a semiconductor substrate between the device isolation films 102. A gate electrode is formed on the gate electrode 101, and then lightly doped drain (LDD) regions are formed on both sides of the gate electrode, sidewall spacers are formed on both sides of the gate electrode, and then the surface of the semiconductor substrate 101 on both sides of the gate electrode is formed. A source / drain impurity diffusion region connected to the LDD region is formed in the substrate.

그런 다음, 소오스 및 드레인 불순물 확산영역의 표면이 소정부분 노출되도록 층간 절연막을 선택적으로 제거하여 콘택홀을 형성한 다음 콘택홀을 포함한 반도체 기판(101)의 전면에 물리기상증착법이나 화학기상증착법으로 TiN, Ta, TaN, WNX, TiAl(N) 등을 10 내지 1000Å의 두께를 갖는 베리어 금속막을 형성한다.Then, the interlayer insulating film is selectively removed to expose the surface of the source and drain impurity diffusion regions to form a contact hole, and then TiN is deposited on the entire surface of the semiconductor substrate 101 including the contact hole by physical vapor deposition or chemical vapor deposition. , Ta, TaN, WNX, TiAl (N) and the like form a barrier metal film having a thickness of 10 to 1000 GPa.

이상과 같이 본 발명의 바람직한 실시예에 따르면, 게이트 절연막(103)상에 형성되는 언도프드 폴리실리콘층(104)에 의해 인시튜(in-situ) 도프드 폴리실리콘의 증착 초기에 발생할 수 있는 PH3, B2H6 등의 불순물 가스와 게이트 절연막(103)과의 접촉을 방지함으로써 게이트 절연막(103)의 오염으로 인한 트랜지스터의 특성 변화를 막을 수 있다.As described above, according to the preferred embodiment of the present invention, the PH which may occur in the early stage of deposition of the in-situ doped polysilicon by the undoped polysilicon layer 104 formed on the gate insulating film 103 By preventing the contact between the impurity gas such as 3 and B 2 H 6 and the gate insulating film 103, it is possible to prevent the transistor from changing characteristics due to contamination of the gate insulating film 103.

또한, PH3, B2H6 의 가스가 분해되어 P,B 등의 원자가 되고, 이런 원자들이 게이트 절연막(103) 내부에 쌓이게 되면 절연파괴에 따른 전압의 저하, 유전상수의 변화를 초래하게 되고, 계면에 머무르게 되면 문턱 전압의 변화 등을 초래하여 소자의 신뢰성에 악영향을 미치게 되는데, 이러한 문제점을 언도프드 폴리실리콘층(104)이 도프드 폴리실리콘층(105)을 게이트 절연막(103)으로부터 비접촉되도록 하여 해결하게 된다.In addition, when the gas of PH 3 , B 2 H 6 is decomposed to become atoms of P, B, etc., and these atoms accumulate inside the gate insulating film 103, a voltage decrease and dielectric constant change due to dielectric breakdown occur. In this case, the threshold voltage may be changed to adversely affect the reliability of the device. The solution is to make it possible.

상술한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판상에 형성되는 도프드 폴리실리콘층이 게이트 절연막에 접촉되는 것을 차단함으로써 도프드 폴리실리콘층의 도펀트 가스인 불순물이 게이트 절연막에 접촉하여 오염시키는 것을 방지하는 효과를 가지고 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, the doped polysilicon layer formed on the semiconductor substrate is blocked from contacting the gate insulating film so that the impurity dopant gas of the doped polysilicon layer contacts the gate insulating film. It has the effect of preventing contamination.

이상에서 설명한 것은 본 발명에 따른 반도체 소자의 제조방법을 실시하기 위한 하나의 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와 같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.What has been described above is only one embodiment for carrying out the method of manufacturing a semiconductor device according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims of the present invention Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (4)

반도체 소자의 제조방법에 있어서,In the manufacturing method of a semiconductor device, 반도체 기판상에 게이트 절연막을 형성시키는 단계와,Forming a gate insulating film on the semiconductor substrate; 상기 게이트 절연막상에 SiH4 분위기하에서 언도프드 폴리실리콘층을 형성시키는 단계와,Forming an undoped polysilicon layer on the gate insulating film in a SiH 4 atmosphere; 상기 언도프드 폴리실리콘층상에 도펀트 가스 분위기하에서 도프드 폴리실리콘층을 증착 형성시키는 단계Depositing a doped polysilicon layer on the undoped polysilicon layer in a dopant gas atmosphere 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 언도프드 폴리실리콘층을 형성시키는 단계는,Forming the undoped polysilicon layer, 상기 언도프드 폴리실리콘층을 80 내지 120Å의 두께로 형성하는 것Forming the undoped polysilicon layer to a thickness of 80 to 120 kPa 을 특징으로 하는 반도체 소자의 제조방법.Method for manufacturing a semiconductor device, characterized in that. 제 1 항에 있어서, The method of claim 1, 상기 도프드 폴리실리콘층을 형성시키는 단계는,Forming the doped polysilicon layer, 상기 도펀트 가스로 SiH4와 PH3를 사용하는 것Using SiH 4 and PH 3 as the dopant gas 을 특징으로 하는 반도체 소자의 제조방법.Method for manufacturing a semiconductor device, characterized in that. 제 1 항에 있어서, The method of claim 1, 상기 도프드 폴리실리콘층을 형성시키는 단계이후 상기 반도체 기판을 어닐(anneal)하여 상기 도프드 폴리실리콘층의 도펀트가 상기 언도프드 폴리실리콘층으로 확산되도록 하는 단계Annealing the semiconductor substrate after forming the doped polysilicon layer to allow the dopant of the doped polysilicon layer to diffuse into the undoped polysilicon layer 를 더 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising.
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