KR20080048263A - Thin film transistor array substrate and method for fabricating thereof - Google Patents

Abstract

A TFT(Thin Film Transistor) array substrate and a manufacturing method thereof are provided to enable at least one of a gate pattern and a source drain pattern to be formed by a conductive layer and a conductive layer protection film formed to cover the conductive layer to improve the conductivity of the gate pattern and the source drain pattern, thereby improving the supply efficiency of a gate signal and a data signal and improving the switching characteristic of a TFT. A gate pattern includes a gate electrode(108) formed on a substrate(142), a gate line(102) connected with the gate electrode, and a lower gate pad electrode(128) connected to the gate line. A gate insulating film(144) is formed to cover the gate pattern. A source drain pattern includes a data line(104) crossing the gate line, a source electrode(110) connected to the data line, a drain electrode(112) facing the source electrode, and a lower data pad electrode(136) connected to the gate line. Transparent electrode patterns include a pixel electrode(118) connected to the drain electrode. At least one of the gate pattern and the source drain pattern includes a conductive layer(164) and a conductive layer protection film(162) formed to cover the conductive layer.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THEREOF}

1 is a plan view showing a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array substrate of FIG. 3 taken along a line II-II '.

5A through 5D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 4.

6A to 6C are views illustrating in detail a manufacturing process of the gate pattern of FIG. 5A.

 7 is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16, 116: first contact hole

18, 118: pixel electrodes 20, 120: storage capacitor

22, 122: storage electrode 24, 124: second contact hole

26, 126: gate pad portion 28, 128: gate pad lower electrode

30 and 130: third contact hole 32 and 132: gate pad upper electrode

34, 134: data pad portion 38, 138: fourth contact hole

40, 140: data pad upper electrode 42, 142: lower substrate

44, 144: gate insulating film 48, 148: ohmic contact layer

49, 149: semiconductor pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor array substrate capable of improving reliability of a thin film transistor and a gate pad portion, and a method of manufacturing the same.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

1 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 1 taken along the line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. A transistor 6, a pixel electrode 18 formed in a cell region provided in an intersecting structure thereof, a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2, and a gate line 2; The gate pad part 26 connected to the ()) and the data pad part 34 connected to the data line 4 are provided.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and the source electrode 10 and the drain electrode ( 12) further comprises a channel section therebetween. An ohmic contact layer 48 for ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. do. Hereinafter, the active layer 14 and the ohmic contact layer 48 will be referred to as a semiconductor pattern 49.

The thin film transistor 6 keeps the pixel voltage signal supplied to the data line 4 charged and maintained in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes the front gate line 2, the storage electrode 22 overlapping the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween. And a pixel electrode 22 which is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad portion 26 is formed through the gate pad lower electrode 28 extending from the gate line 2, and the gate pad lower electrode through the third contact hole 30 penetrating through the gate insulating layer 44 and the passivation layer 50. And a gate pad upper electrode 32 connected to (28).

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad part 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. The data pad upper electrode 40 is formed.

In the thin film transistor array substrate having such a configuration, gate patterns such as the gate electrode 8, the gate line 2, and the gate pad lower electrode 28 provide smooth supply of the gate signal for switching the thin film transistor 6. It is formed of copper (Cu) having high conductivity.

However, copper (Cu) has the advantages of very high electrical conductivity and thermal conductivity, but has a property that is well fused with other materials and easily corroded in the air. Accordingly, when the gate electrode is formed of only copper (Cu), the copper ions of the gate electrode 8 diffuse into the gate insulating film 44, thereby degrading the switching characteristics of the thin film transistor 6. In addition, since the gate pad lower electrode 28 is made of copper, the gate pad lower electrode 28 may be easily corroded by an external environment during the process, thereby preventing a normal gate signal from being supplied from the gate driver.

As such, in order to prevent a problem occurring when the gate pattern is formed of only copper (Cu), a gate pattern is recently formed by using a copper nitride alloy mixed with copper (Cu) and nitrogen (N). . However, as the nitrogen (N) is contained, the electrical conductivity is lowered by that amount, and the line resistance in the gate line 2 is generated, thereby preventing the normal signal supply.

Accordingly, there is a need for a method of improving conductivity and enabling normal signal supply and protecting gate patterns from an external environment.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, which can prevent corrosion of the gate metal pattern and improve conductivity to improve the reliability of the thin film transistor and the gate pad.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention includes a gate pattern including a gate electrode formed on the substrate, a gate line connected to the gate electrode, a gate pad lower electrode connected to the gate line; A gate insulating film formed to cover the gate pattern; A source drain pattern including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a data pad lower electrode connected to the data line; Transparent electrode patterns including a pixel electrode connected to the drain electrode, and at least one of the gate pattern and the source drain pattern includes a conductive layer and a conductive layer protective film formed to cover the conductive layer. It features.

The conductive layer is characterized by consisting of copper (Cu).

The conductive layer protective film is characterized in that it contains copper (Cu) and nitrogen (N).

The source drain pattern may include a storage electrode partially overlapping the gate line with the gate insulating layer interposed therebetween.

The semiconductor device may further include a passivation layer having a first contact hole for exposing the drain electrode, wherein the pixel electrode is in contact with the drain electrode through the first contact hole.

The transparent electrode pattern may include a gate pad upper electrode contacting the gate pad lower electrode through a second contact hole penetrating through the passivation layer and the gate insulating layer; And a data pad upper electrode contacting the data pad lower electrode through a third contact hole penetrating the passivation layer.

The semiconductor device may further include a semiconductor pattern under the source drain pattern.

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line on the substrate; Forming a gate insulating film to cover the gate pattern; Forming a source drain pattern on the gate insulating layer including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a data pad lower electrode connected to the data line Wow; Forming a transparent electrode pattern including a pixel electrode connected to the drain electrode, wherein forming at least one of the gate patterns and the source drain patterns comprises: forming a conductive layer; And forming a conductive layer protective film covering the conductive layer.

The forming of the conductive layer protective film may include forming a copper nitride (CuN) film by reacting an inert gas including copper and nitrogen in the conductive layer.

The forming of the copper nitride (CuN) film further includes removing oxygen concentrated on the surface of the conductive layer before the copper and the inert gas are reacted.

Inert gas containing copper and nitrogen in the said conductive layer reacts in 200-800 degreeC environment.

Ammonia (NH ₃ ) is used as the inert gas containing nitrogen.

The forming of the source drain pattern may include forming a storage electrode partially overlapping the gate line with the gate insulating layer interposed therebetween.

Forming a passivation layer having a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad lower electrode, and a third contact hole exposing the data pad lower electrode.

The pixel electrode is in contact with the drain electrode through the first contact hole.

The forming of the transparent electrode pattern may include forming a gate pad upper electrode contacting the gate pad lower electrode through the second contact hole and a data pad upper electrode contacting the data pad lower electrode through the third contact hole. Forming a step.

The forming of the source drain pattern may further include forming a semiconductor pattern under the source drain pattern.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 7.

3 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 4 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 3 taken along a line II-II '.

The thin film transistor array substrate illustrated in FIGS. 3 and 4 includes a gate line 102 and a data line 104 formed to intersect on a lower substrate 142 with a gate insulating layer 144 therebetween, and a thin film formed at each intersection thereof. A transistor 106, a pixel electrode 118 formed in a cell region provided in an intersecting structure thereof, a storage capacitor 120 formed at an overlapping portion of the pixel electrode 118 and the front gate line 102, and a gate line 102; ), And a gate pad portion 126 connected to the () and a data pad portion 134 connected to the data line 104.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 connected to the pixel electrode 116. And an active layer 114 overlapping the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. The active layer 114 is formed to overlap the data pad 136, the storage electrode 122, the data line 14, the source electrode 110, and the drain electrode 112, and the source electrode 110 and the drain electrode 112. It further comprises a channel portion between. An ohmic contact layer 148 for ohmic contact with the data pad lower electrode 136, the storage electrode 122, the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114. do. Hereinafter, the active layer 114 and the ohmic contact layer 148 will be referred to as a semiconductor pattern 149.

The thin film transistor 106 keeps the pixel voltage signal supplied to the data line 104 charged to the pixel electrode 118 in response to the gate signal supplied to the gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the thin film transistor 106 through the first contact hole 116 penetrating the passivation layer 150. The pixel electrode 118 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 118 from the light source (not shown) toward the upper substrate.

The storage capacitor 120 includes the storage gate 122 overlapping the front gate line 102 with the gate line 102, the gate insulating layer 144, the active layer 114, and the ohmic contact layer 148 interposed therebetween. ) And the pixel electrode 122 that overlaps with the storage electrode 122 and the passivation layer 150 therebetween and is connected via the second contact hole 124 formed in the passivation layer 150. The storage capacitor 120 allows the pixel voltage charged in the pixel electrode 118 to be stably maintained until the next pixel voltage is charged.

The gate line 102 is connected to a gate driver (not shown) through the gate pad part 126. The gate pad portion 126 is formed through the gate pad lower electrode 128 extending from the gate line 102, and the gate pad lower electrode through the third contact hole 130 penetrating the gate insulating layer 144 and the passivation layer 150. And a gate pad upper electrode 132 connected to 128.

The data line 104 is connected to a data driver (not shown) through the data pad unit 134. The data pad unit 134 is connected to the data pad lower electrode 136 through the data pad lower electrode 136 extending from the data line 104 and the fourth contact hole 138 penetrating the passivation layer 150. The data pad upper electrode 140 is formed.

A gate pattern including the gate electrode 108 of the thin film transistor 106, the gate line 102 connected to the gate electrode, the gate pat lower electrode 128 connected to the gate line 102, and the like is formed of the conductive layer 164. And a conductive layer protective film 162 formed to cover the conductive layer 164.

Since the conductive layer 164 is made of copper (Cu), the electrical conductivity and the thermal conductivity are very high. As a result, the supply of the gate signal for switching the thin film transistor 6 is improved in efficiency.

The conductive layer protective film 162 is formed of a copper nitride (CuN) film in which copper (Cu) and nitrogen (N) are mixed to protect the conductive layer 164 made of copper. As described above, when the gate pattern is formed of only copper (Cu), as the copper ions penetrate into the gate insulating layer 144, the switching characteristic of the thin film transistor 106 is degraded, and the gate pad lower electrode 128 is exposed to the external environment. There is a risk of corrosion. Accordingly, the conductive layer protective film 162 is used to cover the conductive layer 164 made of copper (Cu), thereby smoothly supplying the gate signal of the gate pattern and preventing corrosion of the gate pattern. Will be. Furthermore, the conductive layer protective film 162 prevents diffusion of copper ions in the conductive layer 164 into the gate insulating film 144.

5A through 5D are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

Referring to FIG. 5A, a gate line 102, a gate electrode 108, and a gate are formed of a conductive layer 164 and a conductive layer protective layer 162 formed on the lower substrate 142 to cover the conductive layer 164 and the conductive layer 164. Gate patterns including the pad lower electrode 128 are formed.

Hereinafter, a process of forming a gate pattern will be described in detail with reference to FIGS. 6A to 6D.

The copper thin film layer is deposited on the lower substrate 142 through the deposition method of the sputtering method. Subsequently, the copper thin layer is patterned by a photolithography process and an etching process using a mask to form a conductive layer 164 as shown in FIG. 6A.

The lower substrate 142 on which the conductive layer 164 is formed is loaded into the plasma apparatus, and an inert gas such as ammonia (NH ₃ ) is supplied to the plasma apparatus, and then ammonia (NH ₃ ) and The surface of the conductive layer 164 is reacted.

Accordingly, oxygen (O) on the surface of the conductive layer 164 is removed as shown in FIG. 6B.

In more detail, the surface of the conductive layer 164 made of copper is easily oxidized so that oxygen is concentrated on the surface of the conductive layer 164. Accordingly, ammonia (NH ₃ ) and oxygen (O) on the surface of the conductive layer 164 react first. As a result, oxygen (O) on the surface of the conductive layer 164 is removed by reacting with two hydrogens (H) in ammonia (NH ₃ ) to vaporize (H ₂ O) and then vaporize. At the same time, oxygen (O) is also reacted with nitrogen (N), so that nitrogen oxides (N ₂ O), nitric acid (HNO ₃ ), and the like are formed and then removed by vaporization.

Subsequently, when all of the oxygen (O) on the surface of the conductive layer 164 is removed, as shown in FIG. 6C, ammonia (NH ₃ ) directly reacts with copper (Cu), and copper nitride (CuN) is formed on the surface of the conductive layer 164. ) Film is formed and hydrogen (H ₂ ) gas is generated.

The chemical formula for this is as follows.

2NH ₃ + 2Cu-> 2CuN + 3H ₂ (gas)

Accordingly, as illustrated in FIG. 5A, gate patterns including the conductive layer 164 and the conductive layer protective film 162 formed to cover the conductive layer 164 are formed.

Referring to FIG. 5B, the gate insulating layer 144, the active layer 114, the ohmic contact layer 148, and the source / drain patterns are sequentially formed on the lower substrate 142 on which the gate patterns are formed.

The gate insulating layer 144, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 142 on which the gate patterns are formed by a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 104, the source electrode 110, the drain electrode 112 integrated with the source electrode 110, and the storage electrode 122 are formed. A source drain pattern comprising a is formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form a semiconductor pattern 149 including the ohmic contact layer 148 and the active layer 114.

Then, the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 148 of the channel portion are etched by a dry etching process. Accordingly, the active layer 114 of the channel portion is exposed to separate the source electrode 110 and the drain electrode 112.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 5C, a passivation layer 150 including first to fourth contact holes 116, 124, 130, and 138 is formed on the gate insulating layer 144 on which the source / drain patterns are formed.

The passivation layer 150 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a mask to form first to fourth contact holes 116, 124, 130, and 138. The first contact hole 116 is formed to pass through the passivation layer 150 to expose the drain electrode 112, and the second contact hole 124 is formed to pass through the passivation layer 150 to expose the storage electrode 122. do. The third contact hole 130 is formed to pass through the passivation layer 150 and the gate insulating layer 144 to expose the gate pad lower electrode 128. The fourth contact hole 138 is formed through the passivation layer 150 to expose the data pad lower electrode 136.

As the material of the passivation layer 150, an inorganic insulating material such as the gate insulating film 144 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 5D, transparent electrode patterns are formed on the passivation layer 150.

The transparent electrode material is deposited on the passivation layer 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through a photolithography process and an etching process using a mask, thereby forming transparent electrode patterns including the pixel electrode 118, the gate pad upper electrode 132, and the data pad upper electrode 140. . The pixel electrode 118 is electrically connected to the drain electrode 112 through the first contact hole 116 and the storage electrode 122 overlapping the front gate line 102 through the second contact hole 124. Electrically connected. The gate pad upper electrode 132 is electrically connected to the gate pad lower electrode 128 through the third contact hole 130. The data pad upper electrode 140 is electrically connected to the data pad lower electrode 136 through the fourth contact hole 138. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the present invention include the gate electrode 108 of the thin film transistor 106, the gate line 102 connected to the gate electrode, and the lower gate pat connected to the gate line 102. A gate pattern including the electrode 128 is formed of a conductive layer 164 made of copper and a conductive layer protective film 162 formed to cover the conductive layer 164. Accordingly, the conductivity of the gate pattern can be improved, thereby improving the gate signal supply efficiency to the thin film transistor, thereby improving switching characteristics of the thin film transistor, and also improving the reliability of the pad part, such as preventing corrosion of the gate pad lower electrode 128. do.

Meanwhile, the conductive layer protective film 162 according to the present invention forms a copper nitride film (CuN) by using a copper nitride (CuN) target, and patterns the copper nitride film (CuN) by a photolithography process and an etching process using a mask. Can be formed accordingly.

7 is a cross-sectional view illustrating a thin film transistor array substrate according to still another embodiment of the present invention.

Compared to the thin film transistor array substrates shown in FIGS. 3 and 4, the thin film transistor array substrate illustrated in FIG. 7 includes a conductive layer formed so as to cover the conductive layer 164 and the conductive layer 164 made of copper. Since the same components are provided except for the layer protective layer 162, the same components as those of FIGS. 3 and 4 will be denoted by the same reference numerals and detailed description thereof will be omitted.

In the thin film transistor array substrate of FIG. 7, the source / drain patterns including the data line 104, the source electrode 110, the drain electrode 112, the storage electrode 122, and the data pad lower electrode 136 are electrically conductive. Is composed of a conductive layer 164 made of high copper and a conductive layer protective film 162 which is directed to cover the conductive layer 164 and is a copper nitride (CuN) film. Accordingly, the resistance of the source / drain patterns can be lowered and the conductivity can be improved, thereby improving the supply efficiency of the data signal. In addition, the source / drain patterns may be protected from the external environment, such as to prevent corrosion of the data pad lower electrode 136.

In the method of manufacturing the thin film transistor array substrate illustrated in FIG. 7, the method of forming the source drain pattern is formed by the same method as the method illustrated in FIGS. 6A to 6C. That is, the conductive layer 164 of the source drain pattern is made of copper and forms the conductive layer protective film 164 using ammonia (NH ₃ ) gas.

The manufacturing method of the other components is formed by the same manufacturing process as the method shown in Figures 5a to 5d will be omitted detailed description.

Meanwhile, when the source drain pattern includes the conductive layer 164 and the conductive layer passivation layer 162, the thin film transistor array substrate without the passivation layer 150 may be formed.

As described above, at least one of the thin film transistor array substrate and the manufacturing method gate patterns and the source drain patterns according to the present invention is formed to cover the conductive layer 164 and the conductive layer 164 made of copper. It consists of a layer protective film. Accordingly, the conductivity of the gate patterns and the source drain patterns can be improved, thereby improving supply efficiency of the gate signal and the data signal, thereby improving switching characteristics of the thin film transistor and preventing pads from being corroded. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (19)

A gate pattern including a gate electrode formed on the substrate, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line; A gate insulating film formed to cover the gate pattern; A source drain pattern including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a data pad lower electrode connected to the data line; Transparent electrode patterns including a pixel electrode connected to the drain electrode; And at least one of the gate pattern and the source drain pattern includes a conductive layer and a conductive layer protection layer formed to cover the conductive layer. The method of claim 1, The conductive layer is a thin film transistor array substrate, characterized in that made of copper (Cu). The method of claim 1, The conductive layer passivation layer may include copper (Cu) and nitrogen (N). The method of claim 1, The source drain pattern includes a storage electrode partially overlapping the gate line with the gate insulating layer interposed therebetween. The method of claim 1, Further comprising a protective film having a first contact hole for exposing the drain electrode, The pixel electrode is in contact with the drain electrode through the first contact hole. The method of claim 5, wherein The transparent electrode pattern is A gate pad upper electrode contacting the gate pad lower electrode through a second contact hole penetrating through the passivation layer and the gate insulating layer; And a data pad upper electrode contacting the data pad lower electrode through a third contact hole penetrating through the passivation layer. The method of claim 1, The thin film transistor array substrate further comprising a semiconductor pattern under the source drain pattern. Forming a gate pattern including a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line on the substrate; Forming a gate insulating film to cover the gate pattern; Forming a source drain pattern including a data line crossing the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a data pad lower electrode connected to the data line on the gate insulating layer; Wow; Forming a transparent electrode pattern including a pixel electrode connected to the drain electrode, Forming at least one of the gate patterns and the source drain patterns Forming a conductive layer; And forming a conductive layer protective film covering the conductive layer. The method of claim 8, The conductive layer is a method of manufacturing a thin film transistor array substrate, characterized in that made of copper. The method of claim 9, Forming the conductive layer protective film Forming a copper nitride (CuN) film by reacting an inert gas containing copper and nitrogen in the conductive layer. The method of claim 10, Forming the copper nitride (CuN) film And removing oxygen that is concentrated on the surface of the conductive layer before the copper and the inert gas are reacted. The method of claim 10, Inert gas containing copper and nitrogen in the conductive layer reacts in an environment of 200 ~ 800 ℃. The method of claim 10, Ammonia (NH ₃ ) is used as the inert gas containing nitrogen, the method of manufacturing a thin film transistor array substrate. The method of claim 8, Forming the source drain pattern And forming a storage electrode partially overlapping the gate line with the gate insulating layer interposed therebetween. The method of claim 8, And forming a passivation layer having a first contact hole exposing the drain electrode, a second contact hole exposing the gate pad lower electrode, and a third contact hole exposing the data pad lower electrode. A method of manufacturing a thin film transistor array substrate. The method of claim 15, The pixel electrode is in contact with the drain electrode through the first contact hole. The method of claim 15, Forming the transparent electrode pattern And forming a gate pad upper electrode in contact with the gate pad lower electrode through the second contact hole and a data pad upper electrode in contact with the data pad lower electrode through the third contact hole. A method of manufacturing a thin film transistor array substrate. The method of claim 12, Forming the source drain pattern And forming a semiconductor pattern under the source drain pattern. The method of claim 8, Forming the conductive layer protective film Forming a copper nitride film (CuN) film on the conductive layer by using a copper nitride film (CuN) target; And patterning the copper nitride film (CuN) film.

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