KR20080047383A - 초소형 전자 소자를 위한 금속 상호접속 구조체 - Google Patents

초소형 전자 소자를 위한 금속 상호접속 구조체 Download PDF

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Publication number
KR20080047383A
KR20080047383A KR1020087006150A KR20087006150A KR20080047383A KR 20080047383 A KR20080047383 A KR 20080047383A KR 1020087006150 A KR1020087006150 A KR 1020087006150A KR 20087006150 A KR20087006150 A KR 20087006150A KR 20080047383 A KR20080047383 A KR 20080047383A
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KR
South Korea
Prior art keywords
metal
dielectric
dielectric cap
layer
forming
Prior art date
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Abandoned
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KR1020087006150A
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English (en)
Korean (ko)
Inventor
치흐-차오 양
카우시크 찬다
로렌스 클레벤저
윤-유 왕
대원 양
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR20080047383A publication Critical patent/KR20080047383A/ko
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020087006150A 2005-09-19 2006-09-06 초소형 전자 소자를 위한 금속 상호접속 구조체 Abandoned KR20080047383A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/162,666 US7563704B2 (en) 2005-09-19 2005-09-19 Method of forming an interconnect including a dielectric cap having a tensile stress
US11/162,666 2005-09-19

Publications (1)

Publication Number Publication Date
KR20080047383A true KR20080047383A (ko) 2008-05-28

Family

ID=37400882

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087006150A Abandoned KR20080047383A (ko) 2005-09-19 2006-09-06 초소형 전자 소자를 위한 금속 상호접속 구조체

Country Status (7)

Country Link
US (1) US7563704B2 (https=)
EP (1) EP1943675B1 (https=)
JP (1) JP5261647B2 (https=)
KR (1) KR20080047383A (https=)
CN (1) CN100583427C (https=)
TW (1) TWI397149B (https=)
WO (1) WO2007039385A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150047647A (ko) * 2013-10-22 2015-05-06 삼성전자주식회사 반도체 소자

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US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
US8178436B2 (en) * 2006-12-21 2012-05-15 Intel Corporation Adhesion and electromigration performance at an interface between a dielectric and metal
US7666753B2 (en) * 2007-01-11 2010-02-23 International Business Machines Corporation Metal capping process for BEOL interconnect with air gaps
US8592312B2 (en) * 2007-06-07 2013-11-26 Globalfoundries Inc. Method for depositing a conductive capping layer on metal lines
US7858532B2 (en) * 2007-08-06 2010-12-28 United Microelectronics Corp. Dielectric layer structure and manufacturing method thereof
US7732324B2 (en) * 2007-12-20 2010-06-08 Texas Instruments Incorporated Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer
US20090218644A1 (en) * 2008-02-29 2009-09-03 Gill Yong Lee Integrated Circuit, Memory Device, and Method of Manufacturing an Integrated Circuit
US8039966B2 (en) * 2009-09-03 2011-10-18 International Business Machines Corporation Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects
DE102009055439A1 (de) * 2009-12-31 2011-07-07 GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG, 01109 Halbleiterbauelement mit halbleiterbasierten e-Sicherungen mit besserer Programmiereffizienz durch erhöhte Metallagglomeration und/oder Hohlraumbildung
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US9224643B2 (en) * 2011-09-19 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for tunable interconnect scheme
US8981466B2 (en) * 2013-03-11 2015-03-17 International Business Machines Corporation Multilayer dielectric structures for semiconductor nano-devices
US9299605B2 (en) * 2014-03-07 2016-03-29 Applied Materials, Inc. Methods for forming passivation protection for an interconnection structure
US11756828B2 (en) 2018-11-20 2023-09-12 Applied Materials, Inc. Cluster processing system for forming a transition metal material
US20230335498A1 (en) * 2022-04-18 2023-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection structure and methods of forming the same

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US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
JP3226816B2 (ja) * 1996-12-25 2001-11-05 キヤノン販売株式会社 層間絶縁膜の形成方法、半導体装置及びその製造方法
US6369423B2 (en) * 1998-03-03 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device with a thin gate stack having a plurality of insulating layers
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6342733B1 (en) 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US6319819B1 (en) * 2000-01-18 2001-11-20 Advanced Micro Devices, Inc. Process for passivating top interface of damascene-type Cu interconnect lines
US6383925B1 (en) * 2000-02-04 2002-05-07 Advanced Micro Devices, Inc. Method of improving adhesion of capping layers to cooper interconnects
JP4350337B2 (ja) * 2001-04-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US6506677B1 (en) * 2001-05-02 2003-01-14 Advanced Micro Devices, Inc. Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance
US6429128B1 (en) * 2001-07-12 2002-08-06 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
CN1329972C (zh) * 2001-08-13 2007-08-01 株式会社荏原制作所 半导体器件及其制造方法
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US7091137B2 (en) * 2001-12-14 2006-08-15 Applied Materials Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6764951B1 (en) * 2002-02-28 2004-07-20 Advanced Micro Devices, Inc. Method for forming nitride capped Cu lines with reduced hillock formation
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US6617690B1 (en) * 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
JP2004095865A (ja) * 2002-08-30 2004-03-25 Nec Electronics Corp 半導体装置およびその製造方法
JP4606713B2 (ja) * 2002-10-17 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7241696B2 (en) * 2002-12-11 2007-07-10 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
US6818557B1 (en) * 2002-12-12 2004-11-16 Advanced Micro Devices, Inc. Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance
US7102232B2 (en) * 2004-04-19 2006-09-05 International Business Machines Corporation Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150047647A (ko) * 2013-10-22 2015-05-06 삼성전자주식회사 반도체 소자

Also Published As

Publication number Publication date
CN100583427C (zh) 2010-01-20
CN101268549A (zh) 2008-09-17
TWI397149B (zh) 2013-05-21
TW200729400A (en) 2007-08-01
EP1943675A1 (en) 2008-07-16
EP1943675B1 (en) 2013-03-20
JP5261647B2 (ja) 2013-08-14
US7563704B2 (en) 2009-07-21
WO2007039385A1 (en) 2007-04-12
JP2009509319A (ja) 2009-03-05
US20070063348A1 (en) 2007-03-22

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