KR20080046979A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to make the charge time of each pixel identical, thereby preventing the badness of the horizontal line. The LCD includes plural pixels(PX) having the first and second sub pixels arrayed by a matrix shape. Data lines(D1-Dn) are connected with the pixels. A data driving member(500) produces a data voltage and applies the data voltage to the data lines. A signal control member(600) processes the image signal from the outside and transmits the processed image signal to the data driving member together with plural control signals. The data driving member includes output terminals connected with the data lines and connects the output terminals by 1 H period. The plural controls signals include a load signal and a polarity conversion signal. The output terminal is connected during the high period of the load signal.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are equivalent circuit diagrams of one pixel of the liquid crystal display according to the exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a gray voltage generator of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a block diagram of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a signal waveform diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

200: upper display panel

300: liquid crystal panel assembly 400: gate driver

500: data driver 511: resistance string

513: analog switching element 600: signal control unit

800: gray voltage generator 811: resistance string

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

PX: Pixel PXa, PXb: Subpixel

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element SL: sustain electrode wire

DL: data line GL: gate line

PE: pixel electrode CF: color filter

CE: common electrode SEL: selection signal

DAC: Digital to Analog Converter

VGMA: Gray Reference Voltage LOAD: Load Signal

POL: polarity reversal signal

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Meanwhile, the liquid crystal display includes a display panel including a pixel including a switching element and a display signal line, a gray voltage generator to generate a gray reference voltage, and a plurality of gray voltages by using the gray reference voltages. And a data driver for applying a gray scale voltage corresponding to the video signal to the data lines of the display signal lines.

In addition, among the liquid crystal display devices, the vertical alignment mode liquid crystal display in which the long axes of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device has a high contrast ratio and is easy to implement a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

In order to solve this problem, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is directly applied with voltage, and the other subpixel causes voltage drop due to capacitive coupling. A method of changing the transmittances by changing the voltages of the two subpixels has been proposed.

In this case, different data voltages are applied to different transmittances, which are achieved by differently applying the gray voltage or the gray reference voltage applied to the two subpixels.

In addition, inversion driving is performed to prevent deterioration of the liquid crystal layer. In general, dot inversion or 2 × 1 inversion that inverts the polarity of the data voltage with respect to the common voltage in one row unit or two row units is generally used.

In particular, in the case of 2x1 inversion, the polarity of the data voltage applied to one data line is changed in units of two rows. That is, the two rows maintain the same polarity and the other two adjacent rows have different polarities. For example, when applied to kth through (k + 3) rows in the order of +, +,-,-, the row that maintains the same polarity (k + 1) and the row that is adjacent to and have the opposite polarity (k + 2) has a difference in the filling rate, so it appears as a bad horizontal line.

The technical problem to be achieved by the present invention is to provide a liquid crystal display device which can prevent such a horizontal line defect.

According to an aspect of the present invention, a liquid crystal display device including a plurality of pixels arranged in a matrix form and including first and second subpixels, respectively, generates data lines and data voltages connected to the pixels. A data driver for applying the data line, and a signal controller to process an image signal from an external source and to output the data signal to the data driver together with a plurality of control signals, wherein the data driver includes an output terminal connected to each of the data lines. And the output terminals are connected to each other at intervals of 1H.

In this case, the plurality of control signals include a load signal and a polarity inversion signal,

The output terminals may be connected to each other during the high period of the load signal.

Meanwhile, the data voltage may be changed in two rows based on the polarity inversion signal.

The data voltage may include a first voltage applied to the first subpixel and a second voltage applied to the second subpixel, and the magnitudes of the first voltage and the second voltage may be different from each other. have.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIGS. 2A and 2B are equivalent circuit diagrams of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. An equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment is shown.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. And a gray voltage generator 800 connected to the signal, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes a lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The display signal line is provided in the lower panel 100, and includes a plurality of gate lines G _1a -G _nb transmitting the gate signals (also called “scan signals”) and data lines D ₁ -D transferring the data signals. _m ). The gate lines G _1a -G _nb extend approximately in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

2A and 2B show an equivalent circuit of a display signal line and a pixel. In addition to the gate line indicated by reference numerals GLa and GLb and the data line indicated by reference numeral DL, the display signal lines are substantially parallel to the gate lines G ₁ -G _2b . The extended sustain electrode line SL is included.

Referring to FIG. 2A, each pixel PX includes a pair of subpixels PXa and PXb, and each of the subpixels PXa and PXb has a corresponding gate line GLa and GLb and a data line DL. Switching elements Qa and Qb connected thereto and liquid crystal capacitors Clca and Clcb connected thereto, and storage capacitors connected to switching elements Qa and Qb and sustain electrode lines SL. (Csta, Cstb). The storage capacitors Csta and Cstb may be omitted as necessary, and in this case, the storage electrode line SL is also unnecessary.

Referring to FIG. 2B, each pixel PX includes a pair of subpixels PXa and PXb and coupling capacitors Ccp connected therebetween, and each subpixel PXa and PXb has a corresponding gate line. And switching elements Qa and Qb connected to the GLa and GLb and data lines DL, and liquid crystal capacitors Clca and Clcb connected thereto. One of the two subpixels PXa and PXb includes a storage capacitor Csta connected to the switching element Qa and the storage electrode line SL.

Referring to FIG. 3, the switching elements Q of each of the subpixels PXa and PXb are formed of a thin film transistor or the like provided in the lower display panel 100, and each of the control terminals connected to the gate lines GL; A three-terminal device having an input terminal connected to the data line DL and an output terminal connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the subpixel electrode PE of the lower panel 100 and the common electrode CE of the upper panel 200, and the liquid crystal layer 3 between the two electrodes PE and CE It functions as a dielectric. The subpixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode CE may be provided in the lower panel 100. In this case, at least one of the two electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor Cst serving as an auxiliary role of the liquid crystal capacitor Clc is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. ), A predetermined voltage such as the common voltage Vcom is applied. However, the storage capacitor Cst may be formed by the subpixel electrode PE overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. 3 illustrates that each pixel includes a color filter CF representing one of primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrode PE of the lower panel 100.

Referring to FIG. 1, the gate driver 400 is connected to the gate lines G _1a -G _nb to receive a gate signal formed of a combination of a gate on voltage Von and a gate off voltage Voff from the outside. G _1a -G _nb ).

The gray voltage generator 800 generates a gray reference voltage set applied to the subpixel PXa among two sets of gray reference voltages related to the transmittance of the pixel.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to divide the gray reference voltage from the gray voltage generator 800 and another gray reference voltage for the entire gray level. Generate a gradation voltage and select a data voltage among them.

Two sets of gray reference voltages will be provided independently of two subpixels PXa and PXb constituting one pixel. Each set of gray reference voltages has a positive value and a negative value with respect to a common voltage Vcom. It includes having.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). In contrast, these driving devices 400, 500, 600, and 800 are connected to the liquid crystal panel assembly 300 together with the signal lines G _1a -G _nb , D ₁ -D _m and the thin film transistor switching elements Qa and Qb. It may be integrated. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync), the main clock signal MCLK, and the data enable signal DE are provided. Based on the input image signals R, G and B of the signal controller 600 and the input control signals, the image signals R, G and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and a clock signal CPV controlling the output time of the gate-on voltage Von.

The data control signal CONT2 is a horizontal synchronization start signal STH for transmitting data to a group of pixels PX and a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m . And a selection signal SEL for controlling the data clock signal HCLK and the analog switching element of the data driver 500. The data control signal CONT2 may also include an inversion signal POL that inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage). have.

The selection signal SEL is a signal for selecting one of two gray level reference voltage sets, and has the same period as the horizontal synchronization start signal STH, the load signal LOAD, and the like. On the other hand, the period of the clock signal among the gate control signal CONT1 may be twice the horizontal synchronization start signal STH, and in this case, it may be used as the selection signal SEL.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image data DAT for the bundle of subpixels PX, and applies the digital image data DAT to each digital image signal DAT. The digital image signal DAT is converted into an analog data signal by selecting a corresponding gray voltage, and then applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G _1a -G _nb in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G _1a -G _nb . Turn on the switching elements Qa and Qb connected to the corresponding subpixels PXa and PXb through the switching elements Qa and Qb on which the data voltages applied to the data lines D ₁ -D _m are turned on. Is applied to.

The difference between the data voltage applied to the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The data driver 500 and the gate driver 400 perform the same operation in units of 1/2 horizontal periods (or "1/2 H") (one period of the horizontal sync signal Hsync and the gate clock CPV). Repeat. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G _1a -G _nb during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame is started and the state of the inversion signal POL applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame. "). In this case, the polarities of the data voltages flowing through one data line change according to the characteristics of the inversion signal POL (eg, row inversion and point inversion) within one frame, or polarities of data voltages simultaneously flowing through adjacent data lines are also different from each other. Can be different (eg invert columns, invert points).

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a block diagram of a driving device of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a block diagram showing an example of a data driving integrated circuit (IC) forming a data driver shown in FIG. 1. Reference numeral 540 is used. FIG. 6 is a waveform diagram of the signal and data voltage shown in FIG. 5. 6, the waveform of the data voltage of the liquid crystal display according to the exemplary embodiment of the present invention is represented by 'Vdat1', and the waveform of the data voltage of the liquid crystal display according to the related art is represented by 'Vdat2'.

Referring to FIG. 4, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention may include a reference voltage generator 810 and a reference voltage generator 810 including a pair of resistor strings 811 and 511. Analog switching element 513 is connected.

Each of the resistor strings 811 and 511 is connected between the analog reference voltage AVDD and the ground voltage GND, and the resistor string 811 includes a plurality of resistors R1a through R18a connected in series. The high gray reference voltage set VGAMa applied to the pixel PXa is generated, and the resistor string 511 is applied to the subpixel PXb including a plurality of resistor strings R1b to R18b connected in series. Generate a low gradation reference voltage set (VGMb). In the drawing, an example of generating 18 reference voltages, each of nine positive and negative polarities, is illustrated.

The analog switching element 513 is composed of a multiplexer, and selects one of two sets of gray reference voltages according to the selection signal SEL and sends it out.

In this case, the resistor string 811 of the reference voltage generator 810 is included in the gray voltage generator 800, the resistor string 511 is included in the data driver 500, and the analog switching element 513 is also included in the data driver 500.

Referring to FIG. 5, a data driving integrated circuit 540 according to an exemplary embodiment of the present invention may include a shift register 541, a latch 543, a digital-to-analog converter (DAC) 545, and a buffer ( 547).

When the horizontal register start signal STH is applied, the shift register 541 sequentially shifts the input image data DAT according to the data clock signal HCLK, and transfers the image data DAT to the latch 543. When the data driver 500 includes a plurality of data driver ICs 540, the shift register 541 shifts all of the image data DAT in charge of the shift register 541, and then shifts the shift clock signal SC to a neighbor. To the shift register of the data driver IC.

Latch 543 includes first and second latches (not shown). The first latch receives and stores the image data DAT sequentially from the shift register 541. The second latch simultaneously receives and stores the image data DAT from the first latch according to the load signal LOAD. Export to analog converter 545.

The digital-to-analog converter 545 receives one of two sets of gray reference voltages VGMAa and VGMAb from the analog switching element 513, converts the digital image data DAT from the latch 543 into an analog data voltage, and buffers the analog data voltage. Export to (547). The data voltage has a positive value or a negative value with respect to the common voltage Vcom according to the polarity signal POL. At this time, the polarity voltage is changed in units of 2H, that is, in units of two rows as shown in FIG.

The buffer 547 outputs the data voltage from the digital-analog converter 545 through the output terminals Y ₁ -Y _r . The polarities of the data voltages output through the neighboring output terminals Y ₁ -Y _r are different from each other. The output terminals Y ₁ -Y _r are connected to the corresponding data lines D ₁ -D _m . The data signal applied to the data line is applied to the corresponding subpixels PXa and PXb through the switching elements turned on. At this time, the output terminals Y ₁ -Y _r are connected to each other at the time when the load signal LOAD becomes high, thereby performing charge sharing. Thus, the data voltage becomes substantially equal to the common voltage.

The pair of subpixels PXa and PXb receive separate data voltages through the same data line at different times, and the data voltage applied to the subpixels PXa is greater than the data voltages applied to the subpixels PXb. It is as high as shown in FIG.

On the other hand, in the data voltage Vdat1 of the liquid crystal display according to the exemplary embodiment, charge sharing is performed whenever the load signal LOAD becomes high, that is, every 1H. As a result, the charging time is the same since each pixel PX, for example, four sections a, b, c, and d, start charging with the positive or negative polarity at the common voltage Vcom. Therefore, it is possible to prevent the horizontal line defects that appear due to different charging times.

On the other hand, the data voltage Vdat2 of the liquid crystal display according to the related art is compared and explained as follows.

The data voltage Vdat2 of the liquid crystal display according to the related art performs charge sharing only when the polarity is changed. Among the sections a ', b', c ', and d', the section a 'starts from the common voltage Vcom, but the adjacent section b' is charged at a point higher than the common voltage Vcom. There is a brightness difference between the two sections a 'and b'. Similarly, the interval c 'starts at the common voltage Vcom and the interval d' has a brightness difference between the two sections c 'and d' at a point lower than the common voltage Vcom. Therefore, a horizontal line defect may occur due to the brightness difference.

However, in the liquid crystal display according to the exemplary embodiment of the present invention, the charging time is the same and thus uniform brightness may be prevented.

As described above, a horizontal line defect can be prevented by making the time charged in each pixel PX the same.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

A liquid crystal display device comprising a plurality of pixels arranged in a matrix and each including first and second subpixels. A data line connected to the pixel, A data driver for generating a data voltage and applying the data voltage to the data line; A signal controller which processes an image signal from the outside and sends it out to the data driver with a plurality of control signals. Including; The data driver includes an output terminal connected to each of the data lines, and connects the output terminals to each other at intervals of 1H. Liquid crystal display. In claim 1, The plurality of control signals include a load signal and a polarity inversion signal, The output terminals are connected to each other during the high period of the load signal. Liquid crystal display. In claim 2, And wherein the data voltage changes polarity in units of two rows according to the polarity inversion signal. In claim 3, The data voltage may include a first voltage applied to the first subpixel and a second voltage applied to the second subpixel. In claim 4, The liquid crystal display device of which the magnitudes of the first voltage and the second voltage are different from each other.

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