KR20080045493A - Apparatus, driving device and power supplier of plasma display - Google Patents

Abstract

A plasma display device, a driving apparatus and a power supply device thereof are provided to reduce power consumption of the plasma display device by removing a zener diode with a high withstanding voltage. A Vnf voltage generator includes resistors(R1,R2), a gate driving circuit(423), a capacitor(C1), and a transistor(Yfr). One end of the first resistor is connected to a voltage source(V1), while the other end is connected to the gate driving circuit. The second resistor is a variable resistor including a first end connected to the other end of the resistor and a second end connected to a voltage source(VscL). The transistor is turned on/off by a control signal which is inputted from the gate driving circuit, wherein a drain of the transistor is connected to a scan electrode(Y) and a source of the transistor is connected to a first end of the second resistor. One end of the capacitor is connected to the drain of the transistor and the first end of the second resistor, while the other end is connected to the voltage source.

Description

Plasma display device, driving device and power supply device {APPARATUS, DRIVING DEVICE AND POWER SUPPLIER OF PLASMA DISPLAY}

1 is a view showing a part of a driving apparatus of a plasma display apparatus for driving a conventional scan electrode.

2 is a block diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

3 illustrates driving waveforms of a plasma display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a driving circuit of a scan electrode driver for generating the driving waveform of FIG. 3 according to an exemplary embodiment of the present invention.

5A and 5B are views illustrating an operation process for generating a drive waveform in a rising period and a falling period of a reset period among the driving waveforms of FIG. 3, respectively, and FIG. 5C is a view of driving in an address period among the driving waveforms of FIG. 3. A diagram illustrating an operation process for generating a waveform.

6 illustrates a Vnf voltage generating circuit according to another embodiment of the present invention.

7 is a view showing a power supply according to an embodiment of the present invention.

The present invention relates to a plasma display device, and more particularly, to a driving device and a power supply device of the plasma display device.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size.

In general, in a plasma display device, one frame is divided into a plurality of subfields to be driven, and a gray level is displayed by a combination of weights of subfields in which a display operation occurs among the plurality of subfields. Each subfield is driven by being divided into a reset period, an address period, and a sustain period. The wall charge state of the discharge cells is initialized during the reset period, cells to be turned on and cells not to be turned on during the address period are selected, and sustain discharge is performed on the cells to be turned on to actually display an image during the sustain period. In this case, the plasma display device applies a voltage lower than the voltage applied at the end of the reset period to the scan electrode constituting the cell to be selected during the address period. A driving circuit therefor will be described with reference to FIG. 1. .

1 is a view showing a part of a driving apparatus of a plasma display apparatus for driving a conventional scan electrode.

As shown in FIG. 1, the conventional driving device 10 is turned on / off by a gate driving circuit 11 and a gate driving circuit 11, a drain is connected to the scan electrode Y, and a source is a VscL power supply. A transistor YscL connected to the transistor, a gate driving circuit 11 turned on / off, a transistor Yfr and a cathode whose source is connected to a VscL power supply, and a cathode connected to the scan electrode Y, and an anode of the transistor Yfr. Zener diode ZD1 connected to the source.

At the end of the reset period, the gate driving circuit 11 turns on the transistor Yfr, and the transistor YscL maintains the turn-off state. As a result, a current path is formed from the scan electrode Y to the VscL power supply through the zener diode ZD1 and the transistor Yfr. At this time, the zener diode ZD1 maintains the voltage applied to the scan electrode Y at a predetermined level (ΔV) higher than that of the VscL power supply.

In the address period, the gate driving circuit 11 turns off the transistor Yfr and turns on the transistor YscL. As a result, a current path from the scan electrode Y to the VscL power source is formed through the transistor YscL, and the voltage applied to the scan electrode Y becomes the VscL voltage.

   In general, the VscL voltage is on the order of -200V, and ΔV is set to around 25V. To this end, the zener diode ZD1 has a high voltage withstand of about 175V. However, the use of the zener diode having such a large voltage withstand voltage has the disadvantage of increasing the power consumption as well as increasing the implementation cost of the plasma display device.

In addition, the conventional driving device 10 shown in FIG. 1 cannot change the size of ΔV and thus cannot cope with the change in the design compatibility and the discharge margin of the plasma display device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device, a driving device, and a power supply device capable of changing a Vnf voltage.

In order to achieve the above technical problem, a driving apparatus of a plasma display device according to an aspect of the present invention includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes. A driving device of a plasma display device including an electrode, the first end of which is connected to a first power supply for supplying a first voltage applied to the first electrode at the end of a reset period, and the second end of which is connected to the first electrode. A first voltage supply unit including a first switch connected to the first switch and a first switching controller for controlling on / off of the first switch and a first stage are sequentially applied to the plurality of first electrodes in an address period, A second switch connected to a second power supply for supplying a second voltage lower than a voltage, and having a second end connected to the first electrode, and a second switching controller controlling on / off of the second switch. And a second voltage supply.

In addition, the driving apparatus of the plasma display device according to an aspect of the present invention includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes. A driving device for operating a plasma display device under control of a controller, comprising: a first resistor having one end connected to a first power supply for supplying a first voltage, one end being connected to the other end of the first resistor, and the other end being the first voltage; A second resistor connected to a second power supply for supplying a lower second voltage, a first capacitor connected at a first point of which one end is a contact point of the first and second resistors, and connected to the second power supply at the other end thereof; The first electrode is connected to the first electrode at a first stage and the second end is connected to the first point, and the first electrode receives a third voltage charged in the first capacitor in response to a resistance value of the second resistor when turned on. A first switch applied to the and And a switching controller for controlling the on / off of the first switch in response to the voltage level of the first point, wherein at least one of the first and second resistors is a variable resistor.

In addition, the power supply apparatus of the plasma display device according to an aspect of the present invention includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes. A power supply of a plasma display device, comprising: a converter configured to convert an input voltage to generate a first voltage and a second voltage lower than the first voltage, and a third voltage generated by stepping down the first voltage to the first electrode. A voltage converter configured to be applied to the first and second resistors connected in series between the output terminals of the first and second voltages, and a control electrode connected to the contacts of the first and second resistors. And a first end connected to an output end of the first voltage, one end connected to a second end of the switch, and another end connected to a second end of the switch and a capacitor connected to an output end of the second voltage. Comprising an output for outputting a third voltage that is charged in the capacitor group, and the third voltage is changed corresponding to any one or more of the resistance change of the first or second resistance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the term wall charge described herein refers to a charge formed close to each electrode on the cell's wall (eg, dielectric layer). Wall charges are not actually in contact with the electrodes themselves, but here they are described as “formed”, “accumulated” or “stacked” on the electrodes, where wall voltage refers to the potential difference formed on the wall of a cell by wall charges.

A plasma display device and a driving device thereof according to an embodiment of the present invention will now be described in detail with reference to the drawings.

2 is a block diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a control device 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. ) And a power supply 600.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 100 includes a substrate (not shown) on which the sustain electrodes X1 to Xn and the scan electrodes Y1 to Yn are arranged, and a substrate (not shown) on which the address electrodes A1 to Am are arranged. Is done. The two substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge spaces at the intersections of the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn form discharge cells. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal Sa, a sustain electrode driving control signal Sx, and a scan electrode driving control signal Sy. The control apparatus 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period when expressed as a temporal change in operation. In addition, the control device 200 generates a scan high voltage Vscan_h applied to a cell that is not addressed in the address period by using the DC voltage received from the power supply device 600 to scan electrode driver 400. Or to the sustain electrode driver 500.

The address electrode driver 300 receives an address electrode driving control signal Sa from the control device 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The scan electrode driver 400 receives the scan electrode driving control signal Sy from the controller 200 and applies a driving voltage to the scan electrode Y.

The sustain electrode driver 500 receives the sustain electrode driving control signal Sx from the controller 200 and applies a driving voltage to the sustain electrode X.

The power supply device 600 supplies power required for driving the plasma display device to the control device 200 and the respective driving units 300, 400, and 500.

3 illustrates driving waveforms of a plasma display device according to an exemplary embodiment of the present invention.

The driving waveform of the plasma display device shown in FIG. 3 shows only driving waveforms in one subfield, and one subfield of the plasma display panel 100 of FIG. 1 is controlled by the control unit 200 of FIG. 1. It consists of a reset period, an address period, and a sustain period according to variations in the input voltages of the sustain electrode X, the scan electrode Y, and the address electrode A. FIG.

First, the reset period will be described. The reset period consists of a rising period and a falling period. In the rising period, while maintaining the address electrode A and the sustain electrode X at the reference voltage (0 V in FIG. 2), the voltage of the scan electrode Y is gradually increased from the voltage Vs to the voltage Vset. The increase in the scan electrode Y voltage results in a weak discharge (hereinafter referred to as "weak discharge") between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A. FIG. This causes negative (-) wall charges to be formed on the scan electrode (Y), and positive (+) wall charges to the sustain electrode (X) and the address electrode (A). The sum of the wall voltage and the external applied voltage between the electrodes due to the wall charge formed when the voltage of the scan electrode Y reaches Vset is equal to the discharge start voltage Vf. In the reset period, the state of all cells must be initialized, which causes the Vset voltage to be set at a voltage high enough to cause a discharge in cells of all conditions. Meanwhile, although FIG. 2 illustrates a case in which the scan electrode Y voltage is increased or decreased in the form of a lamp, other types of waveforms that gradually increase or decrease may be applied.

In the falling period, the voltage of the scan electrode Y is gradually decreased from the voltage Vs to the voltage Vnf while the address electrode A and the sustain electrode X are maintained at the reference voltage and the Ve voltage, respectively. The decrease in the voltage of the scan electrode Y causes a weak discharge between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A, thereby causing the scan electrode ( The negative wall charges formed at Y) and the positive wall charges formed at the sustain electrode X and the address electrode A are erased. As a result, the negative wall charge of the scan electrode Y, the positive wall charge of the sustain electrode X, and the positive wall charge of the address electrode A are reduced. At this time, the positive wall charge of the address electrode A is reduced to an amount suitable for the address operation. In general, the magnitude of the (Vnf-Ve) voltage is set near the discharge initiation voltage Vf between the scan electrode Y and the sustain electrode X, and thus, between the scan electrode Y and the sustain electrode X. The difference in the wall voltage is near 0 V to prevent the cells which do not have an address discharge in the address period from being erroneously discharged in the sustain period.

The falling period of the above-described reset period must necessarily exist once for each subfield. On the contrary, the rising period is determined for each subfield according to the control program preset in the control unit 200 of FIG. 1.

In the address period, in order to select a cell to emit light, a scan pulse having a VscL voltage (scanning voltage) is sequentially applied to the plurality of scan electrodes Y while a Ve voltage is applied to the sustain electrode X. At the same time, the address voltage is applied to the address electrode A passing through the cell to emit light among the plurality of cells formed by the scan electrode Y to which the VscL voltage is applied. As a result, between the address electrode A to which the address voltage is applied and the scan electrode Y to which the VscL voltage is applied, and the scan electrode Y to which the VscL voltage is applied and the scan electrode Y to which the address voltage is applied, An address discharge is generated between the sustain electrodes X, so that positive wall charges are formed on the scan electrode Y, and negative wall charges are formed on the address electrode A and the sustain electrode X, respectively. At this time, the VscL voltage is set at a level lower than the Vnf voltage. On the other hand, a VscH voltage (non-scanning voltage) higher than the VscL voltage is applied to the scan electrode Y to which the VscL voltage is not applied, and a reference voltage is applied to the address electrode A of the discharge cell that is not selected.

In the sustain period, a sustain discharge pulse having a high level voltage (Vs voltage in FIG. 2) and a low level voltage (0V voltage in FIG. 2) is alternately applied to the scan electrode Y and the sustain electrode X in the opposite phase. Therefore, when the Vs voltage is applied to the scan electrode Y, the 0 V voltage is applied to the sustain electrode X, and the 0 V voltage is applied to the scan electrode Y when the Vs voltage is applied to the sustain electrode X. The discharge occurs at the scan electrode Y and the sustain electrode Y by the wall voltage and the Vs voltage formed between the scan electrode Y and the sustain electrode X by the address discharge. Thereafter, the process of applying the sustain discharge pulse to the scan electrode Y and the sustain electrode X is repeated a number of times corresponding to the weight indicated by the corresponding subfield.

Hereinafter, a driving circuit for generating a driving waveform of the plasma display device according to the exemplary embodiment of the present invention shown in FIG. 3 will be described in detail with reference to FIG. 4. For reference, the switch used below is illustrated as an n-channel field effect transistor (FET) having a body diode (not shown), and may be made of another switch having the same or similar function. In addition, the capacitive component formed by the sustain electrode X and the scan electrode Y is shown as a panel capacitor Cp.

 4 is a diagram illustrating a driving circuit of a scan electrode driver for generating the driving waveform of FIG. 3 according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the scan electrode driver 400 according to an exemplary embodiment of the present invention includes a sustain driver 410, a reset driver 420, and a scan driver 430.

The sustain driver 410 has a transistor Ys having a drain connected to the power supply Vs supplying the Vs voltage and a source connected between the scan electrode Y of the panel capacitor Cp and a drain of the panel capacitor Cp. And a transistor Yg connected to the scan electrode Y and connected to a power supply 0V to which a source supplies a 0V voltage. The transistor Ys applies a Vs voltage to the scan electrode Y, and the transistor Yg applies a 0V voltage to the scan electrode Y.

Although not shown in FIG. 4, the sustain driver 410 may include an energy recovery circuit (ERC) for recovering a voltage applied to the panel capacitor Cp.

The reset driver 420 includes transistors Yrr, Yfr, Ypp, and Ynp, a capacitor Cset, a diode Dset, and a Vnf voltage application control unit 422, and the scan electrode Y in the rising period of the reset period. The voltage is gradually increased from the voltage Vs to the voltage Vset, and the voltage of the scan electrode Y is gradually decreased from the voltage Vs to the voltage Vnf in the falling period of the reset period.

A transistor Ynp having a drain connected to the source of the transistor Yrr having a drain connected to the power supply Vset-Vs supplying the voltage (Vset-Vs) and a drain connected to the source of the transistor Yrr The source of is connected to the scan electrode (Y). A source of the transistor Ypp having a drain connected to the source of the transistor Yrr is connected to a contact point of the transistor Ys and the transistor Yg. One end of the capacitor Cset is connected to the power supply Vset-Vs and the other end is connected to the source of the transistor Ypp. This capacitor Cset is charged to the voltage (Vset-Vs) when the transistor Yg is turned on. In addition, the diode Dset is connected in the opposite direction to the body diode of the transistor Yrr between the drain of the transistor Yrr and the power supply Vset-Vs to block current caused by the body diode of the transistor Yrr.

The transistor Yfr is connected between the power supply Vnf supplying the Vnf voltage and the scan electrode Y of the panel capacitor Cp. The Vnf voltage applying control unit 422 controls the on / off of the transistor Yfr to selectively supply the Vnf voltage to the scan electrode Y. Here, the Vnf voltage and the VscL voltage are generated by the power supply device (600 in FIG. 2) and input to the scan electrode driver 400, and the Vnf voltage is a predetermined level (ΔV) higher than the VscL voltage. Thus, when the transistor YscL is turned on, a current path may be formed through the body diode of the transistor Yfr. Therefore, to block the current path through the body diode of the transistor Yfr, the transistor Yfr may be formed in a back-to-back form as shown.

The scan driver 430 includes a selection circuit 431, a capacitor CscH, a diode DscH, a transistor YscL, and a VscL voltage application control circuit 432, and scans to select a discharge cell to be turned on in an address period. The VscL voltage is applied to the electrode Y, and the VscH voltage is applied to the scan electrode Y of the discharge cell that will not be turned on. In general, a selection circuit 431 is connected to each scan electrode Y (Y1 to Yn) in the form of an IC so that the plurality of scan electrodes Y (Y1 to Yn) can be sequentially selected in the address period. The driving circuit of the scan electrode driver 400 is commonly connected to the scan electrodes Y (Y1-Yn) through the selection circuit 431. In FIG. 4, only the selection circuit 431 is illustrated in one scan electrode Y and one corresponding thereto.

The selection circuit 431 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the scan electrode Y of the panel capacitor Cp. One end of the capacitor CscH is connected to the contact point of the source of the transistor Scl and the drain of the transistor YscL, and the other end thereof is connected to the drain of the transistor Sch. The transistor YscL is connected between the power supply VscL and the scan electrode Y of the panel capacitor Cp, and the cathode of the diode DscH whose anode is connected to the power supply VscH supplying the VscH voltage is a transistor ( It is connected to the drain of Sch. Here, the capacitor CscH is charged with the voltages VscH-VscL when the transistor YscL is turned on. The VscL voltage application control unit 432 controls the on / off of the transistor YscL to selectively supply the VscL voltage to the scan electrode Y.

In FIG. 4, each transistor Ys, Yg, Yrr, YscL, Sch, Scl, Ynp, and Ypp is illustrated as one transistor, but each transistor Ys, Yg, Yrr, YscL, Sch, Scl, Ynp, and Ypp is illustrated as one transistor. ) May be formed of one transistor or a plurality of transistors connected in parallel.

The scan electrode driver 400 according to the exemplary embodiment of the present invention illustrated in FIG. 4 includes a Vnf voltage application control circuit 422 unlike a conventional VscL voltage generating unit and a Vnf voltage using a Zener diode. Through this, the transistor Yfr is controlled to supply the Vnf voltage to the scan electrode Y. Therefore, there is an advantage in that the implementation cost of the plasma display device and the driving power consumption of the plasma display device can be greatly reduced due to the use of a zener diode having a large voltage withstand voltage. In addition, since the Vnf voltage is separately generated by the power supply (600 in FIG. 2), the Vnf voltage may be changed through an external input.

In addition, the scan electrode driver 400 according to an exemplary embodiment of the present invention shown in FIG. 4 may also be used as the sustain electrode driver (500 of FIG. 1) for driving the sustain electrode (X).

Hereinafter, a method of generating the driving waveform of FIG. 2 will be described with reference to FIGS. 5A to 5C. Only the voltage applied to the scan electrode Y from the reset period to the address period in the driving waveform of FIG. 3 will be described.

5A and 5B are views illustrating an operation process for generating a drive waveform in a rising period and a falling period of a reset period among the driving waveforms of FIG. 3, respectively, and FIG. 5C is a view of driving in an address period among the driving waveforms of FIG. 3. A diagram illustrating an operation process for generating a waveform. First, it is assumed that before the operation of FIG. 5A, the transistors Yg, Ypp, Ynp, and Scl are turned on so that a 0 V voltage is applied to the scan electrode Y of the panel capacitor Cp.

First, referring to FIG. 5A, in the rising period of the reset period, the transistor Ys is turned on and the transistor Yg is turned off, from the power supply Vs to the transistor Ys, the body diode of the transistor Ypp, and the transistor Ynp. And a voltage Vs is applied to the scan electrode Y through a current path formed by the panel capacitor Cp through the body diode of the transistor Scl (1).

Subsequently, the transistor Yrr is turned on and the transistor Ypp is turned off, so that the body diodes of the transistor Ys, the capacitor Cset, the transistor Yrr, the transistor Ynp and the transistor Scl from the power supply Vs. Through the current path formed through the panel capacitor Cp, the voltage of the scan electrode Y is gradually increased to the voltage Vset (2).

Next, referring to FIG. 5B, in the falling period of the reset period, the transistor scl and the transistor Ypp are turned on, and the transistor Ys and the transistor Yrr are turned off, so that the transistor Scl from the panel capacitor Cp is turned off. ), The voltage Vs is applied to the scan electrode Y through a current path formed through the body diode of the transistor Ynp, the transistor Ypp and the body diode of the transistor Ys to the power supply Vs (3).

Subsequently, the transistor Yfr is turned on and the transistor Ypp is turned off so that the voltage of the scan electrode Y is the Vnf voltage through the current path from the panel capacitor Cp to the power supply Vnf through the transistor Yfr. It is gradually decreased until (④).

Referring to FIG. 5C, only the transistor Sch is turned on in order to apply the VscH voltage to the scan electrode Y in the address period, and the panel capacitor (VscH) through the diode DscH and the transistor Sch is turned on. The VscH voltage is applied to the scan electrode Y through the current path formed by Cp) (5).

Subsequently, in order to apply the VscL voltage to the scan electrode Y, the transistors Scl and YscL are turned on and the transistors Sch are turned off, so that the transistors Scl and transistors C1 from the panel capacitor Cp are turned on. The voltage of the scan electrode Y drops to the VscL voltage through the current path formed through the YscL to the power source VscL (6).

Hereinafter, a driving circuit of a scan electrode driver according to another exemplary embodiment of the present invention will be described with reference to FIG. 6. According to another embodiment of the present invention, only the Vnf voltage generation circuit applied to the scan electrode Y is different from the driving circuit according to the exemplary embodiment of the present invention shown in FIG. do.

6 illustrates a Vnf voltage generating circuit according to another embodiment of the present invention.

As shown in FIG. 6, the Vnf voltage generation circuit according to another embodiment of the present invention includes resistors R1 and R2, a gate driving circuit 423, a capacitor C1, and a transistor Yfr.

The resistor R1 is connected at one end to the power supply V1 supplying the voltage V1 and at the other end thereof to the gate driving circuit 423. The resistor R2 is a variable resistor capable of changing a resistance value, one end of which is connected to the other end of the resistor R1 and the other end of which is connected to a power supply VscL supplying a VscL voltage. The transistor Yfr is driven on / off by a control signal input from the gate driving circuit 423, and a drain is connected to the scan electrode Y and a source is connected to one end of the resistor R2. One end of the capacitor C1 is connected to the drain of the transistor Yfr and one end of the resistor R2, and the other end thereof is connected to the power supply VscL.

Here, the voltage V1 is generated and supplied by the power supply device 600 of FIG. 1, is a voltage higher than the VscL voltage by a predetermined level, and the resistance value of the resistor R2 is a control signal input from the controller 200 of FIG. 2. Will change accordingly.

Meanwhile, unlike FIG. 6, instead of the resistor R2, the resistor R1 may be a variable resistor whose resistance value is changed according to a control signal input from the control unit 200 of FIG. 2. The resistor R2 and both resistors may be variable resistors whose resistance value is changed according to a control signal input from the control unit 200 of FIG. 2.

When the transistor Yfr is turned on under the control of the gate driving circuit 423, current flows from the scan electrode Y through the current path from the scan electrode Y to the power supply VscL through the transistor Yfr and the capacitor C1. Therefore, the voltage level of the scan electrode Y becomes the voltage charged in the capacitor C1, that is, the voltage Vnf. As the resistance value of the resistor R2 is changed, the voltage Vnf, which is the voltage charged in the capacitor C1, is also changed, thereby changing the voltage Vnf in response to the design compatibility and the discharge margin of the plasma display device.

By varying the Vnf voltage to increase the voltage difference ΔV between the VscL and Vnf voltages, the discharge margin can be sufficiently secured during the address period, thereby lowering the address discharge voltage to a predetermined level or less, thereby driving the low power driving of the plasma display device. effective.

Hereinafter, a power supply device that generates the Vnf voltage shown in FIG. 4 and the V1 voltage shown in FIG. 6 will be described with reference to FIG.

7 is a view showing a power supply according to an embodiment of the present invention.

As shown in FIG. 7, the power supply device 600 according to the embodiment of the present invention includes a power supply unit 610, a VscL voltage generator 620, a V1 voltage generator 630, and a feedback signal generator 640. ), A switching controller 650, and a Vnf voltage generator 660.

The power supply unit 610 includes a primary coil L1 of a transformer and a switching transistor Qsw connected to the primary coil. The power supply unit 610 receives the Vs voltage and supplies power to the secondary side of the transformer, that is, the VscL voltage generator 620 and the V1 voltage generator 630 according to the duty of the switching transistor Qsw.

The VscL voltage generator 620 includes a secondary coil L2 of the transformer and a diode D1 having an anode connected to one end of the secondary coil L2, and one end of which is connected to the cathode of the diode D1 and the other end of the resistor ( A capacitor C2 connected to the other end of R3), one end of which is connected to the diode D1 and the contact point of the capacitor C1, and the other end of the resistor R3 connected to the other end of the capacitor C2.

The VscL voltage generator 620 is a voltage generated from the first coil L1 by the on / off of the switching transistor Qsw by using the diode D1 and the capacitor C1 to be generated in the second coil L2. Is converted into a DC voltage, and the Vccf voltage is output to one end of the resistor R3 using the same, and the VscL voltage is output to the other end of the resistor R3. That is, among the voltages applied across the resistor R4, the high voltage is the Vccf voltage and the low voltage is the VscL voltage. Here, the Vccf voltage is a drive voltage for driving the address electrode driver (300 in FIG. 1), the scan electrode driver (400 in FIG. 1) and the sustain electrode driver (500 in FIG. 1).

The V1 voltage generator 630 is for generating a V1 voltage used in the Vnf voltage generating circuit according to another embodiment of the present invention shown in FIG. 6, and the secondary coil L3 and the secondary coil L3 of the transformer are generated. One end of the diode includes a diode (D2) and a capacitor (C3) is connected between the cathode and the ground of the diode (D2). Here, the voltage applied across the capacitor C3 is the voltage V1.

The feedback signal generator 640 is connected to the output terminals of the VscL voltage generator 620 and the V1 voltage generator 630, and outputs an output voltage output to the VscL voltage generator 620 and the V1 voltage generator 630. It receives the input and generates a feedback signal.

The switching controller 650 receives the feedback signal generated by the feedback signal generator 640 and controls the on / off of the switching transistor Qsw included in the power supply 610 to scan the scan voltage generator 620 and the scan. The output voltage of the electrode driver driving voltage generator 630 is precisely controlled.

The Vnf voltage generator 660 includes resistors R3, R4 and R5, zener diodes ZD2 and ZD3, a transistor Q1, and a capacitor C4.

One end of the resistor R3 is connected to the output terminal of the V1 voltage generator 630 and the other end thereof is connected to the control electrode of the transistor Q1. One end of the resistor R4 is connected to the output terminal of the V1 voltage generator 630 and the other end thereof is connected to the drain of the transistor Q1. The resistor R5 is a variable resistor capable of changing a resistance value, one end of which is connected to the other end of the resistor R3 and the other end of which is connected to the VscL voltage output terminal of the VscL voltage generator 620. Zener diode ZD2 has a cathode connected between a resistor R3 and a contact of resistor R5 and a control electrode of transistor Q1 and an anode connected to a source of transistor Q1. The transistor Q1 has a drain connected to the resistor R4 and a source connected to the cathode of the zener diode ZD3. Zener diode ZD3 has an anode connected to one end of capacitor C4, and one end of capacitor C4 connected to a Vnf voltage output terminal and the other end to a VscL voltage output terminal of VscL voltage generator 620.

 As the resistance of the variable resistor R5 is changed, the voltage applied to the control electrode of the transistor Q1 is changed, thereby controlling whether the Vnf voltage is generated by controlling the on / off of the transistor Q1. In addition, the level of the output Vnf voltage is adjusted. The voltage Vnf increases in proportion to the resistance value of the resistor R5. When the transistor Q1 is turned on, a Vnf voltage lower than a predetermined level with respect to the voltage V1 and proportional to the resistance value of the resistor R5 is output through the Vnf voltage output terminal.

On the other hand, unlike shown in FIG. 7, instead of the resistor R5, the resistor R3 may be a variable resistor whose resistance value is changed according to a control signal input from the control unit 200 of FIG. 2. The resistor R5 and both resistors may be variable resistors whose resistance value is changed in accordance with a control signal input from the controller 200 of FIG. 2.

Here, the zener diode ZD2 is for preventing malfunction or breakage of the transistor Q1 as the voltage input to the control electrode of the transistor Q1 exceeds a predetermined level, and the zener diode ZD3 is This is to prevent the level of the voltage input to the control electrode of the transistor Q1 from falling below a predetermined level. To this end, the Zener diodes ZD2 and ZD3 have a low breakdown voltage within several tens of volts, and unlike Zener diodes of the prior art having a high breakdown voltage, the implementation cost of the plasma display device and the driving power consumption of the plasma display device are different. Does not increase.

As described above, as the resistance value of the resistor R5 is changed, the Vnf voltage output from the power supply device (600 in FIG. 1) is also changed, thereby changing the Vnf voltage in response to the design compatibility and the discharge margin of the plasma display device. Can change. By varying the Vnf voltage to increase the voltage difference ΔV between the VscL and Vnf voltages, the discharge margin can be sufficiently secured during the address period, thereby lowering the address discharge voltage to a predetermined level or less, thereby driving the low power driving of the plasma display device. effective.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to an aspect of the present invention, the Zener diode having a large breakdown voltage can be removed to reduce the implementation cost of the plasma display device and the driving power consumption of the plasma display device.

Also, by changing the Vnf voltage, the voltage difference ΔV, which is a voltage difference between the VscL voltage and the Vnf voltage, can be adjusted in response to the design compatibility and the discharge margin of the plasma display device, thereby sufficiently securing the discharge margin in the address period, thereby increasing the address discharge voltage. It can be lowered below a predetermined level, which is effective for low power driving of the plasma display device.

Claims (8)

A driving apparatus of a plasma display device comprising a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes. A first switch connected to a first power supply for supplying a first voltage applied to the first electrode at the end of a reset period, and a second switch connected to the first electrode and the first switch turned on A first voltage supply unit including a first switching control unit to control on / off; A second switch in which a first stage is sequentially applied to the plurality of first electrodes in an address period and connected to a second power supply for supplying a second voltage lower than the first voltage and a second stage is connected to the first electrode And a second switching controller configured to control on / off of the second switch. A driving device of the plasma display device comprising a. A driving apparatus for operating a plasma display device including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes under control of a controller. A first resistor, one end of which is connected to a first power source for supplying a first voltage; A second resistor having one end connected to the other end of the first resistor and the other end connected to a second power supply for supplying a second voltage lower than the first voltage; A first capacitor having one end connected to a first point, which is a contact point of the first and second resistors, and the other end connected to the second power source; The first terminal is connected to the first electrode and the second terminal is connected to the first point, and when turned on, the third voltage charged to the first capacitor in response to the resistance value of the second resistor is the first voltage. A first switch applied to the electrode; A switching controller controlling on / off of the first switch in response to the voltage level of the first point And at least one of the first and second resistors is a variable resistor. The method of claim 2, And the first switch is turned on in a reset period and is turned off at a time point when the address period starts. The method of claim 2, And the second voltage is an address data voltage sequentially applied to the plurality of first electrodes in an address period. A power supply apparatus for a plasma display device comprising a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes. A converter configured to convert an input voltage to generate a first voltage and a second voltage lower than the first voltage; and A voltage converter configured to apply a third voltage generated by stepping down the first voltage to the first electrode, The voltage converter, First and second resistors connected in series between the output terminals of the first and second voltages; A switch having a control electrode connected to the contacts of the first and second resistors and a first end connected to an output end of the first voltage; A capacitor having one end connected to a second end of the switch and the other end connected to an output end of the second voltage; and An output terminal connected to a second terminal of the switch to output the third voltage charged in the capacitor, wherein the third voltage is changed in response to a change in the resistance value of at least one of the first and second resistors. Power supply of plasma display device. The method of claim 5, And a zener diode having a cathode connected to the second end of the switch and an anode connected to one end of the capacitor. The method of claim 5, And a first zener diode having a cathode connected to the control electrode of the switch and an anode connected to the second end of the switch. The method of claim 5, And the second voltage is an address data voltage sequentially applied to the plurality of first electrodes in an address period.

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