KR20080040478A - Liquid crystal display panel and manufacturing method thereof - Google Patents

Abstract

An LCD panel and a manufacturing method thereof are provided to reduce transmittance loss of light generated in a backlight unit, thereby improving an aperture ratio and preventing instant afterimages. An LCD(Liquid Crystal Display) panel comprises a color filter substrate, a TFT(Thin Film Transistor) substrate and an LC. The TFT substrate comprises the following parts. A gate line(23) and a data line(25) define a pixel area by crossing each other. A gate electrode(33) is electrically connected with the gate line. An active layer is overlapped with the gate electrode with a gate insulating layer between active layers. A source electrode(27) is electrically connected with the data line. A drain electrode(31) faces the source electrode, and is overlapped with a part of the active layer. A pixel electrode(17) is disposed in the pixel area, and connected with the drain electrode. A storage electrode forms a storage capacitor by being overlapped with the drain electrode. The drain electrode comprises a central drain electrode(65) disposed in the center of the pixel area to divide the pixel area into two areas, and a drain connection electrode(63) connected with the central drain electrode. The pixel electrode is divided into first and second pixel electrodes(9,15). The first pixel electrode is disposed in an upper part of one side of the central drain electrode. The second pixel electrode is disposed in an upper part of the other side. The storage electrode comprises a central storage electrode(35) overlapped with the central drain electrode. To improve an aperture ratio, an area for forming the storage capacitor by overlapping a central storage electrode with a central drain electrode is reduced.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a cross section taken along the line II ′ of FIG. 1.

3 to 6 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

7 and 8 are cross-sectional views illustrating a method of manufacturing a color filter substrate according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1: black matrix 3: first incision pattern

5: common electrode 7: storage electrode line

9: first pixel electrode 11: second connection electrode

13: first connection electrode 15: second pixel electrode

17: pixel electrode portion 19: second incision pattern

23: gate line 25: data line

27: source electrode 29: ohmic contact layer

31: drain electrode 33: gate electrode

35: central storage electrode 37: contact hole

41: liquid crystal 43: color filter substrate

45: thin film transistor substrate 47: active layer

51: storage connection electrode 53: planarization film

55: color filter 57: thin film transistor

59: protective film 61: gate insulating film

63: drain connection electrode 65: center drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display panel and a method of manufacturing the same, which can achieve a high quality screen by increasing the aperture ratio.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel for displaying an image, a driving circuit for driving the liquid crystal display panel, and a back light unit for irradiating light to the liquid crystal panel.

The liquid crystal display panel includes a gate line GL and a data line DL that cross each other, a liquid crystal cell Clc formed in a pixel region defined by an intersection of the gate line GL and the data line DL, and a liquid crystal cell thereof. A thin film transistor (TFT) for driving (Clc) is provided.

The liquid crystal cell Clc is formed such that a pixel electrode connected to the thin film transistor TFT and a common electrode formed on the upper substrate face each other with a liquid crystal interposed therebetween. The liquid crystal molecules having dielectric anisotropy are rotated according to the voltage charged in the liquid crystal cell Clc, thereby controlling grayscale.

The driving circuit includes a plurality of data integrated circuits for driving a plurality of data lines and a plurality of gate integrated circuits for driving a plurality of gate lines.

Since the liquid crystal display panel implements an image by transmitting light only in a direction that is not shielded by the liquid crystal, a viewing angle is relatively narrower than that of other display devices. In order to compensate for this drawback, a patterned vertical alignment (PVA) mode in which one pixel area is divided into a plurality of pixel areas and one or more holes are formed on a common electrode corresponding to the plurality of pixel areas is proposed. However, since the liquid crystal display panel of the PVA mode has a structure in which contact and storage are formed at the center portion of the pixel region where light passes to form multiple domains, the drain electrode is extended from the channel portion to the center portion. Stretched. Therefore, there is a problem in that the aperture ratio is reduced due to the blocking of light by the contact and storage forming portions of the center portion of the pixel region and the drain electrode passing through the center of the pixel region.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same that can improve the display quality of a PVA liquid crystal display panel.

According to an aspect of the present invention, a liquid crystal display panel includes a thin film transistor substrate formed to face a color filter substrate and the color filter substrate, and a liquid crystal formed between the color filter substrate and the thin film transistor substrate.

The thin film transistor substrate is electrically connected to the active layer and the data line overlapping the gate electrode with a gate line and a data line intersecting each other to define a pixel region, a gate electrode electrically connected to the gate line, and a gate insulating layer interposed therebetween. A storage electrode and a drain electrode facing the source electrode and the source electrode connected to each other, the drain electrode overlapping a portion of the active layer, a pixel electrode disposed in the pixel region, the pixel electrode connected to the drain electrode, the drain electrode, and a storage capacitor; The electrode may include a center drain electrode which divides the pixel region and a drain connection electrode which is connected to the center drain electrode. The pixel electrode may be divided into a first upper portion on one side of the center drain electrode. Pixel electrode is located The second pixel electrode is positioned above the other side, and the storage electrode includes a central storage electrode overlapping the center drain electrode.

Here, the storage electrode preferably further includes a storage connection electrode.

In addition, the storage connection electrode and the drain connection electrode may be formed to overlap each other with an insulating layer therebetween.

In order to achieve the above technical problem, a method of manufacturing a liquid crystal display panel according to the present invention includes forming a black matrix and a color filter on a color filter substrate, and forming a flattening film and a common electrode on the substrate on which the color filter is formed. Forming a gate pattern including a gate electrode, a gate line, a central storage electrode, and a storage connection electrode on a transistor substrate; laminating a gate insulating layer on the substrate on which the gate pattern is formed; and forming an active layer and a source on the gate insulating layer. Forming an electrode, a drain electrode, a center drain electrode, and a drain connection electrode; laminating an organic passivation layer having contact holes on a substrate on which the source and drain electrodes are formed; and forming a pixel electrode and a connection electrode on the organic passivation layer. And the color filter substrate and the thin film substrate. And a step of laminating the substrate register.

In addition, the central storage electrode and the storage connection electrode are formed at the same time as the gate electrode and preferably formed of the same material.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a cross section taken along line II ′ of the liquid crystal display panel illustrated in FIG. 1.

1 and 2, the liquid crystal display panel according to the present invention includes a thin film transistor substrate 45 and a liquid crystal and color filter substrate 43.

The liquid crystal 41 is formed between the thin film transistor substrate 45 and the color filter substrate 43. The liquid crystal 4 rotates due to a difference between the data voltage from the pixel electrode portion 17 of the thin film transistor substrate 45 and the common voltage from the common electrode 5 of the color filter substrate 43. Therefore, the transmittance of light supplied from the backlight assembly (not shown) is adjusted. Here, the liquid crystal 41 uses a vertically aligned liquid crystal 41 having a negative dielectric constant.

The thin film transistor substrate 45 may include a gate line 23, a data line 25, a pixel region (not shown), a thin film transistor 57, a storage electrode line 7, a central storage electrode 35, and a storage connection electrode ( 51, a drain electrode 31, a protective film 59, and a pixel electrode part 17.

The gate line 23 has a material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, and is formed of a single layer or multiple layers. The gate line 23 supplies a scan signal from the gate driver to the gate electrode of the thin film transistor (TFT) 45.

The data line 25 has a material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Ti or Ti alloy, and is formed of a single layer or multiple layers. This data line 25 supplies a video signal from the data driver to the source electrode 31 of the thin film transistor 57.

The gate line 23 and the data line 25 are formed to cross each other to form a pixel area.

The thin film transistor 57 is formed in each pixel region. The thin film transistor 57 is formed of a gate electrode 33, a gate insulating film 61, an active layer 47, an ohmic contact layer 49, a source electrode 27, and a drain electrode 31.

The gate electrode 33 is formed on the gate line 23, and a portion of the gate electrode 33 protrudes from the gate line 23. The gate electrode 33 turns on and off the thin film transistor 57 using the gate on / off voltage transmitted through the gate line 23.

The gate insulating layer 61 is formed by depositing a material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the gate line 23 and the gate electrode 33 to form the gate line 23 and the gate electrode 33. Is electrically insulated.

The active layer 47 is formed of amorphous silicon or polysilicon to form a channel of the thin film transistor 57.

The ohmic contact layer 49 is formed for ohmic contact between the source electrode 27 and the drain electrode 31 and the active layer 47. To this end, the ohmic contact layer 49 is doped with impurities such as n + in the amorphous silicon.

The source electrode 27 is formed to protrude from one side of the data line 25 of the same material as the data line 25. The source electrode 27 supplies the data voltage from the data line 25 to the drain electrode 31 via the channel of the thin film transistor 57 when the thin film transistor 57 is turned on.

The drain electrode 31 is made of the same material as the data line 25, and one side thereof is formed to face the source electrode 27. The drain electrode 31 supplies the data voltage transmitted from the source electrode 27 to the pixel electrode portion 17 through the drain connection electrode 63.

The passivation layer 59 is formed of an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or the like, or an organic material such as acrylic, polyamide, or benzoclylobutene (BCB). The passivation layer 59 is formed to cover the thin film transistor 57 and the gate insulating layer 61, and electrically insulates the thin film transistor 57 from the pixel electrode part 17.

The pixel electrode part 17 is positioned in the pixel area formed by the intersection of the data line 25 and the gate line 23, and is made of a transparent conductive material having high transmittance and is formed on the passivation layer 59 to form the contact hole 37. It connects with the center drain electrode 65 via. The liquid crystal 41 is driven by forming an electric field with the common electrode 5 through the data voltage supplied from the center drain electrode 65 of the pixel electrode part 17.

Here, the pixel electrode portion 17 is divided into first and second pixel electrodes 9 and 15 in order to divide into two domains having an improved aperture ratio and a faster response speed. The divided first and second pixel electrodes 9 and 15 are formed in the same size in the shape of an ellipse by dividing the center of the long rectangular pixel area in the horizontal direction. In the pixel electrode unit 17, a first connection electrode 13 connecting the first and second pixel electrodes 9 and 15 is formed. In addition, the pixel electrode unit 17 further includes a second connection electrode 11 protruding from the first connection electrode 13.

The second connection electrode 11 protrudes from both sides of the first connection electrode 13, and is connected to the drain electrode 31 to supply a data voltage of the thin film transistor 57. Here, the second connection electrode 11 is connected to the drain electrode 31 through the contact hole 37. The second connection electrode 11 receives the data voltage from the drain electrode 31 and transfers the data voltage to each of the first and second pixel electrodes 9 and 15 through the first connection electrode 13.

The central storage electrode 35 is formed of the same material as the gate line 23 and is electrically connected to the gate line 23. The central storage electrode 35 overlaps the central drain electrode 65 connected to the drain electrode 31 of the thin film transistor 57 with the gate insulating layer 61 therebetween to form the storage capacitor CST.

The storage capacitor maintains the pixel voltage applied to the liquid crystal 41 for one frame until the pixel electrode portion 17 receives the next data voltage. In this way, the central storage electrode 35 and the central drain electrode 65 are formed in the pixel electrode part 17, thereby reducing the aperture ratio. Therefore, in order to increase the aperture ratio, the center storage electrode 35 and the center drain electrode 65 overlap with each other to form a storage capacitor. If the area of the central storage electrode 35 and the center drain electrode 65 is reduced, the capacity of the storage capacitor is also reduced. Therefore, to compensate for this, the drain connection electrode 63 and the storage connection electrode 51 passing through the center of the pixel are formed to overlap each other with the gate insulating layer 61 interposed therebetween. Therefore, the area where the central storage electrode 35 is reduced is the same as the area where the storage connection electrode 51 is formed. Since the drain connection electrode 63 may not transmit light and form a storage capacitor with the storage connection electrode 51, the drain connection electrode 63 may be used without reducing the aperture ratio and reducing the capacity of the storage capacitor. The storage capacitor formed by the drain connection electrode 63 and the storage connection electrode 51 has an effect of improving the aperture ratio as the area of the central storage electrode 35 and the central drain electrode 65 is reduced.

The color filter substrate 43 includes a black matrix 1, a color filter 55, a planarization film 53, and a common electrode 5 for applying a common voltage to the liquid crystal 41.

The black matrix 1 is formed of the thin film transistor 57, the gate line 23, the data line 25 and the thin film transistor substrate 45 of the thin film transistor substrate 45 to prevent light from being emitted through a region in which the liquid crystal 41 cannot be controlled. It overlaps with the storage electrode line 7. For this purpose, the black matrix 1 is formed of an opaque organic material or an opaque metal.

The color filter 55 is formed under the black matrix 1 and includes red, green, and blue color filters 55 to implement color. The red, green, and blue color filters 55 exhibit red, green, and blue colors by absorbing or transmitting light of a specific wavelength through the red, green, and blue pigments included therein, respectively. In this case, various colors are realized through additive color mixing of red, green, and blue light passing through the red, green, and blue color filters 55, respectively.

The planarization film 53 removes a step generated in the crossover region of the black matrix 1 and the color filter 55. In addition, it is formed of a transparent organic material and protects the color filter 55 and the black matrix 1, and is formed for good step coverage and insulation of the common electrode 5.

The common electrode 5 controls the movement of the liquid crystal 41. The common electrode 5 forms first and second cutout patterns 3 and 19 on the common electrode 5 corresponding to each of the first and second pixel electrodes 9 and 15. On the other hand, the liquid crystal 41 rotates facing the first and second incision patterns 3 and 19 due to the potential difference between the pixel electrode portion 17 and the common electrode 5.

Specifically, the common electrode 5 corresponds to the first and second pixel electrodes 9 and 15 of the thin film transistor substrate 45 so as to divide the domain into multiple domains. To form.

The first and second cutout patterns 3 and 19 are formed to overlap the centers of the first and second pixel electrodes 9 and 15. In this case, the first domain is defined by the first cutout pattern 3 and the first pixel electrode 9, and the second domain is defined by the second cutout pattern 19 and the second pixel electrode 15.

In the first and second cutout patterns 3 and 19, a fringe field is strongly formed at the edges thereof and the edges of the first and second pixel electrodes 9 and 15. Accordingly, the liquid crystal 41 is sequentially driven inward from the edges of the first and second incision patterns 3 and 19 having the fringe field formed therein and the edges of the first and second pixel electrodes 9 and 15. do.

Here, in order to improve the response speed of the liquid crystal 41, the same electric field must be formed between the edges of the first and second incision patterns 3 and 19 and the edges of the first and second pixel electrodes 9 and 15. do.

3 to 6 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3, chromium (Cr), aluminum (Al), copper (Cu), aluminum alloy (AlNd), molybdenum (Mo), and silver (Ag) on a thin film transistor substrate 45 made of an insulating material such as glass or ceramic. A single metal or alloy, such as N, is deposited using a sputtering or chemical vapor deposition (CVD) method, and a gate pattern is formed that includes a gate electrode 33, a central storage electrode 35, and a gate line 23.

Specifically, the gate line 23 is formed by patterning the gate metal layer deposited on the thin film transistor substrate 45 by a photolithography process and an etching process. A gate electrode 33 protruding from the gate line 23 is formed to define the thin film transistor 57. In addition, the storage electrode line 7 is formed in parallel with the gate line 23, and a central storage electrode 35 connected to the storage electrode line 7 is formed. Here, the central storage electrode 35 is formed to be elongated in the horizontal direction at the center of the long rectangular pixel area.

Next, as shown in FIG. 4, an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or the like is stacked on the entire surface of the thin film transistor substrate 43 having the gate pattern formed thereon by PECVD (Plasma Enhanced Chemical Vapor Deposion). Thus, the gate insulating film 61 is formed. Subsequently, the active layer 47 and the ohmic contact layer 49 are formed, and a single or an alloy thereof such as chromium (Cr), aluminum (Al), molybdenum (Mo), silver (Ag), titanium (Ti), or the like is formed. The metal is deposited to form a data pattern layer including the source electrode 27, the drain electrode 31, and the data line 25.

Specifically, an inorganic insulating material is deposited on the entire surface of the gate pattern layer to form the gate insulating layer 61. The amorphous silicon layer and the amorphous silicon layer doped with impurities are sequentially stacked in the same manner as the deposition method of the gate insulating layer 61. Subsequently, the amorphous silicon layer and the amorphous silicon layer doped with impurities are patterned by a photolithography process and an etching process to form a semiconductor pattern including the active layer 47 and the ohmic contact layer 49.

The data line 25, the source electrode 27, the drain electrode 31, and the data line 25 are formed on the gate insulating layer 61.

Specifically, the source / drain metal layer is formed on the gate insulating layer 61 by a deposition method such as sputtering. Therefore, as the source / drain metal layer, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or an alloy thereof is used as a single layer or a multilayer structure. The source / drain metal layer is patterned by a photolithography process and an etching process to form a data line 25, a source electrode 27, and a drain electrode 31. The source electrode 27 thus formed is patterned to protrude from the data line 25. One side of the drain electrode 31 is formed to overlap the gate electrode 33, and the other side of the drain electrode 31 is formed to overlap the first and storage connection electrodes 35 and 51. In order to overlap the first and storage connection electrodes 35 and 51 and the gate line 23, the drain electrode 31 is further formed with a signal line through which a data signal is transmitted to the center of the second pixel electrode 9.

Next, referring to FIG. 5, the thin film transistor 57 and data on the gate insulating layer 61 by a method such as plasma enhanced chemical vapor deposition (PECVD), spin coating, spinless coating, or the like. A protective film 59 is formed to protect and insulate the line 25. The protective film 59 is patterned by a photolithography process and an etching process to form a contact hole 37 exposing a portion of the drain electrode 31. Here, as the protective film 59, an inorganic insulating material such as the gate insulating film 61 is used, or an organic insulating material such as acrylic or the like is used.

Next, as illustrated in FIG. 6, the pixel electrode part 17 is formed on the passivation layer 59. Here, the pixel electrode portion 17 divides the pixel region to form first and second pixel electrodes 9 and 15. The pixel electrode unit 17 forms a first connection electrode 13 connecting the first and second pixel electrodes 9 and 15. In addition, the pixel electrode part 17 protrudes from the first connection electrode to form a second connection electrode 11 connected to the drain electrode 31 through the contact hole 37.

The pixel electrode part 17 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode part 17 may be patterned in a form of being divided into two parts in the pixel area after front coating, or may be partially coated so that only the first and second pixel electrodes 9 and 15 are formed.

7 and 8 are cross-sectional views illustrating a method of manufacturing a color filter substrate according to an exemplary embodiment of the present invention.

The color filter substrate 43 is formed from the top to the bottom on the color filter substrate 43 shown in FIG. 2 in the manufacturing process.

As illustrated in FIG. 7, an opaque organic material or an opaque metal is coated on the color filter substrate 43 and then patterned after the photolithography process to form the black matrix 1. After the black matrix 1 is formed, the color filter 55 is formed to implement color. The color filter 55 is formed in the order of red, green, and blue of the color filter 55 by a photolithography method or an inkjet method.

Next, as shown in FIG. 8, the planarization film 53 is formed on the surface of the color filter 55 for the protection of the color filter 55 and the good step coverage in forming the common electrode 5. The planarization film 53 forms an acrylic resin or the like by spin coating. The common electrode 5 is formed on the planarization film 53.

Specifically, the common electrode 5 is formed of a transparent conductive material such as ITO or IZO. The common electrode 5 forms the first and second incision patterns 3 and 19 corresponding to the first and second pixel electrodes 9 and 15 of the thin film transistor substrate 45 to divide the domain into multiple domains. do. The first and second cutout patterns 3 and 19 are formed to overlap the centers of the first and second pixel electrodes 9 and 15. In this case, a first domain is formed by the first cutout pattern 3 and the first pixel electrode 9, and a second domain is formed by the second cutout pattern 19 and the second pixel electrode 15.

The thin film transistor substrate 45 and the color filter substrate 43 are bonded to each other.

As described above, the liquid crystal display panel according to the present invention reduces the area where the center drain electrode and the center storage electrode overlapping the central storage electrode, which are located at the center portion that divides one pixel into two pixel regions, to form a storage capacitor and the reduced area. The silver overlaps with the drain connection electrode portion through which light cannot pass. Therefore, the transmission loss of the light generated by the backlight unit can be reduced to solve the high aperture ratio and the afterimage problem.

In the detailed description of the invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Claims (5)

A color filter substrate; A thin film transistor substrate formed to face the color filter substrate; A liquid crystal formed between the color filter substrate and the thin film transistor substrate, The thin film transistor substrate is; A gate line and a data line crossing each other to define a pixel area; A gate electrode electrically connected to the gate line; An active layer overlapping the gate electrode with a gate insulating layer interposed therebetween; A source electrode electrically connected to the data line; A drain electrode facing the source electrode and overlapping a portion of the active layer; A pixel electrode positioned in the pixel area and connected to the drain electrode; A storage electrode forming a storage capacitor with the drain electrode; The drain electrode includes a center drain electrode positioned at the center of the pixel region and dividing the pixel region and a drain connection electrode connected to the center drain electrode; The pixel electrode is bisected so that a first pixel electrode is positioned on one side of the center drain electrode and a second pixel electrode is positioned on the other side; And the storage electrode includes a central storage electrode overlapping the center drain electrode. The method of claim 1, The storage electrode further comprises a storage connection electrode. The method of claim 2, And the storage connection electrode and the drain connection electrode overlap each other with an insulating layer therebetween. Forming a black matrix, color filter on the color filter substrate; Forming a planarization layer and a common electrode on the substrate on which the color filter is formed; And Forming a gate pattern including a gate electrode, a gate line, a central storage electrode, and a storage connection electrode on the thin film transistor substrate; Stacking a gate insulating film on the substrate on which the gate pattern is formed; Forming an active layer, a source electrode, a drain electrode, a center drain electrode, and a drain connection electrode on the gate insulating layer; Stacking an organic passivation layer having a contact hole on the substrate on which the source and drain electrodes are formed; Forming a pixel electrode and a connection electrode on the organic passivation layer; And bonding the color filter substrate and the thin film transistor substrate to each other. The method of claim 4, wherein And the central storage electrode and the storage connection electrode are formed at the same time as the gate electrode and formed of the same material.

Images