KR20060015209A - Array substrate, manufacturing method thereof, and liquid crystal display having the same - Google Patents

Abstract

An array substrate for realizing a multi-domain, a manufacturing method thereof, and a display device having the same are disclosed. The array substrate includes a switching element and a pixel electrode portion. The switching element is formed in the pixel region of the substrate, and the pixel electrode portion has an open pattern shape facing in different directions in the pixel region, and is electrically connected to the switching element. Accordingly, the multi-domain can be realized by patterning the pixel electrode layer of the array substrate and not patterning the common electrode layer of the opposing substrate. In particular, by patterning so as to define a radial shape with respect to the center of the pixel electrode layer, a multi-domain can be realized.

Pixel electrode, pattern, patterning, VA, PVA, reflector, swirl

Description

An array substrate, a method of manufacturing the same, and a display device having the same {ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY HAVING THE SAME}

1 is a plan view of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3A and 3B are cross-sectional views schematically illustrating an operation of a liquid crystal panel according to the present invention.

4A through 4D are plan views illustrating a method of manufacturing the array substrate of FIG. 1.

FIG. 5A is a simulation diagram for schematically describing an operation of a liquid crystal panel according to a first exemplary embodiment of the present invention in a unit pixel area, and FIG. 5B is a waveform diagram illustrating a voltage felt by the liquid crystal layer corresponding to FIG. 5A.

6 is a plan view of an array substrate according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line II-II ′ of FIG. 6.

8A to 8D are diagrams for describing a method of manufacturing the array substrate of FIG. 6.

FIG. 9A is a simulation diagram for schematically describing an operation of a liquid crystal panel according to a second exemplary embodiment of the present invention in a unit pixel area, and FIG. 9B is a waveform diagram illustrating a voltage felt by the liquid crystal layer corresponding to FIG. 9A.

10 is a plan view of an array substrate according to a third embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line III-III ′ of FIG. 10.

12A to 12F are diagrams for describing a method of manufacturing the array substrate of FIG. 10.

13 is a plan view of an array substrate according to a fourth embodiment of the present invention.

14 is a plan view of an array substrate according to a fifth embodiment of the present invention.

15 is a plan view of an array substrate according to a sixth embodiment of the present invention.

16 is a plan view of an array substrate according to a seventh embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: array substrate 110: gate wiring

112: gate electrode 120: source wiring

122 source electrode 124 drain electrode

140: pixel electrode portions 141, 143, 145: connection electrode

142, 144, 146: Sub electrode 200: Liquid crystal layer

300: color filter substrate 310: color pixel layer

320: common electrode layer

The present invention relates to a display device, and more particularly, to an array substrate, a manufacturing method thereof, and a display device having the same.

In general, an LCD includes an array substrate (or TFT substrate) on which a thin film transistor (TFT) for switching each pixel is formed, an opposing substrate (or color filter substrate) on which a common electrode is formed, and a liquid crystal layer sealed between the two substrates. It is composed. The liquid crystal display displays an image by applying a voltage to the liquid crystal layer to control light transmittance.

Since the liquid crystal display implements an image by transmitting light only in a direction that is not shielded by the liquid crystal, a view angle is relatively narrower than that of other display devices. Accordingly, in order to realize a wide viewing angle, a liquid crystal display device having a vertically aligned mode has been developed.

The VA mode liquid crystal display is composed of two substrates vertically aligned on opposite surfaces, and a liquid crystal having a negative type dielectric constant anisotropy sealed between the two substrates. The molecules of the liquid crystal have a property of homeotropic orientation.

In operation, when no voltage is applied between the two substrates, they are aligned vertically with respect to the substrate surface to display black, and when a predetermined voltage is applied, they are aligned in a substantially horizontal direction to the substrate surface and are white. white is displayed, and when a voltage smaller than the voltage for the white display is applied, it is oriented so as to be inclined obliquely with respect to the surface of the substrate to display gray.

On the other hand, a liquid crystal display generally employing a PVA mode has a common electrode layer patterned on a color filter substrate and a pixel electrode layer patterned on an array substrate in order to define a multi-domain.

Narrow viewing angles or gray level inversion are a problem to be solved in liquid crystal displays, particularly small and medium-sized liquid crystal displays. In order to solve this problem, relatively small and medium-sized liquid crystal displays use a patterned vertical alignment (PVA) structure.

Therefore, a PVA structure suitable for small and medium-sized devices is a structure in which an ITO patterning process should be performed on the array substrate and the color filter substrate, respectively. This is a problem that a process such as a photo process, a developing process, an etching process, a PR strip process, etc. in order to separately pattern the ITO layer during the color filter process.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide an array substrate for realizing a multi-domain.

In addition, another object of the present invention is to provide a method of manufacturing the above-described array substrate.

Further, another object of the present invention is to provide a display device having the above-described array substrate.

An array substrate according to one feature for realizing the above object of the present invention includes a substrate, a switching element, and a pixel electrode portion. The substrate has a pixel region, the switching element is formed in the pixel region, and the pixel electrode portion is electrically connected to the switching element, having a pattern shape that opens in a different direction in the pixel region.

According to one aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: (a) forming a gate wiring, a source wiring, and a switching element connected to the gate wiring and the source wiring in a unit pixel region; step; And (b) forming a pixel electrode layer connected to the switching element, having a pattern shape opened in different directions to define domains of a plurality of liquid crystals in the unit pixel region.

According to an aspect of the present invention, a display device includes an upper substrate, a liquid crystal layer, and a lower substrate. The upper substrate includes a common electrode layer, and the lower substrate receives the liquid crystal layer through coalescence with the upper substrate, and faces different directions to define a plurality of domains through connection with the common electrode layer. A pixel electrode portion having an open pattern shape is provided.

According to such an array substrate, a method of manufacturing the same, and a display device having the same, a multi-domain can be realized by patterning a pixel electrode layer of an array substrate and not patterning a common electrode layer of an opposite substrate. In particular, by patterning to define a radial shape with respect to the center of the pixel electrode layer, multi-domains can be realized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. As described in the drawing, when it is described from an observer's point of view, when a part such as a layer, a film, an area, or a plate is "on" another part, it is not only when another part is "directly" but also another part in between. It also includes the case. On the contrary, when a part is "just above" another part, it means that there is no other part in the middle.

Example-1

1 is a plan view of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. In particular, a transmissive array substrate is shown.

1 and 2, the liquid crystal display according to the first exemplary embodiment of the present invention may be formed by integrating the array substrate 100, the liquid crystal layer 200, and the array substrate 100. And a color filter substrate 300 accommodating 200.

The array substrate 100 is spaced apart from the gate wiring 110 extending in the horizontal direction on the transparent substrate 105, the gate electrode 112 extending from the gate wiring 110, and the gate wiring 110. The gate insulating layer 113 covering the gate wiring 110 and the gate electrode 112 is formed of a material such as an open lower pattern 111 and silicon nitride (SiNx) to correspond to the center region of the unit pixel region. do.

The array substrate 100 includes a semiconductor layer 114 such as a-Si covering the gate electrode 112, a semiconductor impurity layer 115 such as n + a-Si formed on the semiconductor layer, and a lengthwise direction. The extended source wiring 120 includes a source electrode 122 extending from the source wiring 120, and a drain electrode 124 spaced apart from the source electrode 122 by a predetermined distance. The gate electrode 112, the semiconductor layer 114, the semiconductor impurity layer 115, the source electrode 122, and the drain electrode 124 define one thin film transistor TFT.

The gate wiring 110 or the source wiring 120 may be formed as a single layer or a double layer. When formed as the single layer, it may be formed of aluminum (Al) or aluminum (Al) -neodymium (Nd) alloy, and when formed as the double layer, such as chromium (Cr), molybdenum (Mo), or molybdenum alloy film A material having excellent physical / chemical properties of is formed as a lower layer, and a material having low specific resistance such as aluminum (Al) or aluminum alloy is formed as an upper layer.

The array substrate 100 includes a passivation layer 130 and an organic insulating layer 132 sequentially stacked to expose a portion of the drain electrode 126 while covering the thin film transistor TFT. The passivation layer 130 and the organic insulating layer 132 cover and protect the semiconductor layer 114 and the semiconductor impurity layer 115 between the source electrode 122 and the drain electrode 124. The thickness of the liquid crystal layer 200 may be adjusted by controlling the height of the organic insulating layer 132 by insulating the transistor TFT and the pixel electrode layer 140. Of course, the formation of the passivation layer 130 may be omitted.

The array substrate 100 is electrically connected to the drain electrode 124 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 140 having a pattern shape opened to face different directions. It includes. The pixel electrode unit 140 defines a capacitance of the storage capacitor Cst by an area overlapping the lower pattern 111.

In detail, the pixel electrode unit 140 extends from the first connection electrode 141 and the first connection electrode 141 contacting the drain electrode 124, and defines a rounded quadrangular shape. ), The second connection electrode 143 extending from the first sub-electrode 142 and the second sub-electrode 144 extending from the second connection electrode 143 and defining a rounded square shape with a relatively small width. The third sub-electrode 146 having a relatively small width and extending from the second sub-electrode 144 and the third sub-electrode 146 extending from the third sub-electrode 145 and defining a rounded square shape may be formed. Include.

Each of the first to third sub-electrodes 142, 144, and 146 is formed with a plurality of straight patterns 142a, 144a, and 144a that are opened in a radial shape at a center on a plane. In the drawing, 16 linear patterns are formed on each of the first to third sub-electrodes 142, 144, and 146.

Meanwhile, the color filter substrate 300 includes a color pixel layer 310 formed on the transparent substrate 305 corresponding to a unit pixel area, and a common electrode layer 320 formed on the color pixel layer 310. The liquid crystal layer 200 is accommodated through incorporation with the array substrate 100. The liquid crystals in the liquid crystal layer 200 are arranged in a vertical alignment (VA) mode.

When viewed in a plan view, 16 different domains are formed in each of the first to third sub-electrodes 142, 144, and 146 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction can be omitted, and the alignment film may not be formed.

As described in the first embodiment of the present invention, the pixel electrode portion of the array substrate is divided into three sub-electrodes, patterned to define a radial shape based on the center of the divided sub-electrodes, and the opposite substrate ( By not patterning the common electrode layer of the color filter substrate, as shown in FIGS. 3A and 3B described below, multi-domains can be realized in the unit pixel region.

3A and 3B are cross-sectional views schematically illustrating an operation of a liquid crystal panel according to the present invention, and particularly illustrate an alignment state of a liquid crystal in a unit pixel region. Here, the multi-domain may include an opening 142a formed between the first connection electrode 141 and the first sub electrode 142 of the array substrate 100, and the first sub electrode 142 and the second connection electrode 143. It is formed by the opening part 142a formed in the liver.

In the initial stage of driving, the liquid crystals oriented in the vertical direction with respect to the array substrate 100 are oriented in a shape in which liquid crystals lie down as the liquid crystals converge toward the opening, as shown in FIG. 3A. That is, the liquid crystal maintains vertical alignment while no voltage is applied, and while the voltage is applied, the liquid crystal is oriented while lying in a direction having a predetermined angle with the foreground line.

As time passes, as shown in FIG. 3B, the liquid crystal collects at one point (or opening) and rotates in the plane direction of the array substrate to display an image.

That is, by performing the patterning process only on the array substrate, it is possible to form a multi-domain of the liquid crystal without much drop in transmittance as compared with the general vertical alignment (VA) mode. In addition, an ITO-free region outside the pixel is used as a storage capacitor.

4A through 4D are plan views illustrating a method of manufacturing the array substrate of FIG. 1.

Referring to FIG. 4A, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or the like on a transparent substrate 105 made of an insulating material such as glass or ceramic. A metal such as tungsten (W) is deposited.

Subsequently, a plurality of gate lines 110 extending in a horizontal direction and arranged in a vertical direction by patterning the deposited metal and a lower portion having a pattern parallel to the gate lines and opening in a rounded rectangle in a unit pixel area The storage pattern 111 and the gate electrode 112 extending from the gate line 110 are defined to define the thin film transistor.

Subsequently, silicon nitride or the like is stacked on the entire surface of the substrate including the gate electrode 112 by plasma chemical vapor deposition to form a gate insulating layer 113. The gate insulating layer 113 may be formed on the entire surface of the transparent substrate 105, or may be patterned to cover the gate line 110 and the gate electrode 112.

As shown in FIG. 4B, forming an amorphous-silicon (a-Si) film and an insitu doped n + amorphous silicon (a-Si) film on the gate insulating layer 113 and defining a thin film transistor For example, a portion of the region is patterned to form the active layer 115 in the region where the gate electrode 112 is located.

Subsequently, metals such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or tungsten (W) are deposited. Subsequently, the deposited metal is patterned to form a plurality of source lines 120, source electrodes 122, and drain electrodes 124. The source electrode 122 extends from the source line 120, and the drain electrode 124 is patterned to be spaced apart from the source electrode 122 by a predetermined interval.

As shown in FIG. 4C, a passivation layer 130 and an organic insulating layer 132 are formed by stacking resist on the substrate on which the resultant substrate of FIG. 3B is formed by spin coating. Next, a portion of the passivation layer 130 and the organic insulating layer 132 is removed from the unit pixel area defined by the gate line 110 and the source line 120 to remove a portion of the drain electrode 124. A contact hole CNT is formed to be exposed.

As illustrated in FIG. 4D, the pixel electrode layer 140 connected to the drain electrode 124 is formed through the contact hole CNT while defining the pixel electrode portion in the unit pixel region.

In detail, the pixel electrode layer 140 extends from the first connection electrode 141 and the first connection electrode 141 contacting the drain electrode 124 and defines a rounded quadrangular shape. ), The second connection electrode 143 extending from the first sub-electrode 142 and the second sub-electrode 144 extending from the second connection electrode 143 and defining a rounded square shape with a relatively small width. The third sub-electrode 146 having a relatively small width and extending from the second sub-electrode 144 and the third sub-electrode 146 extending from the third sub-electrode 145 and defining a rounded square shape may be formed. Include.

The pixel electrode layer 140 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like. In this case, the pixel electrode layer 140 may be patterned such that only the pixel electrode layer corresponding to the unit pixel region is left after the entire surface is applied, or may be partially coated to be formed only in the unit pixel region. In the drawing, although the pixel electrode 140 is spaced apart from the gate line 110 and the source line 120 at a observer's point of view, the pixel electrode 140 may overlap with a minimum width.

1, each of the first to third sub-electrodes 142, 144, and 146 of the pixel electrode layer 140 formed in the unit pixel region is opened in a radial shape at the center of the plane. A plurality of straight line patterns 142a, 144a, and 144a are formed. In the drawing, 16 linear patterns are formed on each of the first to third sub-electrodes 142, 144, and 146. Removing some regions from each of the first to third sub-electrodes 142, 144, and 146 is to define a plurality of domains. In the drawings, a plurality of linear patterns 142a, 144a, and 144a are formed by forming a pixel electrode layer entirely in a unit pixel region and then removing a portion of the region through a patterning process, but this is separated for convenience of description. In addition, when forming the pixel electrode layer, it is preferable to simultaneously form a plurality of linear patterns 142a, 144a, and 144a.

FIG. 5A is a simulation diagram for schematically describing an operation of a liquid crystal panel according to a first exemplary embodiment of the present invention in a unit pixel area, and FIG. 5B is a waveform diagram illustrating a voltage felt by the liquid crystal layer corresponding to FIG. 5A.

As shown in FIG. 5A, the color filter substrate 300 has a common electrode layer 320 flat over the first transparent substrate 305, and the array substrate 100 has a second transparent substrate to define a multi-domain. The pixel electrode layer 140 has holes 142a formed thereon.

In operation, the first domain area DA1 is defined by the first connection electrode 141 and the first hole, and the second domain area DA2 is defined by the left side of the first hole and the first sub-electrode 142. The third domain area DA3 is defined by the right side and the second hole of the first sub electrode 142, and the fourth domain area DA4 is defined by the left side of the second hole and the second connection electrode 143. ) Is defined, and the fifth domain region DA5 is defined by the second connection electrode and the third hole. The voltage of the liquid crystal layer felt in the first to fifth domain regions DA1, DA2, DA3, DA4, and DA5 is as shown in FIG. 5B.

Example-2

6 is a plan view of an array substrate according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line II-II ′ of FIG. 6. In particular, a transmissive array substrate having a process formed in sub-pixel regions connected to each other is shown.

6 and 7, the liquid crystal display according to the second exemplary embodiment of the present invention includes an array substrate 400, a liquid crystal layer 200, and a combination of the liquid crystal layer and the array substrate 400. And a color filter substrate 300 accommodating 200.

The array substrate 400 is spaced apart from the gate wiring 410 extending in the horizontal direction on the transparent substrate 405, the gate electrode 412 extending from the gate wiring 410, and the gate wiring 410. The gate insulating layer 413 is formed of a material such as an open lower pattern 411, silicon nitride (SiNx), and the like to cover the gate wiring 410 and the gate electrode 412. .

The array substrate 400 includes a semiconductor layer 414 such as a-Si covering the gate electrode 412, a semiconductor impurity layer 415 such as n + a-Si formed on the semiconductor layer, and a lengthwise direction. An extended source wiring 420, a source electrode 422 extending from the source wiring 420, and a drain electrode 424 spaced apart from the source electrode 422 by a predetermined interval are included. The gate electrode 412, the semiconductor layer 414, the semiconductor impurity layer 415, the source electrode 422, and the drain electrode 424 define one thin film transistor TFT.

The gate wiring 410 or the source wiring 420 may be formed as a single layer or a double layer. When formed as the single layer, it may be formed of aluminum (Al) or aluminum (Al) -neodymium (Nd) alloy, and when formed as the double layer, such as chromium (Cr), molybdenum (Mo), or molybdenum alloy film A material having excellent physical / chemical properties of is formed as a lower layer, and a material having low specific resistance such as aluminum (Al) or aluminum alloy is formed as an upper layer.

The array substrate 400 includes a passivation layer 430 and an organic insulating layer 432 that are sequentially stacked to expose a portion of the drain electrode 426 while covering the thin film transistor TFT. The passivation layer 430 and the organic insulating layer 432 cover and protect the semiconductor layer 414 and the semiconductor impurity layer 415 between the source electrode 422 and the drain electrode 424. The thickness of the liquid crystal layer 200 may be adjusted by controlling the height of the organic insulating layer 432 by insulating the transistor TFT and the pixel electrode layer 440. Of course, the formation of the passivation layer 430 may be omitted.

The array substrate 400 is electrically connected to the drain electrode 424 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 440 having a pattern shape opened to face different directions. It includes. The pixel electrode part 440 defines a capacitance of the storage capacitor Cst by an area overlapping the lower pattern 411.

In detail, the pixel electrode part 440 extends from the first connection electrode 441 and the first connection electrode 441 which are in contact with the drain electrode 424, and defines a rounded quadrangular shape. ), The second connection electrode 443 extending from the first sub-electrode 442 and the second sub-electrode 444 extending from the second connection electrode 443 and defining a rounded quadrangular shape. The third sub-electrode 446 having a relatively small width extending from the second sub-electrode 444 and the third sub-electrode 446 extending from the third sub-electrode 445 and defining a rounded quadrangular shape is defined. Include.

Each of the first to third sub electrodes 442, 444, and 446 is provided with a plurality of straight line patterns 442a, 444a, and 444a that are radially opened at the center of the plane. In the drawing, 16 linear patterns are formed in each of the first to third sub-electrodes 442, 444, and 446. In addition, each of the first to third sub-electrodes 442, 444, and 446 includes first to third protrusion electrodes 442b, 444b, and 446b in the center area. Although the first to third protrusion electrodes 442b, 444b, and 446b are circular in shape, various shapes, such as a triangular shape and a square shape, may be used.

Meanwhile, the color filter substrate 300 includes a color pixel layer 310 formed on the transparent substrate 305 corresponding to a unit pixel area, and a common electrode layer 320 formed on the color pixel layer 310. The liquid crystal layer 200 is accommodated through the coalescence with the array substrate 400. The liquid crystals in the liquid crystal layer 200 are arranged in a vertical alignment (VA) mode.

When the LCD is viewed on a plane, 16 different domains are formed in each of the first to third sub electrodes 442, 444, and 446 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

8A to 8D are diagrams for describing a method of manufacturing the array substrate of FIG. 6.

Referring to FIG. 8A, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or the like on a transparent substrate 405 made of an insulating material such as glass or ceramic. A metal such as tungsten (W) is deposited. Subsequently, a plurality of gate lines 410 extending in the horizontal direction and arranged in the vertical direction by patterning the deposited metal, and a lower portion having a pattern parallel to the gate lines and opened in a rounded rectangle in the unit pixel region A storage pattern 411 and a gate electrode 412 extending from the gate line 410 are defined to define the thin film transistor.

Subsequently, silicon nitride or the like is stacked on the entire surface of the substrate including the gate electrode 412 by plasma chemical vapor deposition to form a gate insulating layer 413. The gate insulating layer 413 may be formed on the entire surface of the transparent substrate 405, or may be patterned to cover the gate line 410 and the gate electrode 412.

As shown in FIG. 8B, forming an amorphous-silicon (a-Si) film and an insitu doped n + amorphous silicon (a-Si) film on the gate insulating layer 413 and defining a thin film transistor For example, a portion of the region is patterned to form an active layer 415 in the region where the gate electrode 412 is located.

Subsequently, metals such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or tungsten (W) are deposited. Subsequently, the deposited metal is patterned to form a plurality of source lines 420, a source electrode 422, and a drain electrode 124. The source electrode 422 extends from the source line 420, and the drain electrode 424 is patterned to be spaced apart from the source electrode 422 by a predetermined interval.

As illustrated in FIG. 8C, a passivation layer 430 and an organic insulating layer 432 are formed by stacking resist on the substrate on which the resultant substrate of FIG. 8B is formed by spin coating. Subsequently, a portion of the drain electrode 424 is removed by removing a portion of the passivation layer 430 and the organic insulating layer 432 from the unit pixel area defined by the gate line 410 and the source line 420. The contact hole CNT to be exposed and the first to third protrusions 433, 435, and 437 having a relatively high height are formed.

As shown in FIG. 8D, the pixel electrode layer 440 connected to the drain electrode 424 is formed through the contact hole CNT while defining the pixel electrode portion in the unit pixel region. In detail, the pixel electrode layer 440 extends from the first connection electrode 441 and the first connection electrode 441 which are in contact with the drain electrode 424, and defines a rounded quadrangular shape. A second connection electrode 443 extending from the first sub electrode 442 having a relatively small width, a second sub electrode 444 extending from the second connection electrode 443 and defining a rounded square shape, A third connection electrode 445 having a relatively small width and extending from the second sub electrode 444, and a third sub electrode 446 extending from the third connection electrode 445 and defining a rounded square shape. do.

The pixel electrode layer 440 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like. In this case, the pixel electrode layer 440 may be patterned such that only the pixel electrode layer corresponding to the unit pixel region is left after the entire surface application, or may be partially coated to be formed only in the unit pixel region. In the drawing, the pixel electrode 440 is spaced apart from the gate line 410 and the source line 420 at an observer's point of view, but may overlap with the minimum width.

Subsequently, as illustrated in FIG. 6, each of the first to third sub-electrodes 442, 444, and 446 of the pixel electrode layers 440 formed in the unit pixel region has a plurality of linear patterns that are radially opened at the center of the plane. Fields 442a, 444a and 444a are formed. In the drawing, 16 linear patterns are formed on each of the first to third sub electrodes 442, 444, and 446. Removing some regions from each of the first to third sub-electrodes 442, 444, and 446 is for defining a plurality of domains. In the drawings, a plurality of linear patterns 442a, 444a, and 444a are formed by forming a pixel electrode layer entirely in a unit pixel region and then removing a portion of the region through a patterning process, but this is only separated for convenience of description. In the formation of the pixel electrode layer, it is preferable to simultaneously form a plurality of linear patterns 442a, 444a, and 444a.

FIG. 9A is a simulation diagram for schematically describing an operation of a liquid crystal panel according to a second exemplary embodiment of the present invention in a unit pixel area, and FIG. 9B is a waveform diagram illustrating a voltage felt by the liquid crystal layer corresponding to FIG. 9A. In particular, the color filter substrate has a flat common electrode layer, and the array substrate has a pixel electrode layer formed with holes and protrusions to define a multi-domain.                     

As shown in FIG. 9A, the color filter substrate 300 has a common electrode layer 320 flat over the first transparent substrate 305, and the array substrate 400 has a second transparent substrate to define a multi-domain. Holes 442a are formed on 405 and have pixel electrode layer 440 having protrusions 442b.

In operation, the first domain area DA1 is defined by the first connection electrode 441 and the first hole, and the second domain area DA2 is defined by the left side of the first hole and the first sub-electrode 442. The third domain area DA3 is defined by the right and second holes of the first sub-electrode 442. Voltages of the liquid crystal layers sensed in the first to third domain areas DA1, DA2, and DA3 are as shown in FIG. 9B.

Example-3

10 is a plan view of an array substrate according to a third exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along the line III-III 'of FIG. 10. In particular, it shows a reflective-transmissive array substrate having protrusions formed in the centers of sub-pixel regions connected to each other.

10 and 11, the liquid crystal display according to the third exemplary embodiment of the present invention may be formed by integrating an array substrate 500, a liquid crystal layer 200, and the array substrate 500. And a color filter substrate 300 accommodating 200.

The array substrate 500 is spaced apart from the gate wiring 510 extending in the horizontal direction on the transparent substrate 505, the gate electrode 512 extending from the gate wiring 510, and the gate wiring 510. The gate insulating layer 513 is formed of a material such as an open lower pattern 511, silicon nitride (SiNx), and the like to cover the gate wiring 510 and the gate electrode 512. .

The array substrate 500 includes a semiconductor layer 514 such as a-Si covering the gate electrode 512, a semiconductor impurity layer 515 such as n + a-Si formed on the semiconductor layer, and a lengthwise direction. An extended source wiring 520, a source electrode 522 extending from the source wiring 520, and a drain electrode 524 spaced apart from the source electrode 522 by a predetermined distance are included. The gate electrode 512, the semiconductor layer 514, the semiconductor impurity layer 515, the source electrode 522, and the drain electrode 524 define one thin film transistor TFT.

The gate wiring 510 or the source wiring 520 may be formed as a single layer or a double layer. When formed as the single layer, it may be formed of aluminum (Al) or aluminum (Al) -neodymium (Nd) alloy, and when formed as the double layer, such as chromium (Cr), molybdenum (Mo), or molybdenum alloy film A material having excellent physical / chemical properties of is formed as a lower layer, and a material having low specific resistance such as aluminum (Al) or aluminum alloy is formed as an upper layer.

The array substrate 500 includes a passivation layer 530 and an organic insulating layer 532 that are sequentially stacked to cover a portion of the drain electrode 526 while covering the thin film transistor TFT. The passivation layer 530 and the organic insulating layer 532 cover and protect the semiconductor layer 514 and the semiconductor impurity layer 515 between the source electrode 522 and the drain electrode 524. The thickness of the liquid crystal layer 200 may be adjusted by controlling the height of the organic insulating layer 532 by insulating the transistor TFT and the pixel electrode layer 540. Of course, the formation of the passivation layer 530 may be omitted.

The array substrate 500 is electrically connected to the drain electrode 524 of the thin film transistor TFT through the contact hole CNT, and has a pixel shape 540 having a pattern shape that opens in a different direction. It includes. The pixel electrode part 540 defines the capacitance of the storage capacitor Cst by an area overlapping the lower pattern 511.

In detail, the pixel electrode part 540 may include a first connection electrode 541 contacting the drain electrode 524 and a first sub electrode extending from the first connection electrode 541 and defining a rounded square shape. 542) a second sub-electrode 543 having a relatively small width extending from the first sub-electrode 542 and a second sub-electrode extending from the second sub-electrode 543 and defining a rounded square shape. 544, a third connection electrode 545 having a relatively small width and extending from the second sub electrode 544, and a third sub extending from the third connection electrode 545 and defining a rounded square shape Electrode 546.

Each of the first to third sub-electrodes 542, 544, and 546 is formed with a plurality of straight patterns 542a, 544a, and 544a that are radially opened at the center on a plane. In the drawing, 16 linear patterns are formed on each of the first to third sub-electrodes 542, 544, and 546.

The array substrate 500 includes an interlayer insulating layer 534 covering the organic insulating layer 532 and the pixel electrode layer 540, and a region 542 corresponding to the source wiring 520 formed in the pixel electrode layer 540. The reflective layer 550 is formed on a portion of the pixel electrode layer 540 to cover the gap.

In the drawing, although the projections are formed on the surface of the flat organic insulating layer of the sub-electrode, the first and second regions are defined after the organic insulating layer of the sub-electrode is defined as a plurality of first and second region portions formed at a relatively high level. Alternatively, protrusions may be formed on the organic insulating layers of the second region portions. The first region portions define a convex shape having a relatively higher height than the second region portions.

Meanwhile, the color filter substrate 300 includes a color pixel layer 310 formed on the transparent substrate 305 corresponding to a unit pixel area, and a common electrode layer 320 formed on the color pixel layer 310. The liquid crystal layer 200 is accommodated through the coalescence with the array substrate 500. The liquid crystals in the liquid crystal layer 200 are arranged in a vertical alignment (VA) mode.

When the LCD is viewed on a plane, 16 different domains are formed in each of the first to third sub-electrodes 542, 544, and 546 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

In addition, the PVA mode liquid crystal display may be transferred to the reflection-transmissive mode by forming a separate reflection part corresponding to the boundary region between the different domains and the vicinity thereof. Accordingly, an area in which the liquid crystal molecules are arranged in an undesired direction in the corresponding area and thus cannot be used as a normal display area may be used as a reflection area.

12A to 12F are diagrams for describing a method of manufacturing the array substrate of FIG. 10.

Referring to FIG. 12A, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or the like on a transparent substrate 505 made of an insulating material such as glass or ceramic. A metal such as tungsten (W) is deposited. Subsequently, a plurality of gate lines 510 extending in a horizontal direction and arranged in a vertical direction by patterning the deposited metal and a lower portion having a pattern parallel to the gate lines and opening in a rounded rectangle in a unit pixel area A storage pattern 511 and a gate electrode 512 extending from the gate line 510 are formed to define the thin film transistor.

Subsequently, silicon nitride or the like is stacked on the entire surface of the substrate including the gate electrode 512 by plasma chemical vapor deposition to form a gate insulating layer 513. The gate insulating layer 513 may be formed on the entire surface of the transparent substrate 505, or may be patterned to cover the gate line 510 and the gate electrode 512.

As shown in FIG. 12B, forming an amorphous-silicon (a-Si) film and an insitu doped n + amorphous silicon (a-Si) film on the gate insulating layer 513 and defining a thin film transistor For example, a portion of the region is patterned to form an active layer 515 in the region where the gate electrode 512 is located.                     

Subsequently, metals such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or tungsten (W) are deposited. Subsequently, the deposited metal is patterned to form a plurality of source lines 520, a source electrode 522, and a drain electrode 524. The source electrode 522 extends from the source line 520, and the drain electrode 524 is patterned to be spaced apart from the source electrode 522 by a predetermined interval.

As shown in FIG. 12C, a passivation layer 530 and an organic insulating layer 532 are formed by laminating a resist on a substrate on which the resultant of FIG. 12B is formed by a spin coating method. Subsequently, a portion of the drain electrode 524 is removed by removing a portion of the passivation layer 530 and the organic insulating layer 532 from the unit pixel area defined by the gate line 510 and the source line 520. The contact hole CNT to be exposed and the first to third protrusions 532b, 534b and 536b having a relatively high height are formed.

As shown in FIG. 12D, the pixel electrode layer 540 is formed to be connected to the drain electrode 524 through the contact hole CNT while defining the pixel electrode portion in the unit pixel region. In detail, the pixel electrode layer 540 includes a first connection electrode 541 contacting the drain electrode 524 and a first sub electrode 542 extending from the first connection electrode 541 and defining a rounded square shape. ), A second connection electrode 543 extending from the first sub electrode 542 having a relatively small width, and a second sub electrode extending from the second connection electrode 543 and defining a rounded quadrangular shape ( 544, a third connection electrode 545 having a relatively small width and extending from the second sub electrode 544, and a third sub electrode extending from the third connection electrode 545 and defining a rounded square shape. 546.

The pixel electrode layer 540 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like. In this case, the pixel electrode layer 540 may be patterned such that only the pixel electrode layer corresponding to the unit pixel region is left after the entire surface application, or may be partially coated to be formed only in the unit pixel region. In the drawing, the pixel electrode 540 is spaced apart from the gate line 510 and the source line 520 by a certain distance from the observer's point of view, but may overlap with the minimum width.

Subsequently, as illustrated in FIG. 12E, each of the first to third sub-electrodes 542, 544, and 546 of the pixel electrode layer 540 formed in the unit pixel region has a plurality of straight patterns that are radially opened at the center of the plane. Fields 542a, 544a, and 544a are formed.

In the drawing, 16 linear patterns are formed in each of the first to third sub-electrodes 542, 544, and 546. Removing some regions from each of the first to third sub-electrodes 542, 544, and 546 is to define a plurality of domains. In the drawing, after forming the pixel electrode layer as a whole in the unit pixel region (shown in FIG. 12D), some regions are removed through a patterning process to form a plurality of straight line patterns 542a, 544a, and 544a (shown in FIG. 12E). ), It is separated for convenience of description, and it is preferable to simultaneously form the plurality of straight line patterns 542a, 544a, and 546a when the pixel electrode layer is formed.

Subsequently, as shown in FIG. 12F, after forming an interlayer insulating layer (not shown) on the resultant of FIG. 12E, the reflective layer 550 covering the first connection electrode 541 and the first sub-electrode 542. To form.

Example-4

13 is a plan view of an array substrate according to a fourth embodiment of the present invention. In particular, an array substrate is formed in which a whirlpool opening pattern that is rotated in a clockwise direction is formed in a rounded rectangular sub-pixel region connected to each other.

Referring to FIG. 13, the array substrate 600 according to the fourth embodiment of the present invention may include a gate wiring 610 extending in a horizontal direction on the transparent substrate 605, and a gate electrode extending from the gate wiring 610. 612 and a lower pattern 611 spaced apart from the gate wiring 610 and corresponding to the center area of the unit pixel area.

The array substrate 600 includes a channel layer 615 covering the gate electrode 612, a source wiring 620 extending in a vertical direction, a source electrode 622 extending from the source wiring 620, and The drain electrode 624 is spaced apart from the source electrode 622 by a predetermined distance. The gate electrode 612, the semiconductor layer 614, the semiconductor impurity layer 615, the source electrode 622, and the drain electrode 624 define one thin film transistor TFT.

The array substrate 600 is electrically connected to the drain electrode 624 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 640 having a pattern shape opened to face different directions. It includes. The pixel electrode part 640 defines the capacitance of the storage capacitor Cst by an area overlapping the lower pattern 611.

In detail, the pixel electrode part 640 may include a first connection electrode 641 contacting the drain electrode 624 and a first sub electrode extending from the first connection electrode 641 and defining a rounded quadrangular shape ( 642), a second connection electrode 643 having a relatively small width extending from the first sub-electrode 642, and a second sub-electrode extending from the second connection electrode 643 and defining a rounded square shape. 644, a third connection electrode 645 having a relatively small width, extending from the second sub electrode 644, and a third sub extending from the third connection electrode 645 and defining a rounded square shape. Electrode 646.

Each of the first to third sub-electrodes 642, 644, and 646 is formed with a plurality of curved patterns 642a, 644a, and 644a that are radially opened at a center on a plane. In the drawing, 16 curved patterns are formed in each of the first to third sub-electrodes 642, 644, and 646.

When the LCD is viewed on a plane, 16 different domains are formed in each of the first to third sub-electrodes 642, 644, and 646 formed in the unit pixel area. Therefore, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

Example-5

14 is a plan view of an array substrate according to a fifth embodiment of the present invention. In particular, an array substrate is formed in which a circular pool-shaped opening pattern rotating in a clockwise direction is formed in circular sub-pixel regions connected to each other.

Referring to FIG. 14, the array substrate 700 according to the fifth embodiment of the present invention may include a gate wiring 710 extending in a horizontal direction on the transparent substrate 705, and a gate electrode extending from the gate wiring 710. 712 and a lower pattern 711 that is spaced apart from the gate line 710 and is open to correspond to the center area of the unit pixel area.

The array substrate 700 may include a channel layer 715 covering the gate electrode 712, a source wiring 720 extending in a longitudinal direction, a source electrode 722 extending from the source wiring 720, and The drain electrode 724 is spaced apart from the source electrode 722 by a predetermined distance. The gate electrode 712, the semiconductor layer 714, the semiconductor impurity layer 715, the source electrode 722, and the drain electrode 724 define one thin film transistor TFT.

The array substrate 700 is electrically connected to the drain electrode 724 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 740 having a pattern shape opened to face different directions. It includes. The pixel electrode part 740 defines a capacitance of the storage capacitor Cst by an area overlapping the lower pattern 711.

In detail, the pixel electrode part 740 extends from the first connection electrode 741 contacting the drain electrode 724 and the first connection electrode 741 to define a circular shape. A second connection electrode 743 extending from the first sub electrode 742 having a relatively small width, a second sub electrode 744 extending from the second connection electrode 743 and defining a circular shape; A third connection electrode 745 having a relatively small width and extending from the second sub electrode 744, and a third sub electrode 746 extending from the third connection electrode 745 and defining a circular shape. do.

Each of the first to third sub-electrodes 742, 744, and 746 is formed with a plurality of curved patterns 742a, 744a, and 744a that are radially opened at a center on a plane. In the drawing, 16 curved patterns are formed in each of the first to third sub-electrodes 742, 744, and 746.

When the LCD is viewed on a plane, 16 different domains are formed in each of the first to third sub electrodes 742, 744, and 746 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

<Example-6>

15 is a plan view of an array substrate according to a sixth embodiment of the present invention. In particular, an array substrate is formed in which linear and curved opening patterns are formed in rounded rectangular sub-pixel regions connected to each other.

Referring to FIG. 15, the array substrate 800 according to the sixth embodiment of the present invention may include a gate wiring 810 extending in a horizontal direction on the transparent substrate 805, and a gate electrode extending from the gate wiring 810. 812 and a lower pattern 811 spaced apart from the gate wiring 810 to correspond to the center area of the unit pixel area.

The array substrate 800 includes a channel layer 815 covering the gate electrode 812, a source wiring 820 extending in a vertical direction, a source electrode 822 extending from the source wiring 820, and The drain electrode 824 is spaced apart from the source electrode 822 by a predetermined distance. The gate electrode 812, the semiconductor layer 814, the semiconductor impurity layer 815, the source electrode 822, and the drain electrode 824 define one thin film transistor TFT.

The array substrate 800 is electrically connected to the drain electrode 824 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 840 having a pattern shape opened to face different directions. It includes. The pixel electrode part 840 defines a capacitance of the storage capacitor Cst by an area overlapping the lower pattern 811.

In detail, the pixel electrode part 840 includes a first connection electrode 841 contacting the drain electrode 824 and a first sub electrode extending from the first connection electrode 841 and defining a rounded square shape. 842, a second connection electrode 843 having a relatively small width and extending from the first sub electrode 842, and a second sub electrode extending from the second connection electrode 843 and defining a rounded square shape. 844, a third connection electrode 845 having a relatively small width and extending from the second sub-electrode 844, and a third sub extending from the third connection electrode 845 and defining a rounded square shape. Electrode 846.

Each of the first to third sub electrodes 842, 844, and 846 includes a plurality of straight patterns 842a, 844a, and 844a that are radially opened at a center on a plane, and a plurality of openings that surround the straight patterns. Curve patterns 842b, 844b, and 846b are formed. In the drawing, eight straight patterns are formed on each of the first to third sub electrodes 842, 844, and 846, and eight curved patterns are formed.

When the LCD is viewed on a plane, a total of 16 different domains are formed in each of the first to third sub-electrodes 842, 844, and 846 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

<Example-7>

16 is a plan view of an array substrate according to a seventh embodiment of the present invention. In particular, an array substrate in which linear and curved opening patterns are formed in circular sub-pixel regions connected to each other is shown.                     

Referring to FIG. 16, the array substrate 900 according to the seventh embodiment of the present invention may include a gate wiring 910 extending in a horizontal direction on the transparent substrate 905, and a gate electrode extending from the gate wiring 910. 912 and a lower pattern 911 that is spaced apart from the gate wiring 910 and is open to correspond to the center area of the unit pixel area.

The array substrate 900 includes a channel layer 915 covering the gate electrode 912, a source wiring 920 extending in a vertical direction, a source electrode 922 extending from the source wiring 920, and The drain electrode 924 is spaced apart from the source electrode 922 by a predetermined distance. The gate electrode 912, the semiconductor layer 914, the semiconductor impurity layer 915, the source electrode 922, and the drain electrode 924 define one thin film transistor TFT.

The array substrate 900 is electrically connected to the drain electrode 924 of the thin film transistor TFT through a contact hole CNT, and has a pixel shape 940 having a pattern shape opened to face different directions. It includes. The pixel electrode part 940 defines a capacitance of the storage capacitor Cst by an area overlapping the lower pattern 911.

In detail, the pixel electrode part 940 extends from the first connection electrode 941 and the first connection electrode 941 which are in contact with the drain electrode 924, and defines a circular shape. A second connection electrode 943 extending from the first sub electrode 942 having a relatively small width, a second sub electrode 944 extending from the second connection electrode 943 and defining a circular shape; The third connection electrode 945 having a relatively small width and extending from the second sub electrode 944, and the third sub electrode 946 extending from the third connection electrode 945 and defining a circular shape. do.

Each of the first to third sub electrodes 942, 944, and 946 includes a plurality of linear patterns 942a, 944a, and 944a that are radially opened at a center on a plane, and a plurality of openings that surround the linear patterns. Curve patterns 942b, 944b, and 946b are formed. In the drawing, eight straight patterns are formed on each of the first to third sub electrodes 942, 944, and 946, and eight curved patterns are formed.

When the LCD is viewed on a plane, a total of 16 different domains are formed in each of the first to third sub electrodes 942, 944, and 946 formed in the unit pixel area. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate of the liquid crystal display device to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

As described above, according to the present invention, the common electrode layer of the color filter substrate is not patterned, but only the pixel electrode layer of the array substrate is patterned, in particular, patterning to define a radial shape or a swirl shape with respect to the center of the pixel electrode layer. By processing, multi-domains can be realized.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (19)

A substrate having a pixel region; A switching element formed in the pixel region; And And a pixel electrode part electrically connected to the switching element, having a pattern shape opened to face different directions in the pixel area. The method of claim 1, wherein the pixel electrode unit, A plurality of sub electrodes; And And a connection electrode having a width relatively smaller than that of the sub electrode and connecting adjacent sub electrodes to each other. The array substrate of claim 1, wherein the pattern shape is a plurality of straight lines opened radially with respect to a center. The array substrate of claim 1, wherein the pattern shape is a plurality of whirlpool shapes that are radially opened with respect to a center. The method of claim 1, wherein the pixel electrode unit, A plurality of sub electrodes; A connection electrode having a smaller width than the sub electrode and connecting adjacent sub electrodes to each other; And An array substrate comprising a reflector formed on at least one sub-electrode to reflect light. The display apparatus of claim 5, wherein the sub-electrode corresponding to the reflecting portion includes a plurality of first region portions and second region portions formed at a relatively high level, and the first region portions are relatively higher than the second region portions. An array substrate characterized by defining a convex shape having a height. The array substrate of claim 5, wherein the reflector is formed on a sub electrode connected to an electrode of the switching element. The array substrate of claim 5, wherein the sub electrode is any one of a quadrangular shape, a rounded rectangular shape, and a circular shape. The array of claim 1, wherein the pixel electrode unit includes a plurality of sub-electrodes connected to each other, and the widths of the opening patterns facing each other based on the center of the plane among the opening patterns formed in the sub-electrodes are substantially the same. Board. The array substrate of claim 1, wherein the pixel electrode portion further includes protrusions. (a) forming a gate wiring, a source wiring, and a switching element connected to the gate wiring and the source wiring in a unit pixel area; And (b) forming a pixel electrode layer connected to the switching element having a pattern shape opened in different directions to define domains of a plurality of liquid crystals in the unit pixel region. The method of claim 11, wherein step (b) comprises: (b-1) forming an organic insulating film on the resultant of step (a); (b-2) forming a plurality of first region portions and second region portions formed on the upper portion of the organic insulating layer at a relatively high height, wherein the first region portions are convex with a height that is relatively higher than that of the second region portions; A method of manufacturing an array substrate, the method comprising forming a pixel electrode layer defining a. The method of claim 12, (b-3) A method of manufacturing an array substrate, further comprising the step of forming a reflector on the resultant of step (b-2). The method of claim 11, wherein the pixel electrode layer includes a plurality of sub electrodes and a connection electrode connecting the sub electrodes to each other with a width smaller than that of the sub electrodes. An upper substrate having a common electrode layer; Liquid crystal layer; And A lower substrate having the pixel electrode portion accommodating the liquid crystal layer through coalescence with the upper substrate and having a pattern shape opened to face different directions to define a plurality of domains through connection with the common electrode layer; Including display device. The display device of claim 15, wherein the lower substrate includes a gate wiring, a source wiring, and a switching element formed in a pixel region defined by the gate wiring and the source wiring, wherein the pixel electrode portion is electrically connected to a drain electrode of the switch element. Display device characterized in that connected to. The display device of claim 15, wherein the upper substrate further comprises a common electrode layer covering the color pixel layer. The display device of claim 17, wherein the common electrode layer has a flat shape. 16. The display device of claim 15, wherein the pixel electrode portion has a plurality of sub-electrodes, a connecting electrode for connecting the sub-electrodes to each other with a smaller width than the sub-electrode, and formed on one or more sub-electrodes to reflect light. Display device including a reflector.

Images