KR101232618B1 - Array substrate, and liquid crystal display panel and liquid crystal display device having the same - Google Patents

Abstract

Disclosed are an array substrate, a liquid crystal display panel having the same, and a liquid crystal display device for improving an image quality defect caused by an RMS cause of a pixel. The switching element is formed in a unit pixel area defined by gate lines adjacent to each other and data lines adjacent to each other. The main pixel portion is formed in the center region of the unit pixel region. The coupling capacitor is connected to the switching element. The sub pixel portion is connected to the coupling capacitor and is formed in the remaining area of the unit pixel area. Accordingly, the area of the additional gate-source capacitor generated by overlapping the gate wiring and the pixel electrode in the PVA structure is transferred from the main pixel to the sub pixel, thereby reducing the kickback voltage of the main pixel, which is caused by the RMS cause of the pixel. The poor image quality can be improved.

Liquid Crystal, Vertical Alignment, VA, PVA, Kickback Voltage, Main Pixel, Sub Pixel

Description

ARRAY SUBSTRATE, AND LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME

1 is a plan view illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of the liquid crystal display panel shown in FIG. 1.

3 is a plan view of the array substrate illustrated in FIG. 2.

4 to 8 are plan views illustrating a method of manufacturing the array substrate illustrated in FIG. 3.

9 is a plan view illustrating the transfer of a gate-source capacitor according to the present invention.

10 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 11 is a plan view of the array substrate illustrated in FIG. 10.

12 is a plan view illustrating a liquid crystal display panel according to a third exemplary embodiment of the present invention.

FIG. 13 is a plan view of the array substrate illustrated in FIG. 12.

14 is a plan view illustrating a liquid crystal display panel according to a fourth exemplary embodiment of the present invention.

FIG. 15 is a plan view of the array substrate shown in FIG. 14.

16 is a plan view illustrating a liquid crystal display panel according to a fifth exemplary embodiment of the present invention.

17 is a plan view of the array substrate shown in FIG. 16.

18 is a plan view illustrating a liquid crystal display panel according to a sixth embodiment of the present invention.

19 is a plan view of the array substrate shown in FIG. 18.

20 is a plan view illustrating a liquid crystal display panel according to a seventh exemplary embodiment of the present invention.

FIG. 21 is a plan view of the array substrate illustrated in FIG. 20.

22 is a plan view illustrating a liquid crystal display panel according to an eighth embodiment of the present invention.

FIG. 23 is a plan view of the array substrate illustrated in FIG. 22.

<Description of the symbols for the main parts of the drawings>

100: array substrate 180: liquid crystal layer

190: color filter substrate 110: gate wiring

STL1, STL2: Lower Storage Pattern CPL, 126: Coupling Pattern

120: source wiring 124, 128: upper storage pattern

125, 127: extension pattern 142, 146: sub electrode

144: main electrode GL: gate line

DL: Data line MP: Main pixel part

Ccp1, Ccp2: coupling capacitors SP1, SP2: sub-pixel portion

The present invention relates to an array substrate, a liquid crystal display panel and a liquid crystal display device having the same, and more particularly, to an array substrate for improving the image quality defect caused by the RMS cause of the pixel, a liquid crystal display panel and a liquid crystal display device having the same It is about.

In general, a liquid crystal display (LCD) includes an array substrate (or TFT substrate) on which a thin film transistor (TFT) for switching each pixel is formed, an opposing substrate (or a color filter substrate) on which a common electrode is formed, and a seal between the two substrates. It consists of a liquid crystal layer. The liquid crystal display displays an image by applying a voltage to the liquid crystal layer to control light transmittance.

Since the liquid crystal display implements an image by transmitting light only in a direction that is not shielded by the liquid crystal, a view angle is relatively narrower than that of other display devices. Accordingly, in order to realize a wide viewing angle, a liquid crystal display device having a vertically aligned mode has been developed.

The liquid crystal display of the VA mode is composed of two substrates vertically aligned on opposite surfaces and a liquid crystal layer having negative type dielectric constant anisotropy sealed between the two substrates. The liquid crystal molecules of the liquid crystal layer have a property of homeotropic alignment.

In operation, when no voltage is applied between the two substrates, they are aligned vertically with respect to the substrate surface to display black, and when a predetermined voltage is applied, they are aligned in a substantially horizontal direction to the substrate surface and are white. white is displayed, and when a voltage smaller than the voltage for the white display is applied, it is oriented so as to be inclined obliquely with respect to the surface of the substrate to display gray.

On the other hand, in a liquid crystal display device, especially a small and medium sized liquid crystal display device, narrow viewing angle or gray level inversion is a problem to be solved. To solve this problem, relatively small and medium-sized liquid crystal displays use a patterned vertically alignment (PVA) structure. The liquid crystal display adopting the PVA mode has a common electrode layer patterned on a color filter substrate and a pixel electrode layer patterned on an array substrate to define a multi-domain.

Accordingly, a relatively high kickback voltage is applied to the main pixel, thereby causing a poor image quality such as flicker.

Therefore, the technical problem of the present invention is focused on this point, an object of the present invention is to reduce the kickback voltage of the main pixel array substrate having an optimized PVA pixel structure to improve the poor image quality caused by the RMS cause of the pixel To provide.

Another object of the present invention is to provide a liquid crystal display panel having the above-described array substrate.

Still another object of the present invention is to provide a liquid crystal display device having the above-described array substrate.

In order to realize the above object of the present invention, an array substrate according to an embodiment includes a switching element, a main pixel portion, a coupling capacitor, and a sub pixel portion. The switching element is formed in a unit pixel area defined by gate lines adjacent to each other and data lines adjacent to each other. For example, one pixel may be defined by the first and second gate lines and the first and second data lines. The main pixel portion is formed in the central region of the unit pixel region. The coupling capacitor is connected to the switching element. The sub-pixel portion is connected to the coupling capacitor and is formed in the remaining area of the unit pixel area.

A plurality of opening patterns are formed in the main pixel portion.

A plurality of opening patterns are formed in the sub pixel portion.

The main pixel unit may be formed in an area parallel to the gate line and divided into two unit pixel areas.

The main pixel unit is connected to the switching element. Preferably, the main pixel portion includes a second coupling pattern formed at a lower portion thereof, and a main electrode formed at an upper portion thereof to contact the second coupling pattern. The sub-pixel portion may be separated from the first lower storage pattern formed at a lower portion, the first sub electrode contacting the first lower storage pattern, the second lower storage pattern formed at a lower portion, and the first sub electrode. It is preferable to include a second sub-electrode in contact with the lower storage pattern.

In this case, the main electrode is characterized in that the two Y-shaped opening pattern which is mirror-symmetrical about the horizontal axis of the unit pixel region is formed.

The first sub-electrode may have two opening patterns formed in parallel with the Y-shaped branch.

The second sub-electrode is formed with two opening patterns which are parallel to the Y-shaped branching part and are mirror-symmetrical with respect to the central axis in the horizontal direction and the opening pattern formed in the first sub-electrode.

In order to realize the above object of the present invention, an array substrate according to another embodiment includes a main switching element, a main pixel portion, a sub gate line, a sub switching element, and a sub pixel portion. The main gate line is formed in a unit pixel area. The main switching element is connected to the main gate line. The main pixel portion is connected to the main switching element and is formed in a central region of the unit pixel region. The sub gate line is formed in the unit pixel area. The sub switching element is connected to the sub gate line. The sub-pixel portion is formed in the remaining area of the unit pixel area.

Here, the array substrate according to another embodiment further includes a first lower storage pattern formed to be perpendicular to the gate line, and a first coupling pattern dividing the unit pixel region in the horizontal direction by two, the first coupling pattern Is connected to the first lower storage pattern in the right region of the unit pixel.

In order to achieve the above object of the present invention, a liquid crystal display panel according to an embodiment includes an upper substrate, a liquid crystal layer, and a lower substrate. The upper substrate has a common electrode layer. The lower substrate receives the liquid crystal layer through coalescence with the upper substrate, the main pixel portion formed in the central region of the unit pixel region, a coupling capacitor connected to the switching element, and the coupling capacitor, And a sub pixel portion formed in the remaining area of the unit pixel area.

In accordance with another aspect of the present invention, a liquid crystal display device includes a gate line, a data line, a switching element, a main pixel portion, a first coupling capacitor, a first sub pixel portion, and a second coupling. And a capacitor and a second sub pixel portion. The gate line carries a gate signal. The data line carries a data signal. The switching element is connected to the gate line and the data line. The main pixel portion is connected to the switching element. One end of the first coupling capacitor is connected to the switching element. The first sub pixel portion is connected to the switching element via the first coupling capacitor. One end of the second coupling capacitor is connected to the switching element. The second sub-pixel portion is connected to the switching element via the second coupling capacitor.

The main pixel unit includes a main liquid crystal capacitor having one end connected to the switching element, the other end connected to the common voltage, and one end connected to the switching element and the other end connected to the storage voltage.

A first liquid crystal capacitor having one end connected to the first coupling capacitor, the other end connected to the common voltage, and one end connected to the first coupling capacitor and the other end connected to the storage voltage; It characterized in that it comprises a storage capacitor.

The second sub pixel portion is connected to the second coupling capacitor, one end of which is connected to the second coupling capacitor, the other end of which is connected to the second coupling capacitor, and the other end of which is connected to the storage voltage. It characterized in that it comprises a second storage capacitor.

According to such an array substrate, a liquid crystal display panel and a liquid crystal display device having the same, a main pixel is transferred by transferring an area of an additional gate-source capacitor generated by overlapping gate wiring and pixel electrodes in a PVA structure from a main pixel to a sub pixel. By reducing the kickback voltage of, the poor image quality caused by the RMS cause of the pixel such as flicker can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the width and thickness of wirings are enlarged in order to clearly express various layers (or films) and regions. As described in the overall description, it is described from an observer's point of view that, when a part such as a layer, a film, an area, or a plate is located above another part, this includes not only the part directly above the other part but also another part in the middle. . On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Example-1

1 is a plan view illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of the liquid crystal display panel illustrated in FIG. 1. In particular, a liquid crystal display panel having a transmissive array substrate is shown.

1 and 2, the liquid crystal display panel according to the first exemplary embodiment of the present invention may be formed by combining the array substrate 100, the liquid crystal layer 180, and the array substrate 100. ) Includes a color filter substrate 190.

The array substrate 100 is spaced apart from the gate wiring 110 on the substrate 105 in a horizontal direction, the gate electrode 112 extending from the gate wiring 110, and the gate wiring 110. First and second lower storage patterns STL1 and STL2 formed to be parallel to the gate lines 110 in a pixel area, and a first coupling pattern CPL that divides in the horizontal direction of a unit pixel area. do.

The array substrate 100 is made of a material such as silicon nitride (SiNx), and includes a gate insulating layer 113 covering the gate wiring 110 and the gate electrode 112, and an active layer covering the gate electrode 112. 114. The active layer 114 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 100 includes a source wiring 120 extending in a vertical direction, a source electrode 122 extending from the source wiring 120, and a drain electrode 123 spaced apart from the source electrode 122 by a predetermined distance. ). The gate electrode 112, the semiconductor layer 114, the semiconductor impurity layer 115, the source electrode 122, and the drain electrode 123 define a thin film transistor TFT.

The array substrate 100 may include a first upper storage pattern 124 extending from the drain electrode 123, a first extension pattern 125 extending from the drain electrode 123 while being formed on the left side of a unit pixel area, The second coupling pattern 126 connected to the first extension pattern 125, the second extension pattern 127 and the second extension formed on the left side of the unit pixel area and connected to the first extension pattern 125. And a second upper storage pattern 128 connected to the pattern 127.

The gate wiring 110 or the source wiring 120 may be formed as a single layer or a double layer. When formed as the single layer, it may be formed of aluminum (Al) or aluminum (Al) -neodymium (Nd) alloy, and when formed as the double layer, such as chromium (Cr), molybdenum (Mo), or molybdenum alloy film A material having excellent physical / chemical properties of is formed as a lower layer, and a material having low specific resistance such as aluminum (Al) or aluminum alloy is formed as an upper layer.

The array substrate 100 includes a passivation layer 130 and an organic insulating layer 132 sequentially stacked to expose a portion of the drain electrode 126 while covering the thin film transistor TFT. The passivation layer 130 and the organic insulating layer 132 cover and protect the channel layer 114 between the source electrode 122 and the drain electrode 123, and the thin film transistor TFT and the pixel electrode part. It serves to insulate 140. The channel layer 114 includes a semiconductor layer 114 and a semiconductor impurity layer 115 formed on the semiconductor layer 114.

The thickness (cell gap of the liquid crystal layer) of the liquid crystal layer 200 may be adjusted by adjusting the height of the organic insulating layer 132. Of course, the passivation layer 130 may be omitted.

The array substrate 100 includes a pixel electrode part 140 having a pattern shape which is electrically connected to the drain electrode 123 of the thin film transistor TFT through a contact hole CNT.

In detail, the pixel electrode unit 140 may include a main electrode 144 contacting the second coupling pattern 126, a first sub-electrode 142 contacting the first lower storage pattern STL1, and the first electrode. The second sub electrode 146 is separated from the sub electrode 142 and is in contact with the second lower storage pattern.

The main electrode 144 is formed with two Y-shaped opening patterns in which the unit pixel area is mirror symmetrically about the central axis in the horizontal direction. The mirror symmetric Y-shaped branch has an angle of 90 degrees. Two opening patterns are formed on the first sub-electrode 142 in parallel with the Y-shaped branches. The second sub-electrode 146 is formed with two opening patterns that are parallel to the Y-shaped branch and mirror-symmetric with respect to the central axis in the horizontal direction and the opening pattern formed in the first sub-electrode 142. . The plurality of opening patterns are formed in the main electrode 144 and the first and second sub-electrodes 142 and 146 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates in the future.

The main electrode 144 and the first and second sub electrodes 142 and 146 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

Meanwhile, the color filter substrate 190 is formed on the array substrate 100 while being formed on the color layer 194 formed on the transparent substrate 192 and the color layer 194 corresponding to the unit pixel region. The liquid crystal layer 180 is accommodated through the coalescence with the array substrate 100, including the common electrode part 196 covering a portion of the opening of the pixel electrode 140 and having an opening. The liquid crystal molecules in the liquid crystal layer 180 are arranged in a vertical alignment (VA) mode.

In a plan view, a plurality of different domains are formed by the main electrode 144 and the first and second sub electrodes 142 and 146, respectively. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

3 is an equivalent circuit diagram illustrating a unit pixel of the liquid crystal display illustrated in FIG. 1.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a gate line GL, a data line DL, a switching element TFT, a main pixel unit MP, and a first coupling capacitor Ccp1. The first sub pixel part SP1, the second coupling capacitor Ccp2, and the second sub pixel part SP2 are included.

The gate line GL transfers a gate signal for activating the switching element TFT to the switching element TFT, and the data line DL transfers a data signal to the switching element TFT.

One end of the main pixel unit MP is connected to the switching element TFT, the other end of which is connected to the main liquid crystal capacitor Clcm and one end of which is connected to the switching element TFT, and the other end thereof is connected to the switching element TFT. The main storage capacitor Cstm is connected to the storage voltage Vst.

One end of the first coupling capacitor Ccp1 is connected to the switching element TFT, and the other end thereof is connected to the first sub pixel part SP1.

One end of the first sub pixel part SP1 is connected to the first coupling capacitor Ccp1, and the other end is connected to the first liquid crystal capacitor Clcs1 and one end of the first coupling capacitor Ccp1. The first storage capacitor Csts1 connected to the Ccp1 and the other end connected to the storage voltage Vst.

One end of the second coupling capacitor Ccp2 is connected to the switching element TFT, and the other end thereof is connected to the second sub pixel part SP2.

One end of the second sub pixel part SP2 is connected to the second coupling capacitor Ccp2, and the other end of the second sub pixel part SP2 is connected to the common voltage Vcom and one end thereof is the second coupling. A second storage capacitor Csts2 is connected to the capacitor Ccp2 and the other end thereof is connected to the storage voltage Vst.

4 to 8 are plan views illustrating a method of manufacturing the array substrate illustrated in FIG. 1. In particular, an array substrate having contact holes formed in each of the drain wiring adjacent to the TFT and the drain wiring contacting the TFT is shown. In particular, FIG. 4 illustrates the formation of the gate wiring, FIG. 5 illustrates the formation of the active opening pattern, FIG. 6 illustrates the formation of the source-drain wiring, and FIG. 7 illustrates the organic insulating film in which the contact hole is formed. 8 illustrates a pixel electrode such as ITO.

Referring to FIG. 4, tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or the like on a transparent substrate 105 made of an insulating material such as glass or ceramic. A metal of a material such as tungsten (W) is deposited.

Subsequently, the plurality of gate lines 110 extended in the horizontal direction and arranged in the vertical direction by patterning the deposited metal, the gate electrode 112 extending from the gate line 110 to define the thin film transistor, and the unit First and second lower storage patterns STL1 and STL2 are formed to be parallel to the gate lines 110 in the pixel area, and a first coupling pattern CPL is formed to be divided in the horizontal direction of the unit pixel area. do.

Subsequently, silicon nitride or the like is deposited on the entire surface of the substrate including the gate line 110, the gate electrode 112, the first and second lower storage patterns STL1 and STL2, and the first coupling pattern CPL. The gate insulating layer 113 is formed by laminating by vapor deposition. The gate insulating layer 113 may be formed on the entire surface of the substrate 105, and may include the gate line 110, the gate electrode 112, the first and second lower storage patterns STL1 and STL2, and the first and second lower storage patterns STL1 and STL2. It may be patterned to cover the coupling pattern CPL.

As shown in FIG. 5, an amorphous-silicon (a-Si) film and an n + amorphous silicon (a-Si) film are formed on the gate insulating layer 113, and a portion of the region is patterned to define a thin film transistor. The active layer 114 is formed in the region where the gate electrode 112 is located.

Subsequently, metals such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or tungsten (W) are deposited.

As illustrated in FIG. 6, the deposited metal is patterned to form a plurality of data lines 120, source electrodes 122 extending from the data lines 120, and drains spaced apart from the source electrodes 122 at regular intervals. The electrode 123 is connected to the first upper storage pattern 124 extending from the drain electrode 123, the first extension pattern 125 extending from the drain electrode 123, and the first extension pattern 125. A second coupling pattern 126, a second extension pattern 127 connected to the first extension pattern 125, and a second upper storage pattern 128 connected to the second extension pattern 127 are formed.

A first contact hole CNTST1 is formed in the first upper storage pattern 124. The second coupling pattern 126 covers the first coupling pattern CPL while being divided in two in the horizontal direction of the unit pixel area. A second contact hole CNTST2 is formed in the second upper storage pattern 128.

As shown in FIG. 7, the passivation layer 130 and the organic insulating layer 132 are formed by stacking resist on the substrate on which the resultant substrate of FIG. 6 is formed by spin coating.

Subsequently, a portion of the passivation layer 130 and the organic insulating layer 132 is removed in the unit pixel area defined by the gate lines 110 and the data lines 120 adjacent to each other. The third contact hole CNTST3 is formed in the region corresponding to the contact hole CNTST1. In addition, a fourth contact hole CNTST4 is formed in an area corresponding to the second contact hole CNTST2, and a fifth contact hole CNTCP is formed in an area corresponding to the second coupling pattern 126. .

As illustrated in FIG. 8, the first contact hole CNTST4 is connected to the first lower storage pattern STL1 through the third contact hole CNTST3 and the first contact hole CNTST1 in a unit pixel area. And a pixel electrode part 140 connected to the second lower storage pattern STL2 through the second contact hole CNTST2 and connected to the second coupling pattern 126 through the fifth contact hole CNTCP. do.

In detail, the pixel electrode unit 140 may include a main electrode 144 contacting the second coupling pattern 126, a first sub-electrode 142 contacting the first lower storage pattern STL1, and the first electrode. The second sub electrode 146 is separated from the sub electrode 142 and is in contact with the second lower storage pattern.

The main electrode 144 is formed with two Y-shaped opening patterns in which the unit pixel area is mirror symmetrically about the central axis in the horizontal direction. The mirror symmetric Y-shaped branch has an angle of 90 degrees. Two opening patterns are formed on the first sub-electrode 142 in parallel with the Y-shaped branches. The second sub-electrode 146 is formed with two opening patterns that are parallel to the Y-shaped branch and mirror-symmetric with respect to the central axis in the horizontal direction and the opening pattern formed in the first sub-electrode. The plurality of opening patterns are formed in the main electrode 144 and the first and second sub-electrodes 142 and 146 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates in the future.

The main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like. The main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 may be front-coated and then patterned. The main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 may be partially formed.

In the drawing, the main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 are spaced apart from each other by an interval from the edge of the gate line 110 and the edge of the data line 120, respectively, from an observer's point of view. Although shown, it may be overlaid with a minimum width.

As described above, according to the first embodiment of the present invention, a main pixel portion directly connected to the switching element TFT is formed in the central region of the unit pixel region, and a coupling capacitor is formed in the edge region of the unit pixel region. By forming a sub-pixel portion indirectly connected to the switching element TFT through, the kickback voltage of the main pixel portion may be significantly reduced.

This will be described in more detail with reference to FIG. 9.

9 is a plan view illustrating the transfer of a gate-source capacitor according to the present invention.

Referring to FIG. 9, the general gate-source capacitance Cgs1 is defined by the area where the gate wiring and the drain wiring are overlaid on the channel layer. The additional gate-source capacitance Cgs2 according to the present invention is defined by the area where the gate wiring 110 and the pixel electrode 142 are overlaid.

As such, by transferring the area of the additional gate-source capacitance Cgs2 from the main pixel to the sub pixel, the kickback voltage of the main pixel is significantly reduced. That is, the area ratio of the general gate-source capacitance Cgs1 and the additional gate-source capacitance Cgs2 is approximately 60 to 40.

The kickback voltage Vk is defined by Equation 1 below.

Where Cgs is a gate-to-source capacitance, Cst is a storage capacitance, Clc is a liquid crystal capacitance, Von is a gate-on voltage, and Voff is a gate-off voltage.

Therefore, it is advantageous for poor image quality due to RMS cause of pixels such as flicker characteristics.

In addition, the liquid crystal display of the PVA mode according to the present invention is effective in improving low gray afterimage. This is because the gamma curve of the subpixels maintains black until the middle gray scale.

Example-2

10 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention. FIG. 11 is a plan view of the array substrate 200 shown in FIG. 10. In particular, an array substrate having contact holes formed in the drain wiring in direct contact with the switching element TFT is shown.

10 and 11, the array substrate 200 according to the second embodiment of the present invention may include a gate wiring 210 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 210. 212, first and second lower storage patterns STL and STL2 formed to be parallel to the gate lines 210 in the unit pixel area while being spaced apart from the gate line 210, and a horizontal direction of the unit pixel area. The first coupling pattern CPL is divided into two parts.

The array substrate 200 is made of silicon nitride (SiNx) or the like, and includes a gate insulating layer 213 covering the gate wiring 210 and the gate electrode 212, and an active layer covering the gate electrode 212. 214. The active layer 214 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 200 includes a source wiring 220 extending in a vertical direction, a source electrode 222 extending from the source wiring 220, and a drain electrode 223 spaced apart from the source electrode 222 by a predetermined distance. ). The gate electrode 212, the semiconductor layer 214, the semiconductor impurity layer 215, the source electrode 222, and the drain electrode 223 define a thin film transistor TFT.

The array substrate 200 may include a first upper storage pattern 224 extending from the drain electrode 223, a first extension pattern 225 extending from the drain electrode 223 while being formed on the right side of a unit pixel area, The second coupling pattern 226 connected to the first extension pattern 225, the second extension pattern 227 and the second extension formed on the right side of the unit pixel area and connected to the first extension pattern 225. And a second upper storage pattern 228 connected to the pattern 227.

The array substrate 200 includes a passivation layer 230 and an organic insulating layer 232 sequentially stacked to expose a portion of the drain electrode 226 while covering the thin film transistor TFT. The passivation layer 230 and the organic insulating layer 232 cover and protect the channel layer 214 between the source electrode 222 and the drain electrode 223, and the thin film transistor TFT and the pixel electrode part. Serves to insulate 240. The channel layer 214 includes a semiconductor layer 214 and a semiconductor impurity layer 215 formed on the semiconductor layer 214.

The thickness (cell gap of the liquid crystal layer) of the liquid crystal layer 200 may be adjusted by adjusting the height of the organic insulating layer 232. Of course, the passivation layer 230 may be omitted.

The array substrate 200 includes a pixel electrode part having an opening pattern shape which is connected to the lower second coupling pattern 224 through the contact hole CNTST1.

In detail, the pixel electrode part includes a main electrode 244 and a sub electrode 242 which are respectively formed on the lower side and the upper side of the unit pixel area and connected through the right side of the unit pixel area. The main electrode 244 defines a wedge shape facing in the right direction, and the sub electrode 242 is formed in an area where the main electrode 244 is not formed.

The main electrode 244 is formed with two Y-shaped opening patterns in which the unit pixel area is mirror symmetrically about the central axis in the horizontal direction. The mirror symmetric Y-shaped branch has an angle of 90 degrees. The width of the sub electrode 242 formed by the opening pattern is preferably uniform.

Two opening patterns parallel to the Y-shaped branch are formed below the sub-electrode 242, and two opening patterns parallel to the Y-shaped branch are formed above the sub-electrode 242. An opening pattern is formed. The two opening patterns formed on the upper side of the sub electrode 242 are mirror-symmetric with respect to the two opening patterns formed on the lower side of the sub electrode 242 and the central axis in the horizontal direction.

The plurality of opening patterns are formed in the main and sub electrodes 244 and 242 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates in the future.

The main electrode 244 and the sub electrode 242 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

According to the first embodiment of the present invention described above, the kickback voltage of the main pixel is reduced by transferring the additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Image quality can be improved.

According to the second embodiment of the present invention described above, by reducing the number of organic film contact holes to two, it is possible to secure a margin for defects in the process and the organic film material.

In the general super-PVA structure, one point is formed at the overlay portion between the gate wiring and the source wiring, and two points are formed at the overlay portion between the common electrode layer of the lower substrate and the source wiring, whereas in the second embodiment of the present invention, the gate wiring and the source wiring are formed. Since one point is formed at the overlay portion between the common electrode layer and the source line of the lower substrate, the short point between the gate and the source can be reduced. The short point defect between the gate and the source is one of main defects in the process of covering the organic layer on the three-layered wiring (MoAlMo).

In the general super-PVA structure, two subpixels are formed and disadvantageous in inspection due to pixel defects, but according to the second embodiment of the present invention, by forming the subpixels as one, it is advantageous for pixel combining inspection, The time required for array inspection can be reduced.

Example-3

12 is a plan view illustrating a liquid crystal display panel according to a third exemplary embodiment of the present invention. FIG. 13 is a plan view of the array substrate 300 illustrated in FIG. 12. In particular, an array substrate is formed in which contact holes are formed in each of the storage wirings adjacent to the switching element TFT and the storage wirings in contact with each other and the width of the storage wiring in the central portion is increased.

12 and 13, the array substrate 300 according to the third exemplary embodiment of the present invention may include a gate wiring 310 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 310. 312, the first and second lower storage patterns STL1 and STL2 formed to be parallel to the gate lines 310 in the unit pixel area while being spaced apart from the gate line 310, and the width of the unit pixel area. The first coupling pattern CPL is divided into two directions.

The array substrate 300 is made of a material such as silicon nitride (SiNx), and a gate insulating layer (not shown) covering the gate wiring 310 and the gate electrode 312, and an active covering the gate electrode 312. Layer 314. The active layer 314 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 300 may include a source wiring 320 extending in a vertical direction, a source electrode 322 extending from the source wiring 320, and a drain electrode 323 spaced apart from the source electrode 322 by a predetermined distance. ). The gate electrode 312, the semiconductor layer 314, the semiconductor impurity layer 315, the source electrode 322, and the drain electrode 323 define a thin film transistor TFT.

The array substrate 300 extends from the drain electrode 323 and is formed on the left side of the first upper storage pattern 324 that exposes the first lower storage pattern STL1 and a unit pixel area, and thus the first upper storage. A first extension pattern 325 extending from the pattern 324, a second coupling pattern 326 connected to the first extension pattern 325, and a first extension pattern 325 formed on a left side of a unit pixel area; ) And a second upper storage pattern 328 connected to the second extension pattern 327 and the second extension pattern 327 to expose the second lower storage pattern STL2.

The array substrate 300 includes a passivation layer (not shown) and an organic insulating layer (not shown) that are sequentially stacked to cover a portion of the drain electrode 326 while covering the thin film transistor TFT. The passivation layer and the organic insulating layer cover and protect the channel layer 314 between the source electrode 322 and the drain electrode 323, and insulate the thin film transistor TFT from the pixel electrode part 340. Play a role. The channel layer 314 includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 300 includes a pixel electrode part having an opening pattern shape connected to the lower second coupling pattern 326 through a contact hole CNTCP.

In detail, the pixel electrode part may include a main electrode 344 contacting the second coupling pattern 326, a first sub electrode 342 contacting the first lower storage pattern STL1, and the first sub electrode 342. And a second sub electrode 346 contacting the second lower storage pattern STL2.

The main electrode 344 is formed with two Y-shaped opening patterns in which the unit pixel area is mirror symmetrically about the horizontal axis in the central axis. The mirror symmetric Y-shaped branch has an angle of 90 degrees. Two opening patterns are formed in the first sub-electrode 342 in parallel with the Y-shaped branch. The second sub-electrode 346 is formed with two opening patterns, which are parallel to the Y-shaped branch and are mirror-symmetrical with respect to the central axis in the horizontal direction, formed in the first sub-electrode 342. . The plurality of opening patterns are formed in the main electrode 344 and the first and second sub-electrodes 342 and 346 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates.

The main electrode 344 and the first and second sub electrodes 342 and 346 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

When viewed in plan view, a plurality of different domains are formed by the main electrode 344 and the first and second sub-electrodes 342 and 346, respectively. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

According to the third embodiment of the present invention described above, the kickback voltage of the main pixel is reduced by transferring the additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Image quality can be improved.

Example-4

14 is a plan view illustrating a liquid crystal display panel according to a fourth exemplary embodiment of the present invention. FIG. 15 is a plan view of the array substrate 400 shown in FIG. 14. In particular, an array substrate is shown in which the widths of the contact holes formed in the drain wiring adjacent to the switching element TFT and the drain wiring adjacent to the switching element and the storage wiring in the central portion are increased.

14 and 15, an array substrate 400 according to a fourth embodiment of the present invention includes a gate wiring 410 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 410. 412, the first and second lower storage patterns STL1 and STL2 formed to be parallel to the gate lines 410 in the unit pixel area while being spaced apart from the gate line 410, and the width of the unit pixel area. The first coupling pattern CPL is divided into two directions.

The array substrate 400 is made of a material such as silicon nitride (SiNx), and includes a gate insulating layer (not shown) covering the gate wiring 410 and the gate electrode 412, and an active covering the gate electrode 412. Layer 414. The active layer 414 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 400 includes a source wiring 420 extending in a vertical direction, a source electrode 422 extending from the source wiring 420, and a drain electrode 423 spaced apart from the source electrode 422 by a predetermined distance. ). The gate electrode 412, the semiconductor layer 414, the semiconductor impurity layer 415, the source electrode 422, and the drain electrode 423 define a thin film transistor TFT.

The array substrate 400 may include a first upper storage pattern 424, a first extension pattern 425, a second coupling pattern 426, a second extension pattern 427, and a second upper storage pattern 428. Include.

In detail, the first upper storage pattern 424 extends from the drain electrode 423 and is formed on the first lower storage pattern STL1. The first extension pattern 425 extends from the first upper storage pattern 424 while being formed in the center to vertically divide the unit pixel area. The second coupling pattern 426 is connected to the first extension pattern 425 and covers the first coupling pattern CPL. The second extension pattern 427 is formed at the center to vertically divide the unit pixel area and is connected to the first extension pattern 425. The second upper storage pattern 428 is formed on the second lower storage pattern STL2 while being connected to the second extension pattern 427.

The array substrate 400 includes a passivation layer (not shown) and an organic insulating layer (not shown) that are sequentially stacked to expose a portion of the drain electrode 426 while covering the thin film transistor TFT. The passivation layer and the organic insulating layer cover and protect the channel layer 414 between the source electrode 422 and the drain electrode 423, and insulate the thin film transistor TFT from the pixel electrode part 440. Play a role. The channel layer 414 includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 400 includes a pixel electrode part having an opening pattern shape that is connected to the lower second coupling pattern 426 through a contact hole CNTCP.

In detail, the pixel electrode part may include a main electrode 444 contacting the second coupling pattern 426, a first sub electrode 442 contacting the first lower storage pattern STL1, and the first sub electrode 442. And a second sub electrode 446 contacting the second lower storage pattern STL2.

The main electrode 444 is formed with two Y-shaped opening patterns in which a unit pixel area is mirror symmetrically about a central axis in a horizontal direction. The mirror symmetric Y-shaped branch has an angle of 90 degrees.

Two opening patterns are formed on the first sub-electrode 442 in parallel with the Y-shaped branch.

The second sub-electrode 446 is formed with two opening patterns, which are parallel to the Y-shaped branch and are mirror-symmetric with respect to the central axis in the horizontal direction, formed in the first sub-electrode 442. . The plurality of opening patterns are formed in the main electrode 444 and the first and second sub-electrodes 442 and 446 in order to divide the domain of the liquid crystal layer accommodated through the coalescence between the color filter substrates into a plurality.

The main electrode 444 and the first and second sub electrodes 442 and 446 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

When viewed in plan view, a plurality of different domains are formed by the main electrode 444 and the first and second sub-electrodes 442 and 446, respectively. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

According to the fourth embodiment of the present invention described above, the kickback voltage of the main pixel is reduced by transferring the additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Image quality can be improved.

Example-5

16 is a plan view illustrating a liquid crystal display panel according to a fifth exemplary embodiment of the present invention. 17 is a plan view of the array substrate 500 shown in FIG. 16. In particular, an array substrate is shown in which contact holes are formed in drain wirings close to the switching elements TFT, and the width of the storage wirings in the central portion is increased.

16 and 17, the array substrate 500 according to the fifth embodiment of the present invention may include a gate wiring 510 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 510. 512, a first lower storage pattern STL formed to be parallel to the gate lines 510 in a unit pixel area while being spaced apart from the gate line 510, and a second division that is divided in the horizontal direction of the unit pixel area. One coupling pattern CPL is included.

The array substrate 500 is made of a material such as silicon nitride (SiNx), and includes a gate insulating layer (not shown) covering the gate wiring 510 and the gate electrode 512, and an active covering the gate electrode 512. Layer 514. The active layer 514 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 500 includes a source wiring 520 extending in a vertical direction, a source electrode 522 extending from the source wiring 520, and a drain electrode 523 spaced apart from the source electrode 522 by a predetermined distance. ). The gate electrode 512, the semiconductor layer 514, the semiconductor impurity layer 515, the source electrode 522, and the drain electrode 523 define a thin film transistor TFT.

The array substrate 500 extends from the drain electrode 523 and is formed on the first lower storage pattern 524 formed on the first lower storage pattern STL, and is formed on the left side of the unit pixel area. A first extension pattern 525 extending from 524 and a second coupling pattern 526 connected to the first extension pattern 525 and covering the first coupling pattern CPL are included.

The array substrate 500 includes a passivation layer (not shown) and an organic insulating layer (not shown) that are sequentially stacked to cover a portion of the drain electrode 526 while covering the thin film transistor TFT. The passivation layer and the organic insulating layer cover and protect the channel layer 514 between the source electrode 522 and the drain electrode 523, and insulate the thin film transistor TFT from the pixel electrode part 540. Play a role. The channel layer 514 includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 500 includes a pixel electrode part having an opening pattern shape connected to the lower second coupling pattern 526 through a contact hole CNTCP.

In detail, the pixel electrode part includes a main electrode 544 and a sub electrode 542 which are respectively formed on the lower side and the upper side of the unit pixel area and connected through the right side of the unit pixel area. The main electrode 544 defines a wedge shape facing in the right direction, and the sub electrode 542 is formed in a region where the sub electrode 542 is not formed.

In the sub-electrode 542, two Y-shaped opening patterns in which a unit pixel area is mirror symmetrically about a horizontal axis in the horizontal direction are formed. The mirror symmetric Y-shaped branch has an angle of 90 degrees. The width of the sub electrode 542 formed by the opening pattern is preferably uniform.

Two opening patterns parallel to the Y-shaped branch are formed below the main electrode 544, and two opening patterns parallel to the Y-shaped branch are formed above the main electrode 544. An opening pattern is formed. The two opening patterns formed on the upper side of the main electrode 544 are mirror-symmetric with respect to the two opening patterns formed on the lower side of the main electrode 544 and the central axis in the horizontal direction.

The plurality of opening patterns are formed in the main and sub electrodes 544 and 542 to divide the domain of the liquid crystal layer accommodated through the coalescing between the color filter substrates into a plurality.

The main electrode 544 and the sub electrode 542 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

When viewed in plan view, a plurality of different domains are formed by the main electrode 544 and the sub electrode 542, respectively. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

According to the fifth embodiment of the present invention, the kickback voltage of the main pixel is transferred by transferring an additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Can be reduced to improve image quality defects.

According to the fifth embodiment of the present invention described above, by reducing the number of organic film contact holes to two, it is possible to secure a margin for defects in the process and the organic film material.

In the general super-PVA structure, one point is formed at the overlay portion between the gate wiring and the source wiring, and two points are formed at the overlay portion between the common electrode layer of the lower substrate and the source wiring, whereas in the fifth embodiment of the present invention, the gate wiring and the source wiring are formed. Since one point is formed at the overlay portion between the common electrode layer and the source line of the lower substrate, the short point between the gate and the source can be reduced. The short point defect between the gate and the source is one of main defects in the process of covering the organic layer on the three-layered wiring (MoAlMo).

In a general super-PVA structure, two subpixels are formed and disadvantageous in inspection due to pixel defects, but according to the fifth embodiment of the present invention, by forming subpixels in one, it is advantageous for pixel combining inspection, The time required for array inspection can be reduced.

<Example-6>

18 is a plan view illustrating a liquid crystal display panel according to a sixth embodiment of the present invention. 19 is a plan view of the array substrate 600 shown in FIG. 18. In particular, as compared with FIG. 1, a contact hole is formed in each of the drain wiring adjacent to the switching element TFT and the drain wiring adjacent to the switching element TFT. The array substrate is shown.

18 and 19, the array substrate 600 according to the sixth embodiment of the present invention may include a gate wiring 610 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 610. 612, first and second lower storage patterns STL1 and STL2 formed to be parallel to the gate lines 610 in a unit pixel area while being spaced apart from the gate line 610, and in a horizontal direction of the unit pixel area. The first coupling pattern CPL is divided into two parts.

The array substrate 600 is formed of a material such as silicon nitride (SiNx), and includes a gate insulating layer (not shown) covering the gate wiring 610 and the gate electrode 612, and an active covering the gate electrode 612. Layer 614. The active layer 614 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 600 includes a source wiring 620 extending in a vertical direction, a source electrode 622 extending from the source wiring 620, and a drain electrode 623 spaced apart from the source electrode 622 by a predetermined distance. ). The gate electrode 612, the semiconductor layer 614, the semiconductor impurity layer 615, the source electrode 622, and the drain electrode 623 define a thin film transistor TFT.

The array substrate 600 may include a first upper storage pattern 624, a first extension pattern 625, a second coupling pattern 626, a second extension pattern 627, and a second upper storage pattern 628. Include.

In detail, the first upper storage pattern 624 is formed on the first lower storage pattern STL1 while extending from the drain electrode 623. The first extension pattern 625 extends from the first upper storage pattern 624 while being formed in the center to vertically divide the unit pixel area. The second coupling pattern 626 is connected to the first extension pattern 625 and covers the first coupling pattern CPL. The second extension pattern 627 is formed in the center to vertically divide the unit pixel area and is connected to the first extension pattern 625. The second upper storage pattern 628 is connected to the second extension pattern 627 and is formed on the second lower storage pattern STL2.

The array substrate 600 includes a passivation layer (not shown) and an organic insulating layer (not shown) that are sequentially stacked to cover a portion of the drain electrode 626 while covering the thin film transistor TFT. The passivation layer and the organic insulating layer cover and protect the channel layer 614 between the source electrode 622 and the drain electrode 623, and insulate the thin film transistor TFT from the pixel electrode part 640. Play a role. The channel layer 614 includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 600 has a shape of an opening pattern that is opened, and includes a pixel electrode part connected to the second coupling pattern 626 under the contact hole CNTCP.

In detail, the pixel electrode part may include a main electrode 644 in contact with the second coupling pattern 626, a first sub-electrode 642 in contact with the first lower storage pattern STL1, and the first sub-electrode 642. ) And a second sub-electrode 646 contacting the second lower storage pattern STL2.

In the main electrode 644, two Y-shaped opening patterns are formed in which a unit pixel area is mirror symmetrically about a horizontal axis in a central axis. The mirror symmetric Y-shaped branch has an angle of 90 degrees.

Two opening patterns are formed in the first sub-electrode 642 in parallel with the Y-shaped branch.

The second sub-electrode 646 is formed with two opening patterns that are parallel to the Y-shaped branch and mirror-symmetric with respect to the central axis in the horizontal direction and the opening pattern formed in the first sub-electrode 642. . The plurality of opening patterns are formed in the main electrode 644 and the first and second sub-electrodes 642 and 446 in order to divide the domain of the liquid crystal layer accommodated through the coalescence between the color filter substrates into a plurality.

The main electrode 644 and the first and second sub electrodes 642 and 446 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

In a plan view, a plurality of different domains are formed by the main electrode 644 and the first and second sub-electrodes 642 and 446, respectively. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

According to the sixth embodiment of the present invention described above, the kickback voltage of the main pixel is reduced by transferring the additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Image quality can be improved.

According to the sixth embodiment of the present invention described above, the short wiring between the source wiring and the drain wiring can be prevented by arranging the drain wiring in the center of the unit pixel.

<Example-7>

20 is a plan view illustrating a liquid crystal display panel according to a seventh exemplary embodiment of the present invention. FIG. 21 is a plan view of the array substrate 700 shown in FIG. 20. In particular, an array substrate is formed in which contact holes are formed in the drain wirings in direct contact with the switching element TFT and the wirings connecting the adjacent drain wirings and the drain wirings in contact with each other are moved to the center of the pixel, as compared with FIG. 2. .

20 and 21, the array substrate 700 according to the seventh embodiment of the present invention may include a gate wiring 710 extending in a horizontal direction on the substrate, and a gate electrode extending from the gate wiring 710. 712, the first and second lower storage patterns STL1 and STL2 formed to be parallel to the gate lines 710 in a unit pixel area while being spaced apart from the gate line 710, and a horizontal direction of the unit pixel area. The first coupling pattern CPL is divided into two parts.

The array substrate 700 is made of a material such as silicon nitride (SiNx), and includes a gate insulating layer (not shown) covering the gate wiring 710 and the gate electrode 712, and an active covering the gate electrode 712. Layer 714. The active layer 714 includes a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 700 may include a source wiring 720 extending in a vertical direction, a source electrode 722 extending from the source wiring 720, and a drain electrode 723 spaced apart from the source electrode 722 by a predetermined distance. ). The gate electrode 712, the semiconductor layer 714, the semiconductor impurity layer 715, the source electrode 722, and the drain electrode 723 define a thin film transistor TFT.

The array substrate 700 may include a first upper storage pattern 724, a first extension pattern 725, a second coupling pattern 726, a second extension pattern 727, and a second upper storage pattern 728. Include.

In detail, the first upper storage pattern 724 extends from the drain electrode 723 and is formed on the first lower storage pattern STL1. The first extension pattern 725 extends from the first upper storage pattern 724 while being formed in the center to vertically divide the unit pixel area. The second coupling pattern 726 is connected to the first extension pattern 725 and covers the first coupling pattern CPL. The second extension pattern 727 is formed in the center to vertically divide the unit pixel area and is connected to the first extension pattern 725. The second upper storage pattern 728 is formed on the second lower storage pattern STL2 while being connected to the second extension pattern 727.

The array substrate 700 includes a passivation layer (not shown) and an organic insulating layer (not shown) that are sequentially stacked to expose a portion of the drain electrode 726 while covering the thin film transistor TFT. The passivation layer and the organic insulating layer cover and protect the channel layer 714 between the source electrode 722 and the drain electrode 723, and insulate the thin film transistor TFT from the pixel electrode part 740. Play a role. The channel layer 714 includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 700 has a shape of an opening pattern that is opened, and includes a pixel electrode part connected to the second coupling pattern 726 below through a contact hole CNTCP.

In detail, the pixel electrode part includes a main electrode 742 and a sub electrode 744 which are respectively formed on the lower side and the upper side of the unit pixel area and connected through the right side of the unit pixel area. The sub-electrode 744 defines a wedge shape facing in the right direction, and the main electrode 742 is formed in a region where the sub-electrode 744 is not formed.

The sub-electrode 744 is formed with two Y-shaped opening patterns in which the unit pixel area is mirror symmetrically about the central axis in the horizontal direction. The mirror symmetric Y-shaped branch has an angle of 90 degrees. The width of the sub-electrode 744 formed by the opening pattern is preferably uniform.

Two opening patterns parallel to the Y-shaped branch are formed below the main electrode 742, and two opening patterns parallel to the Y-shaped branch are formed above the main electrode 742. An opening pattern is formed. The two opening patterns formed on the upper side of the main electrode 742 are mirror symmetrically based on the two opening patterns formed on the lower side of the main electrode 742 and the central axis in the horizontal direction.

The plurality of opening patterns are formed in the main and sub electrodes 742 and 744 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates in the future.

The main electrode 742 and the sub electrode 744 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

According to the seventh embodiment of the present invention described above, the kickback voltage of the main pixel is reduced by transferring the additional gate-source capacitor Cgs area generated by overlaying the gate wiring and the pixel electrode from the main pixel to the sub pixel. Image quality can be improved.

According to the seventh embodiment of the present invention described above, by reducing the number of organic film contact holes to two, it is possible to secure a margin for defects in the process and the organic film material.

In the general super-PVA structure, one point is formed at the overlay portion between the gate wiring and the source wiring, and two points are formed at the overlay portion between the common electrode layer of the lower substrate and the source wiring, whereas in the seventh embodiment of the present invention, the gate wiring and the source wiring are formed. Since one point is formed at the overlay portion between the common electrode layer and the source line of the lower substrate, the short point between the gate and the source can be reduced. The short point defect between the gate and the source is one of main defects in the process of covering the organic layer on the three-layered wiring (MoAlMo).

In a general super-PVA structure, two subpixels are formed and disadvantageous in inspection due to pixel defects, but according to the seventh embodiment of the present invention, by forming the subpixels as one, it is advantageous for pixel combining inspection, The time required for array inspection can be reduced.

According to the seventh embodiment of the present invention described above, by disposing the drain wiring in the center of the unit pixel, it is possible to prevent the short circuit occurring between the source wiring and the drain wiring.

In the first to seventh embodiments of the present invention described above, the conversion of the main pixel and the sub pixel is performed in a structure in which one switching element is formed in the unit pixel region. Switching elements may also be formed through a structure formed in the unit pixel region.

<Example-8>

22 is a plan view illustrating a liquid crystal display panel according to an eighth embodiment of the present invention. FIG. 23 is a plan view of the array substrate 800 shown in FIG. 22. In particular, two switching elements TFTs are formed in a unit pixel area, and a region in which a switching element TFT having a drain electrode connected to a storage line of a central portion is formed is defined as a main pixel, and a drain connected to a storage line of an edge. The area in which the switching element TFT which has an electrode is formed is defined as the sub pixel.

22 and 23, an array substrate 800 according to an eighth embodiment of the present invention may include first and second gate wirings 810M and 810S extending in a horizontal direction in a unit pixel area, and the first substrate may be formed in the array substrate 800. And the first and second gate electrodes 812M and 812S extending from the second gate lines 810M and 810S, respectively, and spaced apart from the first and second gate lines 810M and 810S, respectively, in the unit pixel region. The first lower storage pattern STL is formed to be perpendicular to the first gate line 810M, and the first coupling pattern CPL divides the unit pixel region in two directions in the horizontal direction. The first coupling pattern CPL is connected to the first lower storage pattern STL in the right region of the unit pixel.

The array substrate 800 is formed of a material such as silicon nitride (SiNx), and includes a gate insulating layer covering the first and second gate wires 810M and 810S and the first and second gate electrodes 812M and 812S. Not shown) and first and second active layers 814M and 814S respectively covering the first and second gate electrodes 812M and 812S. The first and second active layers 814M and 814S include a semiconductor layer such as a-Si and a semiconductor impurity layer such as n + a-Si formed on the semiconductor layer.

The array substrate 800 includes a source wiring 820 extending in a vertical direction, first and second source electrodes 822M and 822S extending from the source wiring 820, and the first and second source electrodes. And first and second drain electrodes 823M and 823S spaced apart from each other by 822M and 822S. The first gate electrode 812M, the first active layer 814M, the first source electrode 822M, and the first drain electrode 823M define a main thin film transistor TFT. In addition, the second gate electrode 812S, the second active layer 814S, the second source electrode 822S, and the second drain electrode 823S define a sub thin film transistor TFT.

The array substrate 800 extends from the second drain electrode 823S and is formed on the right side of the upper storage pattern 824S formed on the first lower storage pattern STL and the unit pixel area, and the upper storage pattern 824S. And a first extension pattern 825S extending in.

The array substrate 800 includes a second coupling pattern 826 extending from the first drain electrode 823M and covering the first coupling pattern CPL.

The array substrate 800 may include a passivation layer (not shown) that is sequentially stacked to cover a portion of the upper storage pattern 824S and a portion of the second coupling pattern 826 while covering the main and sub thin film transistors. An organic insulating layer (not shown) is included.

The passivation layer and the organic insulating layer are formed between the first channel layer 814M between the first source electrode 822M and the first drain electrode 823M, and between the second source electrode 822S and the second drain electrode 823S. It covers and protects the second channel layer 814S, and insulates the main and sub thin film transistors from the pixel electrode part. Each of the first and second channel layers 814M and 814S includes a semiconductor layer and a semiconductor impurity layer formed on the semiconductor layer.

The array substrate 800 connects the main electrode portion 844 and the contact hole CNTST1 having an opening pattern shape which is electrically connected to the lower second coupling pattern 826 through a contact hole CNTCP. The sub electrode part 842 has an open shape while being electrically connected to the upper upper storage pattern 824S.

The main electrode part 844 defines a wedge shape facing in the right direction, and the sub electrode 842 is formed at an area where the sub electrode 842 is not formed, that is, under and above the unit pixel area.

The main electrode part 844 includes three V-shaped opening patterns connected to each other while being mirror-symmetrical about a unit pixel area about a central axis in a horizontal direction. Among the opening patterns, a large opening pattern and a medium opening pattern are connected at both edges, and the medium opening pattern and the small opening pattern are connected at the center portion. The V-shaped interior angle is 90 degrees. It is preferable that the width | variety of the said V-shaped opening pattern is uniform.

Two opening patterns parallel to the V-shaped opening pattern are formed below the sub-electrode 842, and two opening patterns parallel to the V-shaped opening pattern are formed above the sub-electrode 842. An opening pattern is formed. The two opening patterns formed on the upper side of the sub electrode 842 are mirror-symmetric with respect to the two opening patterns formed on the lower side of the sub electrode 842 and the central axis in the horizontal direction.

The plurality of opening patterns are formed in the main and sub electrodes 844 and 842 in order to divide a plurality of domains of the liquid crystal layer accommodated through coalescence between the color filter substrates.

The main electrode 844 and the sub electrode 842 may be formed of a transparent conductive material. Examples of such a transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZO), and the like.

When viewed in a plane, a plurality of different domains are formed by each of the main electrode 844 and the sub electrode 842. Accordingly, the step of rubbing the surface of the alignment film formed on the array substrate and the color filter substrate to align the liquid crystal in a predetermined direction may be omitted, and the alignment film may not be formed.

As described above, according to the present invention, in the PVA structure, the kickback voltage of the main pixel is reduced by transferring the area of the additional gate-source capacitor generated by overlapping the gate wiring and the pixel electrode from the main pixel to the sub pixel. As a result, poor image quality caused by the RMS cause of the pixel, such as flicker, can be improved.

In addition, since the gamma curve of the subpixel maintains black until the middle gray scale, it is effective in improving the low gray afterimage of the PVA.

In addition, by reducing the number of organic film contact holes to two, it is possible to secure a margin for defects in the process and the organic film material.

In addition, in the general super-PVA structure, one point is formed at the overlay portion between the gate wiring and the source wiring, and two points are formed at the overlay portion between the common electrode layer and the source wiring of the lower substrate. In the present invention, the overlay portion between the gate wiring and the source wiring is formed. Since one point is formed in the overlay portion between the common electrode layer and the source wiring of the lower substrate, the short point between the gate and the source can be reduced.

In addition, in the general super-PVA structure, two sub-pixels are formed and disadvantageous in inspection due to pixel defects, but according to the present invention, by forming the sub-pixels in one, it is advantageous for pixel combining inspection, The time required can be reduced.

Further, according to the present invention described above, by disposing the drain wiring in the center of the unit pixel, it is possible to prevent the short circuit occurring between the source wiring and the drain wiring.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (23)

A switching element formed in a unit pixel region defined by gate lines adjacent to each other and data lines adjacent to each other; A main pixel portion formed in a central region of the unit pixel region; A coupling capacitor having a first end coupled to the switching element; And A subpixel portion connected to a second end of the coupling capacitor and formed in a remaining region of the unit pixel region; The main pixel portion A first coupling pattern formed under the gate insulating layer; A second coupling pattern formed on the gate insulating layer to form the first coupling pattern and the coupling capacitor with the gate insulating layer interposed therebetween; And A main electrode contacted on the second coupling pattern; The sub pixel unit A first lower storage pattern formed under the gate insulating layer; A first upper storage pattern having a first contact hole and formed on the gate insulating layer to correspond to the first lower storage pattern; A first sub-electrode contacting an exposed portion of the first lower storage pattern through the first contact hole of the first upper storage pattern; A second lower storage pattern formed under the gate insulating layer; A second upper storage pattern having a second contact hole and formed on the gate insulating layer to correspond to the second lower storage pattern; And And a second sub-electrode contacting an exposed portion of the second lower storage pattern through the second contact hole of the second upper storage pattern. The array substrate of claim 1, wherein a plurality of opening patterns are formed in the main electrode. The array substrate of claim 1, wherein a plurality of opening patterns are formed in the first sub electrode and the second sub electrode. The array substrate of claim 1, wherein the main pixel portion is formed in an area in which the unit pixel area is divided in two while being parallel to the gate line. The array substrate of claim 1, wherein the main pixel unit is connected to the switching device. delete delete The array substrate of claim 1, wherein the main electrode is formed with two Y-shaped opening patterns that are mirror symmetrically about a horizontal axis of the unit pixel area. The array substrate of claim 8, wherein the first sub-electrode is formed with two opening patterns parallel to the Y-shaped branch. 10. The method of claim 9, wherein the second sub-electrode is formed in the opening pattern formed in the first sub-electrode parallel to the branch of the Y-shaped and two opening patterns are mirror-symmetric with respect to the central axis in the horizontal direction An array substrate. The array substrate of claim 1, wherein the main pixel unit includes a main capacitor having a main liquid crystal capacitor. The array substrate of claim 11, wherein the main capacitor further comprises a main storage capacitor. The array substrate of claim 1, wherein the sub pixel unit comprises a liquid crystal capacitor connected to the second end of the coupling capacitor. delete delete A main gate line formed in the unit pixel area; A main switching element connected to the main gate line; A main pixel part connected to the main switching element and formed in a central area of the unit pixel area; A sub gate line formed in the unit pixel area; A sub switching element connected to the sub gate line; And A sub pixel unit formed in the remaining area of the unit pixel area; The main pixel portion A first coupling pattern formed under the gate insulating layer; A second coupling pattern formed on the gate insulating layer to form a coupling capacitor and the first coupling pattern with the gate insulating layer interposed therebetween; And A main electrode part covering the second coupling pattern and formed on an organic insulating layer having a first contact hole, the main electrode part being in contact with an exposed portion of the second coupling pattern through the first contact hole, The sub pixel unit A lower storage pattern formed under the gate insulating layer to be perpendicular to the main gate line and the sub gate line, respectively; An upper storage pattern formed on the gate insulating layer to correspond to the lower storage pattern; And And a sub electrode part formed on the organic insulating layer covering the upper storage pattern and having a second contact hole, the sub electrode part being in contact with an exposed portion of the upper storage pattern through the second contact hole. The array substrate of claim 16, wherein the first coupling pattern is connected to the lower storage pattern in a right region of a unit pixel. An upper substrate having a common electrode layer; Liquid crystal layer; And The liquid crystal layer is accommodated through the coalescing with the upper substrate, the main pixel portion formed in the central region of the unit pixel region, the coupling capacitor connected to the switching element, the coupling capacitor, and connected to the unit pixel region. A lower substrate having a sub-pixel portion formed in the remaining region, The main pixel portion A first coupling pattern formed under the gate insulating layer; A second coupling pattern formed on the gate insulating layer to form the first coupling pattern and the coupling capacitor with the gate insulating layer interposed therebetween; And A main electrode contacted on the second coupling pattern; The sub pixel unit A lower storage pattern formed under the gate insulating layer; An upper storage pattern having a contact hole and formed on the gate insulating layer to correspond to the lower storage pattern; And And a sub electrode formed in contact with an exposed portion of the lower storage pattern through the contact hole of the upper storage pattern. The method of claim 18, wherein a plurality of opening patterns are formed in the main electrode, the sub electrode, and the common electrode layer, respectively. The opening patterns formed in the common electrode layer divide the liquid crystal layer into a plurality of domain regions in the unit pixel region. delete delete delete delete

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