CN1825599A

CN1825599A - Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same

Info

Publication number: CN1825599A
Application number: CNA2006100049263A
Authority: CN
Inventors: 田尚益; 金东奎
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2005-01-17
Filing date: 2006-01-16
Publication date: 2006-08-30
Anticipated expiration: 2026-01-16
Also published as: TW200642085A; KR101232618B1; KR20060083852A; CN100595926C; TWI400805B

Abstract

In an array substrate, an LCD panel having the same and an LCD device having the same, the array substrate may include an insulating substrate, a switching element (e.g., a transistor such as a TFT), a main pixel portion, a coupling capacitor and a sub-pixel portion. The switching element may be formed on the insulating substrate in a pixel region defined by gate and data lines adjacent to each other. The gate and data lines may be formed on the insulating substrate. The main pixel portion is on a first (e.g., central) portion of the pixel region. The coupling capacitor is electrically connected to the switching element. The coupling capacitor is on the insulating substrate. The sub-pixel portion is electrically connected to the coupling capacitor. The sub-pixel portion is on a second (e.g., peripheral) portion of the pixel region. Therefore, an image display quality is improved.

Description

Array substrate, the liquid crystal indicator that has the display panels of array substrate and have array substrate

Technical field

The present invention relates to a kind of array substrate, have liquid crystal display (LCD) panel of array substrate and LCD device with array substrate.Especially, the present invention relates to a kind of array substrate that can improve image displaying quality, have liquid crystal display (LCD) panel of array substrate and LCD device with array substrate.

Background technology

Usually, the LCD device can comprise array substrate, filter substrate and liquid crystal layer.Array substrate can comprise the thin-film transistor (TFT) of a plurality of control pixels.The filter substrate has common electrode.Liquid crystal layer is sealed between array substrate and the filter substrate.In response to the electric field that is applied to liquid crystal layer, the transmittance of liquid crystal layer changes, so display image.

Light transmissive variation is defined in the predetermined scope, and the LCD device has narrow relatively visual angle as a result.In order to increase the visual angle of LCD device, the LCD device can adopt vertical orientation (VA) pattern.

Adopt the LCD device of VA pattern configurations can comprise two substrates and liquid crystal layer, this liquid crystal layer with liquid crystal material with present negative anisotropic dielectric constant (dielectric constant) and combine.Liquid crystal in the liquid crystal layer is the pattern of vertical orientation.

In operation, when voltage was not applied on the substrate, liquid crystal was arranged in vertical direction, was used to show black.When equaling V at least ₀Voltage when being applied on the substrate (such as, to the electrode of array of controls substrate and the common electrode that is associated of filter substrate), liquid crystal is arranged on the direction of level, is used to demonstrate white.When less than V ₀Voltage when being applied on the substrate, liquid crystalline phase tilts for horizontal direction, is used to demonstrate grey, gray scale depends on the average orientation of the molecule of liquid crystal material.

In the small screen LCD device, the pattern that the LCD device is configured to adopt image vertically to adjust (PVA) is to increase the visual angle and to reduce gray-scale inversion.LCD device in the PVA pattern has pattern common electrode (patterned common electrode) and pattern pixel electrode (patterned pixel electrode).

In some obtainable LCD devices, be applied to the spread of voltage on each pixel, like this, the pixel flicker causes the deterioration of image displaying quality.

Summary of the invention

The invention provides a kind of array substrate that can improve image displaying quality.

The present invention provides a kind of liquid crystal display (LCD) panel with above-mentioned array substrate equally.

The present invention provides a kind of LCD device with above-mentioned array substrate equally.

Array substrate according to an aspect of the present invention can comprise dielectric substrate, switch element (such as, as transistorized switch, can be TFT), main pixel portion, coupling capacitor and inferior pixel portion.Switch element is positioned on the dielectric substrate of pixel region, and this pixel region is limited by gate line adjacent one another are and data wire.For example, pixel region can limit by first grid polar curve and the first adjacent data wire, and further can be by limiting with the continuous second grid line of first grid polar curve and with continuous second data wire of first data wire.Gate line and data wire all are positioned on the dielectric substrate.Main pixel portion is positioned at first's (such as core) of pixel region.Coupling capacitor is electrically connected to switch element.Coupling capacitor is positioned on the dielectric substrate.Inferior pixel portion is electrically connected to coupling capacitor.Inferior pixel portion is positioned at the second portion (such as the periphery) of pixel region.

Array substrate according to other aspects of the invention can comprise dielectric substrate, main grid polar curve, main switch, main pixel portion, inferior gate line, inferior switch and inferior pixel portion.Dielectric substrate has pixel region.The main grid polar curve is positioned on the pixel region.Main switch is positioned on the dielectric substrate.Main switch element is electrically connected to the main grid polar curve.Main pixel portion is positioned at the core of pixel region.Main pixel portion is electrically connected to main switch.Inferior gate line is positioned at pixel region.Inferior switch is positioned on the dielectric substrate.Inferior switch is electrically connected to time gate line.Inferior pixel portion is positioned at the periphery of pixel region.

LCD panel according to typical embodiment of the present invention can comprise substrate, following substrate and liquid crystal layer.Last substrate has transparent substrate and is positioned at common electrode on this transparent substrate.Following substrate can comprise dielectric substrate, main pixel, coupling capacitor and inferior pixel portion.Dielectric substrate has the pixel region that is limited by gate line adjacent one another are and data wire.Gate line and data line bit are on dielectric substrate.Main pixel portion is positioned at first's (such as core).Coupling capacitor is electrically connected on the switch element on the dielectric substrate.Inferior pixel portion is electrically connected to coupling capacitor.Inferior pixel portion is positioned at the periphery of pixel region.Liquid crystal layer is arranged between substrate and the following substrate.

The LCD device of typical embodiment can comprise substrate, following substrate and liquid crystal layer according to the present invention.Last substrate has transparent substrate and is positioned at common electrode on the transparent substrates.Following substrate can comprise dielectric substrate, gate line, data wire, switch element, main pixel, first coupling capacitor, pixel portion, second coupling capacitor and pixel portion for the second time for the first time.Gate line is positioned on the dielectric substrate, is used to transmit signal.Data line bit is used for transmission of data signals on dielectric substrate.Switch element is electrically connected to gate line and data wire.Switch element is positioned on the dielectric substrate.Main pixel portion is electrically connected to switch element.Main pixel portion is positioned on the dielectric substrate.First coupling capacitor has the first end that is electrically connected to switch element.Pixel portion is electrically connected to switch element by first coupling capacitor for the first time.Pixel portion is positioned on the dielectric substrate for the first time.Second coupling capacitor has the end that is electrically connected to switch element.Pixel portion is electrically connected to switch element by second coupling capacitor for the second time.Pixel portion is positioned on the dielectric substrate for the second time.Liquid crystal layer is arranged between substrate and the following substrate.

According to some embodiments of the present invention, whole gate-to-source electric capacity (gate-source capacitance) is divided into the additional gate-source capacitance of gate-to-source electric capacity and additional (additional) gate-to-source capacitor of gate-to-source capacitor.Gate-to-source capacitor and additional gate-source capacitance device is corresponding main electrode and sub-electrode respectively.As a result, the flyback voltage of main electrode (kickback voltage) is lowered, and the image displaying quality of LCD device improves.

Description of drawings

The present invention above-mentioned and other some aspects by following will be more apparent with reference to accompanying drawing to the detailed description of typical embodiment.Wherein:

Fig. 1 is for describing the vertical view of the LCD panel of typical embodiment according to the present invention;

Fig. 2 is the cross-sectional view along the line 1-1 ' among Fig. 1;

Fig. 3 is for describing the circuit diagram of the array substrate shown in Fig. 2;

Fig. 4 to 8 is the vertical view of the manufacture method of the array substrate shown in description Fig. 3;

Fig. 9 is for describing the vertical view of the gate-to-source capacitor of typical embodiment according to the present invention;

Figure 10 is for describing the vertical view of the LCD panel of another typical embodiment according to the present invention;

Figure 11 is for describing the vertical view of the array substrate shown in Figure 10;

Figure 12 is for describing according to the present invention the vertical view of the LCD panel of a typical embodiment again;

Figure 13 is for describing the vertical view of the array substrate shown in Figure 12;

Figure 14 is for describing the vertical view according to the LCD panel of another typical embodiment of the present invention;

Figure 15 is for describing the vertical view of the array substrate shown in Figure 14;

Figure 16 is for describing the vertical view of the LCD panel of another typical embodiment according to the present invention;

Figure 17 is for describing the vertical view of the array substrate shown in Figure 16;

Figure 18 is for describing the vertical view of the LCD panel of another typical embodiment according to the present invention;

Figure 19 is for describing the vertical view of the array substrate shown in Figure 18;

Figure 20 is for describing the vertical view according to the LCD panel of another typical embodiment of the present invention;

Figure 21 is for describing the vertical view of the array substrate shown in Figure 20;

Figure 22 is for describing the vertical view of the LCD panel of another typical embodiment according to the present invention; And

Figure 23 is for describing the vertical view of the array substrate shown in Figure 22.

Embodiment

Hereinafter with reference to accompanying drawing some embodiments of the present invention are described in further detail, some embodiments of the present invention shown in the drawings.Yet the present invention can be presented as multiple different form, and should not be interpreted as only limiting to the embodiment that goes out mentioned herein.Or rather, provide the purpose of these embodiment to be to make this disclosure, and can fully describe the present invention to those skilled in the art thoroughly with complete.In the accompanying drawings, for clarity, the size and the relative size in layer and zone can be exaggerated.

Be understandable that: " be connected in " or " being coupled in " another element or layer when going up when element or layer are called as " being positioned at ", it can be located immediately at, is connected in or is coupled on another element or the layer, perhaps has between two parties element or layer.On the contrary, when element is called as on " being located immediately at ", " being directly connected in " or " being coupled directly to " another element or the layer, then there are not between two parties element or layer.From start to finish, identical Reference numeral is represented components identical.As usage herein, term " and/or " comprise the project of listing that one or more is relevant arbitrarily with all combinations.

Be understandable that: although the term first, second, third, etc. can be used in herein, be used to describe various elements, yet these elements, parts, zone, layer and/or part should not limited by these terms.These terms only are to be used for an element, parts, zone, layer or part and another zone, layer or part etc. are distinguished.Therefore, first element of discussing below, parts, zone, layer or part can be called as second element, parts, zone, layer or part and not break away from instruction of the present invention.Mention " first " element or the like, and do not mean that " second " or other element must be arranged.

The term of spatial relationship, such as " ... down ", " below ", " low ", " top ", " top " or the like, can be used in herein, be used to simplify for the description of as shown in the drawing element or parts for the relation of other element or parts.Be understandable that: spatial relationship term intention comprises that this device is using or different location of removing outside the location shown in the accompanying drawing in service.For example, if with the device in accompanying drawing upset, then be described to be positioned at other element or parts " following " or " under " element will thereby be positioned in " top " of other element or parts.Therefore, term as an example " below " can not only comprise be positioned at above but also comprise be positioned at below.The spatial relationship descriptor that this device can otherwise be located (location of rotating 90 degree or adopting alternate manner) and is used in this should be done corresponding explanation.

The purpose of the term of Shi Yonging only is in order to describe specific embodiment herein, rather than intention restriction the present invention.Also comprise plural form as the singulative that uses herein, unless clearly pointed out other form in the literary composition.Also should understand further: when using term " to comprise " " comprising " here, be that explanation exists described parts, integral body, step, operation, element and/or assembly, but do not get rid of other one or the existence of more parts, integral body, step, operation, element, assembly and/or group.

Some embodiments of the present invention are described with reference to schematically enumerating of desirable embodiment of the present invention (and intermediate structure).Equally, as the variant of the shape shown in the result of manufacturing process and/or tolerance described, also be in the contemplation.Thereby embodiments of the invention should not be interpreted as only limiting to the given shape in zone shown here, but should comprise the variant in shape that produces such as owing to manufacturing.Such as, the zone that is mixed with impurity that is listed as rectangle typically has profile round or curve and/or has gradient at the edge of doping enrichment region, rather than makes binary system from doped region to doped region not and change.Similarly, the zone can cause imbedding the zone and by some doping between its surface that takes place to mix by imbedding of mix forming.Therefore, graphic zone is schematically in essence in the accompanying drawing, and their shape is not intended to enumerate the true form in the zone of device, and also is not intended to limit the scope of the invention.

Unless additionally limit the same meaning of a those of ordinary skill institute common sense in field under the meaning that all terms used herein (comprising technology and scientific terminology) have and the present invention.Also should understand further: should be understood that to have implication with they meaning unanimities in relevant technology such as those terms that limit at dictionary commonly used, and should not be understood that Utopian or the formal meaning of extreme, unless specially make such qualification herein.

Below, describe some embodiments of the present invention with reference to the accompanying drawings in detail.

Fig. 1 is for describing the vertical view of the LCD panel of typical embodiment according to the present invention.Fig. 2 is the cross-sectional view along the line 1-1 ' shown in Fig. 1.The typical embodiment of Fig. 1 and Fig. 2 shows transmission-type (transmissive type) LCD panel.

See figures.1.and.2, the LCD panel can comprise array substrate 100, liquid crystal layer 180 and filter substrate 190.Filter substrate 190 is combined with array substrate 100, so that liquid crystal layer 180 is arranged between array substrate 100 and the filter substrate 190.

Array substrate 100 can comprise: the gate line 110 that along continuous straight runs extends, be electrically connected to the gate electrode 112 of gate line 100, in pixel region, be provided with at interval with gate line 110 and with the parallel substantially first and second bottom memory pattern STL1 of gate line 110 with STL2 and pixel region is divided into first of two zones is connected pattern CPL.Array substrate 100 can comprise that a plurality of gate lines 110, a plurality of gate electrode 112, a plurality of pixel region and a plurality of first connect pattern CPL.

Array substrate 100 can comprise dielectric substrate 105, and this dielectric substrate 105 comprises silicon nitride, silicon dioxide and/or other insulating material.Array substrate 100 may further include gate insulator 113 and active layer 114.Gate insulator 113 is positioned on the dielectric substrate 105 with gate line 110 and gate electrode 112.Active layer 114 is positioned on the gate insulator 113 position relative with gate electrode 112.Active layer 114 comprises: such as the semiconductor layer of amorphous silicon, polysilicon and/or other suitable material; And the semiconductor layer that is mixed with impurity, comprise N+ amorphous silicon, N+ polysilicon and/or other suitable material.

Array substrate 100 can comprise the source electrode line that extends along the longitudinal direction, the drain electrode 123 that is electrically connected to the source electrode 122 on the source electrode line 120 and separates with source electrode 122.Array substrate 100 can comprise multiple source polar curve 120, multiple source electrode 122 and a plurality of drain electrode 123.Gate electrode 112, active layer 114 (comprising semiconductor layer and the semiconductor layer that is mixed with impurity), source electrode 122 and drain electrode 123 form one or more thin-film transistors (TFT).

Array substrate 100 may further include the first top memory pattern 124 that is electrically connected to drain electrode 123, be electrically connected to first of drain electrode 123 on the pixel region left side extends pattern 125, is electrically connected to first and extends second of pattern 125 and connect pattern 126, be electrically connected to first on the pixel region left side and extend second of pattern 125 and extend pattern 127 and be electrically connected to the second second top memory pattern 128 that extends pattern 127.

Gate line 110 can have single layer structure or sandwich construction.When gate line 110 had single layer structure, gate line 110 can comprise aluminium, calorize neodymium alloy or the like.When gate line 110 has sandwich construction, gate line can comprise have chromium, the underclad portion of molybdenum, molybdenum alloy and/or other suitable material and top section with aluminium, aluminium alloy and/or other suitable material.

Array substrate 100 may further include passivation layer 130 and organic insulator 132.Passivation layer 130 covers this TFT.Passivation layer 130 has contact hole with organic insulator 132, and drain electrode 123 is partly exposed by this hole.Active layer 114 between passivation layer 130 and organic insulator 132 protection source electrodes 122 and the drain electrode 123.TFT is by passivation layer 130 and organic insulator 132 and pixel electrode parts 140 electric insulations.Active layer 114 can comprise semiconductor layer and be mixed with (such as, implant impurity) semiconductor layer of impurity.

The height of control organic insulator 132 is so that the thickness of control liquid crystal layer 180.In certain embodiments, passivation layer 130 can be omitted.

Array substrate 100 may further include the pixel electrode parts 140 that are electrically connected to the drain electrode 123 of TFT by contact hole.Pixel electrode parts 140 have patterns of openings.

Especially, pixel electrode parts 140 can comprise main electrode 144, for the first time electrode 142 and electrode 146 for the second time.Main electrode 144 is electrically connected to second and connects pattern 126.Electrode 142 is electrically connected to the first bottom memory pattern STL1 for the first time.For the second time electrode 146 is spaced apart with electrode 142 for the first time, and is electrically connected to the second bottom memory pattern STL2.

Main electrode 144 has two Y shape patterns of openings, the center line symmetry of these two Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars that become an angle of 90 degrees approximately.For the first time electrode 142 has two linear patterns of openings, this patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in one parallel.For the second time electrode 146 has two linear patterns of openings, and this patterns of openings is parallel with in two adjacent bars of each Y shape patterns of openings another substantially.The linear patterns of openings 142 of electrode is with respect to the linear patterns of openings symmetry of center line with electrode 146 second time for the first time.Be in operation, a plurality of zones are formed at the position of the patterns of openings of the pixel electrode parts 140 that close in the liquid crystal layer 180.

Main electrode 144, first and second sub-electrodes 142,146 can comprise transparent electric conducting material, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " amorphous indium tinoxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent conductive material.

Filter substrate 190 can comprise transparent substrate 192, be positioned at color-filter lens layer 194 on the transparent substrates 192, be positioned at the common electrode 196 on the color-filter lens layer 194.Common electrode 196 covers the patterns of openings of pixel electrode parts 140, and is partly opened.Filter substrate 190 is connected on the array substrate 100, is used for liquid crystal layer 180 sealings.In this embodiment, liquid crystal layer 180 has vertical orientation (VA) pattern.

Described field (domains) forms by main electrode 144 and first, second sub-electrode 142,146, can be omitted so that (rubbing process) handled in the orientation of array substrate 100 and/or filter substrate 190.In addition, both alignment layers (alignment layer) (not shown) can be left in the basket equally.

Fig. 3 is for describing the circuit diagram of the array substrate shown in Fig. 2.

With reference to Fig. 3, the LCD device can comprise gate lines G L, data wire DL, thin-film transistor TFT, main pixel portion MP, the first coupling capacitor Ccp1, pixel portion SP1, the second coupling capacitor Ccp2 and pixel portion SP2 for the second time for the first time.

Signal is applied to thin-film transistor TFT by gate lines G L.Data-signal is applied to thin-film transistor TFT by data wire DL.

Main pixel portion MP can comprise host liquid crystal capacitor ClcM and primary storage capacitor CstM.The end of host liquid crystal capacitor ClcM is electrically connected to thin-film transistor TFT, and common voltage Vcom is applied to the other end of host liquid crystal capacitor ClcM.The end of primary storage capacitor CstM is electrically connected to thin-film transistor TFT, and storage voltage Vst is applied to the other end of primary storage capacitor CstM.

The end of the first coupling capacitor Ccp1 is electrically connected to thin-film transistor TFT, and the other end of the first coupling capacitor Ccp1 is electrically connected to pixel portion SP1 for the first time.

Pixel portion SP1 can comprise the first liquid crystal capacitor Clcs1 and the first holding capacitor Csts1 for the first time.The end of the first liquid crystal capacitor Clcs1 is electrically connected to the first coupling capacitor Ccp1, and common voltage is applied to the other end of the first liquid crystal capacitor Clcs1.The end of the first holding capacitor Csts1 is electrically connected to the first coupling capacitor Ccp1, and storage voltage Vst is applied to the other end of the first holding capacitor Csts1.

The end of the second coupling capacitor Ccp2 is electrically connected to thin-film transistor TFT, and the other end of the second coupling capacitor Ccp2 is electrically connected to pixel portion SP2 for the second time.

Pixel portion SP2 can comprise the second liquid crystal capacitor Clcs2 and the second holding capacitor Csts2 for the second time.The end of the second liquid crystal capacitor Clcs2 is electrically connected to the second coupling capacitor Ccp2, and common voltage Vcom is applied to the other end of the second liquid crystal capacitor Clcs2.The end of the second holding capacitor Csts2 is electrically connected to the second coupling capacitor Ccp2, and storage voltage Vst is applied to the other end of the second holding capacitor Csts2.

Fig. 4 to Fig. 8 is the vertical view of the manufacture method of the array substrate shown in description Fig. 3.Array substrate has a plurality of contact holes, these a plurality of contact holes respectively with the drain line adjacent and adjacent with the drain line that is spaced apart with TFT with TFT.Especially, Fig. 4 is for describing the vertical view of gate line.Fig. 5 is for describing the vertical view of active layer.Fig. 6 is for describing the vertical view of source electrode-drain line (source-drain lines).Fig. 7 is for describing the vertical view of organic insulator.Fig. 8 is for describing the vertical view of pixel electrode parts.

With reference to Fig. 2 and 4, one or more metal materials such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), tungsten (W) and/or other metal material are deposited on the dielectric substrate 105, therefore formed metal level, this dielectric substrate 105 comprises such as transparent insulating material such as glass, potteries.

The metal level that is deposited is formed pattern, be used to form that along continuous straight runs extends and the gate line 110 of configuration along the longitudinal direction, be electrically connected to the gate electrode 112 of gate line 110, at the parallel first and second bottom memory pattern STL1 of pixel region and gate line 110 with STL2L and pixel region is divided into first of two zones is connected pattern CPL.

Silicon nitride is deposited on the insulating barrier 105, and this insulating barrier 105 has gate line 110, gate electrode 112, the first and second bottom memory pattern STL1, STL2 and the first connection pattern CPL, is used to form gate insulator 113.In this typical embodiment, silicon nitride is deposited on the insulating barrier 105 by the chemical vapour desposition process quilt, and gate insulator 113 is deposited on the whole insulating barrier 105.As selection, gate insulator 113 is formed pattern, and like this, the gate insulator that is formed pattern only is positioned on gate line 110, gate electrode 112, the first and second bottom memory pattern STL1, STL2 and the first connection pattern CPL.

With reference to Fig. 5, amorphous silicon layer and N+ amorphous silicon layer are formed on the gate insulator 113.Amorphous silicon layer and N+ amorphous silicon layer are formed pattern, are used for forming on gate electrode 112 active layer 114.

One or more metals such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al), chromium (Cr), copper (Cu), tungsten (W) and/or other metal are deposited on the gate insulator 113, therefore formed metal level, this gate insulator 113 has active layer 114.

With reference to Fig. 6, the metal level of deposition is formed pattern, the drain electrode 123 that is used to form data wire 120, is electrically connected to the source electrode 122 of data wire 120, is spaced apart with source electrode 122 respectively, respectively be electrically connected to the first top memory pattern 124 of drain electrode 123, be electrically connected to first of drain electrode 123 respectively and extend pattern 125, be electrically connected to first respectively and extend second of pattern 125 and is connected pattern 126, is electrically connected to first respectively and extends second stored pattern 128 that second of pattern 125 extends pattern 127 and is electrically connected to the second extension pattern 127 respectively.

The first contact hole CNTST1 is formed on each first top memory pattern 124.Each second connection pattern 126 covers each first connection pattern CPL and pixel region is divided into two districts.The second contact hole CNTST2 is formed on each second top memory pattern 128.

With reference to Fig. 2 and Fig. 7, passivation layer 130 and organic insulator 132 are formed on the gate insulator 113, and this gate insulator 113 has active layer 114, data wire 120, source electrode 122, drain electrode 123, the first top memory pattern 124, the first extension pattern 125, the second connection pattern 126, the second extension pattern 127 and second stored pattern 128.In this typical embodiment, drain line comprises that the first top memory pattern 124, first extends pattern 125, second and connects pattern 126, the second extension pattern 127 and second stored pattern 128.

A part and the organic insulator 132 of the passivation layer 130 in the pixel region are partly removed, and are used to form the 3rd contact hole CNTST3 corresponding to the first contact hole CNTST1, corresponding to the 4th contact hole CNTST4 of the second contact hole CNTST2 and corresponding to second the 5th contact hole CNTCP that connects pattern 126.The pixel region of array substrate is restricted to the zone on border by continuous gate line 110 and data wire 120.

With reference to Fig. 2 and Fig. 8, pixel electrode parts 140 are formed on the organic insulator 132.Pixel electrode parts 140 are electrically connected on each first bottom memory pattern STL1 by the first and the 3rd contact hole CNTSTL1 and CNTST3, and are electrically connected to the second bottom memory pattern STL2 by the second and the 4th contact hole CNTSTL2 and CNTST4.In addition, pixel electrode parts 140 are electrically connected to the second connection pattern 126 by the 5th contact hole CNTCP.

Especially, pixel electrode parts 140 can comprise: main electrode 144, this main electrode are electrically connected to second and connect pattern 126; Electrode 142 for the first time, this, electrode was electrically connected to the first bottom memory pattern STL1 first time; And electrode 146 for the second time, electrode 146 was electrically connected to the second bottom memory pattern STL2 and was spaced apart with the first bottom memory pattern STL1 second time this.

Main electrode 144 has two Y shape patterns of openings, the center line symmetry of these two Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars that become 90 degree interior angles to form approximately.For the first time electrode 142 has two linear patterns of openings, this linearity patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in one parallel.For the second time electrode 146 has two linear patterns of openings, and this linearity patterns of openings is parallel with in two adjacent bars of each Y shape patterns of openings another substantially.The linear patterns of openings center line symmetry mutually of the linear patterns of openings of electrode 142 and electrode 146 second time for the first time.Be in operation, a plurality of zones are formed at the position of the patterns of openings of the pixel electrode parts 140 that are adjacent to array substrate, in the liquid crystal layer 180 of this array substrate between array substrate and filter substrate.

Main electrode 144 and first and

second sub-electrodes

142 and 146 comprise such as indium tin oxide " indiumtin oxide (ITO) ", amorphous state indium tin oxide " indium tin oxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " one or more transparent electric conducting materials of zinc oxide (ZO) and/or other transparent conductive material.Transparent electric conducting material can be coated on the organic insulator 132, and is formed pattern, is used to form main electrode 144, first and second sub-electrodes 142 and 146.As selection, the main electrode 144 and first and second sub-electrodes 142,146 can form by the technology that differs from one another.

In this typical embodiment, main electrode 144, first,

second sub-electrode

142 and 146 are intervally installed.As selection, main electrode 144 can be partly overlapping by first and second sub-electrodes 142,146.

According to this typical embodiment of the present invention, main pixel portion is positioned at the core of pixel region, and inferior pixel portion is positioned at the periphery of pixel region.Inferior pixel portion is electrically connected to thin-film transistor by coupling capacitor.Therefore, the flyback voltage of main pixel portion is lowered.

Fig. 9 is for describing the vertical view of the gate-to-source capacitor of typical embodiment according to the present invention.

With reference to Fig. 9, gate-to-source capacitor Cgs1 limits by gate line 110 and the overlapping of drain line 120 on active layer.In this typical embodiment, extra gate-to-source capacitor Cgs2 is limited by the overlapping institute of gate line 110 and pixel electrode 142.

All gate-to-source electric capacity are divided into the gate-to-source electric capacity of gate-to-source capacitor Cgs1 and the extra gate-to-source electric capacity of extra gate-to-source capacitor Cgs2.The extra gate-to-source electric capacity of extra gate-to-source capacitor Cgs2 is corresponding to inferior pixel portion, and according to following equation 1, the flyback voltage of main pixel portion is lowered like this.In this typical embodiment, gate-to-source capacitor Cgs1 is about 60: 40 with the area ratio of extra gate-to-source capacitor Cgs2.

Following equation 1 expression flyback voltage Vk.

Equation 1

Vk＝Cgs·(Von-Voff)/(Cgs+Cst+Clc)

Cgs, Cst, Clc, Von, Voff represent that respectively gate-to-source electric capacity, storage capacitance, liquid crystal capacitance, grid are opened voltage (gate on voltage) and grid is closed voltage (gate off voltage).

By reducing flyback voltage, some display defects can be reduced or eliminate.For example, the error that is caused by the root mean square (RMS) of pixel voltage can be reduced such as flicker.

In addition, between zero gray scale and intermediate gray-scale, inferior pixel portion demonstrates black, has therefore reduced the after image of low gray scale.

Figure 10 is the vertical view of the LCD panel of another typical embodiment of description the present invention.Figure 11 is for describing the vertical view of the array substrate shown in Figure 10.Array substrate has contact hole on the layer of the position that drain electrode adjacent films transistor (TFT) forms.

With reference to Fig. 2,10 and 11, array substrate 200 can comprise the gate line 210 that along continuous straight runs extends, the gate electrode 212 that is electrically connected to gate line 210, pixel region be spaced apart with gate line 210 and parallel with the gate line 210 substantially first and second bottom memory pattern STL1 with STL2 and pixel region is divided into first of two zones is connected pattern CPL.In certain embodiments, array substrate 200 can comprise that a plurality of gate lines 210, a plurality of gate electrode 212, a plurality of pixel region and a plurality of first connect pattern CPL, and wherein pixel region is limited by continuous gate line 210 and data wire 220.

Array substrate 200 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 200 may further include gate insulator (not shown) and active layer 214.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 210 and gate electrode 212.Active layer 214 is positioned on the gate insulator (not shown) corresponding to gate electrode 212.Active layer 214 comprises: semiconductor layer, this semiconductor layer have amorphous silicon, polysilicon and/or other semi-conducting material; Be mixed with impurity (such as, implant) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or other are mixed with the material of impurity.

The drain electrode 223 that array substrate 200 may further include along the longitudinal direction the source electrode line 220 that extends, the source electrode 222 that is electrically connected to source electrode line 220, is spaced apart with source electrode 222.In certain embodiments, array substrate 200 can comprise multiple source polar curve 220, multiple source electrode 222 and a plurality of drain electrode 223.Each gate electrode 212, each semiconductor layer, semiconductor layer, each source electrode 222 and each drain electrode 223 that each is mixed with impurity form relevant thin-film transistor (TFT).

Array substrate 200 may further include: the first top memory pattern 224 that is electrically connected to drain electrode 223; Be electrically connected to the first extension pattern 225 of the drain electrode 223 on the pixel region left side; Be electrically connected to second of the first extension pattern 225 and connect pattern 226; Be electrically connected to first on the pixel region left side and extend the second extension pattern 227 of pattern 225; And the second top memory pattern 228 that is electrically connected to the second extension pattern 227.In this typical embodiment, the first top memory pattern 224, first extends pattern 225, second and connects pattern 226, the second extension pattern 227 and second stored pattern, 228 formation drain lines.

Array substrate 200 may further include passivation layer 230 and organic insulator 232.Passivation layer 230 covers this TFT.Passivation layer 230 and organic insulator 232 have contact hole, and drain electrode 223 is partly exposed by this contact hole.Active layer 214 between passivation layer 230 and organic insulator 232 protection source electrodes 222 and the drain electrode 223.This TFT is by passivation layer 230 and organic insulator 232 and pixel electrode parts electric insulation.Active layer 214 can comprise semiconductor layer and be mixed with the semiconductor layer of impurity.

The height that can control organic insulator 232 is so that the thickness of control liquid crystal layer 200.In certain embodiments, passivation layer 230 can be omitted.

Array substrate 200 may further include the pixel electrode parts that are electrically connected to the second connection pattern 224 by contact hole CNTST1.The pixel electrode parts have patterns of openings.

Especially, the pixel electrode parts can comprise main electrode 244 and sub-electrode 242.Main electrode 244 is to the outstanding wedge shaped in the right side of pixel region.Sub-electrode 242 is positioned on the remaining part that does not form on main electrode 244 pixel regions.

In the embodiment shown, main electrode 244 has two Y shape patterns of openings, the center line symmetry of this Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two the adjacent bars (rods) that form about 90 degree interior angles.Sub-electrode 242 is divided into a plurality of parts.In an illustrated embodiment, each part of sub-electrode 242 has constant width substantially.

Sub-electrode 242 has four linear patterns of openings.In the linear patterns of openings two substantially with two adjacent bars of each Y shape patterns of openings in top one parallel.Two remaining linear patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in following one parallel.Substantially with two adjacent bars of each Y shape patterns of openings in top one parallel two linear patterns of openings with substantially with two adjacent bars of each Y shape patterns of openings in two linear patterns of openings center line symmetry mutually of a following parallel remainder.

In the operation of the LCD device that comprises array substrate 200, a plurality of zones (domains) is formed at the position of the patterns of openings of being close to the pixel electrode parts that are arranged in liquid crystal layer, and this liquid crystal layer is between array substrate 200 and filter substrate.

Main electrode 244 and sub-electrode 242 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " amorphous indium tin oxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent conductive material.

According to this typical embodiment, total gate-to-source electric capacity is divided into the gate-to-source electric capacity of gate-to-source capacitor and the extra gate-to-source electric capacity of extra gate-to-source capacitor.The corresponding sub-electrode 242 of the extra gate-to-source electric capacity of extra gate-to-source capacitor, like this, the flyback voltage of main electrode 244 is lowered.Therefore, the image displaying quality of LCD device improves.

In addition, as described below, the quantity of the contact hole on the organic insulator only is two, and this contact hole can improve the reliability of LCD device.

Herein among the typical embodiment of Tao Luning, a contact hole is formed between layer that forms gate line 210 and the layer that forms source electrode line 220, and another contact hole is formed between 220 layers of the layer that forms the pixel electrode parts and the formation source electrode lines.The structure of other of LCD device has three contact holes: contact hole is at the layer that forms gate line and form between the layer of source electrode line, and in addition two contact holes the layer that forms the pixel electrode parts with form source electrode line layer between.Because each contact hole has increased the possibility that forms short circuit, shown embodiment has reduced the layer that forms gate line 210 and has formed the possibility of short circuit between the layer of source electrode line 220.Short circuit between the layer of the layer of formation gate line 210 and formation source electrode line 220 may cause the LCD device to break down.

In addition, in an illustrated embodiment, have only a sub-electrode to be formed at each pixel region.The number that is sub-electrode is reduced, so that detection arrays substrate 200 easily.This may reduce the fault time of LCD device.

Figure 12 is the vertical view of the LCD panel of another typical embodiment of description the present invention.Figure 13 is for describing the vertical view of the array substrate shown in Figure 12.Contact hole is formed on the storage line of contiguous TFT and is positioned on the storage line that is spaced apart with TFT.The width of the core of storage line is greater than the width of storage line remaining part.

With reference to Figure 12 and 13, array substrate 300 can comprise: the gate line 310 of Yan Shening in the horizontal direction; Be electrically connected to the gate electrode 312 of gate line 310; In pixel region, be spaced apart and first and second parallel with gate line 310 substantially bottom memory pattern STL1 and the STL2 with gate line 310; And the first connection pattern CPL that pixel region is divided into two zones.In certain embodiments, array substrate 300 can comprise that a plurality of gate lines 310, a plurality of gate electrode 312, a plurality of pixel region and a plurality of first connect pattern CPL, and wherein pixel region limits by continuous gate line 310 and data wire 320.

Array substrate 300 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 300 may further include gate insulator (not shown) and active layer 314.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 310 and gate electrode 312.Active layer 314 is positioned on the gate insulator (not shown) corresponding to gate electrode 312.Active layer 314 has: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; The semiconductor layer that contains (such as implanted) of impurity, this semiconductor layer comprise that N+ amorphous silicon, N+ polysilicon and/or other are mixed with the material of impurity.

Array substrate 300 can comprise: the source electrode line 320 of Yan Shening along the longitudinal direction; Be electrically connected to the source electrode 322 of source electrode line 320; And the drain electrode 323 that is spaced apart with source electrode 322.In certain embodiments, array substrate 300 can comprise multiple source polar curve 320, multiple source electrode 322 and a plurality of drain electrode 323.Each gate electrode 312, each semiconductor layer, semiconductor layer, each source electrode 322 and each drain electrode 323 that each is mixed with impurity form the thin-film transistor (TFT) that is associated.

Array substrate 300 may further include: the first top memory pattern 324, and this first top memory pattern 324 is electrically connected to drain electrode 323 and has opening, and STL1 is partly exposed by this lower opening portion stored pattern; First extends pattern 325, and this first extension pattern 325 is electrically connected to the first top memory pattern 324 on the pixel region left side; Second connects pattern 326, and this second connection pattern 326 is electrically connected to first and extends pattern 325; Second extends pattern 327, and this second extension pattern 327 is electrically connected to first on the pixel region left side and extends pattern 325; And the second top memory pattern 328, this second top memory pattern 328 is electrically connected to second and extends pattern 327 and have opening, and the second bottom memory pattern STL2 is partly exposed by this opening.In this typical embodiment, the first top memory pattern 324, first extends pattern 325, second and connects pattern 326, the second extension pattern 327 and second stored pattern, 328 formation drain lines.

Array substrate 300 may further include passivation layer (not shown) and organic insulator (not shown).The passivation layer (not shown) covers TFT.Passivation layer (not shown) and organic insulator (not shown) have contact hole, are partly exposed by this contact hole drain electrode 323.Active layer 314 between passivation layer (not shown) and organic insulator (not shown) protection source electrode 322 and the drain electrode 323.TFT is by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.Active layer 314 can comprise the semiconductor layer of semiconductor layer and implant impurity.

Array substrate 300 may further include the pixel electrode parts, and these pixel electrode parts are electrically connected to second by contact hole CNTCP and connect pattern 326.

Especially, the pixel electrode parts can comprise main electrode 344, for the first time electrode 342 and electrode 346 for the second time.Main electrode 344 is electrically connected to second by contact hole CNTCP and connects pattern 326.Electrode 342 is electrically connected to the first bottom memory pattern STL1 for the first time.For the second time electrode 346 be electrically connected to the second bottom memory pattern STL2 and with the first time electrode 342 be spaced apart.

In an illustrated embodiment, main electrode 344 has two Y shape patterns of openings, the center line symmetry of this Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars that form about 90 degree interior angles.For the first time electrode 342 has two linear patterns of openings, these two linear patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in one parallel.For the second time electrode 346 has two linear patterns of openings, and these two patterns of openings are parallel with in two adjacent bars of each Y shape patterns of openings another substantially.The linear patterns of openings center line symmetry mutually of the linear patterns of openings of electrode 342 and electrode 346 second time for the first time.In the operation of the LCD device that comprises array substrate 300, a plurality of zones are formed at the position of the patterns of openings of being close to the pixel electrode parts that are arranged in liquid crystal layer, and liquid crystal layer is between array substrate 300 and filter substrate.

Main electrode 344 and first,

second sub-electrode

342 and 346 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " indium tinoxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

Described zone is formed by main electrode 344, first and second sub-electrodes 342,346, and like this, orientation (rubbering) process of array substrate and/or filter substrate can be omitted.In addition, both alignment layers also can be omitted.

According to this typical embodiment, total gate-to-source electric capacity is divided into the gate-to-source electric capacity of gate-to-source capacitor and the extra gate-to-source electric capacity of extra gate-to-source capacitor.Corresponding first and

second sub-electrodes

342 and 346 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 344 is lowered, and the image displaying quality of LCD device improves.

Figure 14 is the vertical view of the LCD device of another typical embodiment of the present invention.Figure 15 is for describing the vertical view of the array substrate shown in Figure 14.In an illustrated embodiment, contact hole is formed on the drain line of contiguous TFT, on the drain line that is spaced apart with TFT and on the core of storage line.The width of the part of the drain line that contact hole is formed thereon is greater than the width of drain line remaining part.The width of the core of storage line is greater than the width of storage line remaining part.

With reference to Figure 14 and 15, array substrate 400 can comprise: the gate line 410 of Yan Shening in the horizontal direction; Be electrically connected to the gate electrode 412 of gate line 410; In pixel region, be spaced apart and first and second parallel with gate line 410 substantially bottom memory pattern STL1 and the STL2 with gate line 410; And the first connection pattern CPL that pixel region is divided into two districts.In certain embodiments, array substrate 400 can comprise that a plurality of gate lines 410, a plurality of gate electrode 412, a plurality of pixel region and a plurality of first connect pattern CPL, and wherein pixel region limits by continuous gate line 410 and data wire 420.

Array substrate 400 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 400 may further include gate insulator (not shown) and active layer 414.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 410 and gate electrode 412.Active layer 414 is positioned on the gate insulator (not shown) corresponding to gate electrode 412.Active layer 414 has: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; Mix impurity (such as, implanted) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or other contain the material of impurity.

Array substrate 400 can comprise: at the source electrode line 420 of longitudinal direction extension; Be electrically connected to the source electrode 422 of source electrode line 420; The drain electrode 423 that is spaced apart with source electrode 422.In certain embodiments, array substrate 400 can comprise multiple source polar curve 420, multiple source electrode 422 and a plurality of drain electrode 423.Each gate electrode 412, each semiconductor layer, semiconductor layer, each source electrode 422 and each drain electrode 423 that each is mixed with impurity form the thin-film transistor (TFT) that is associated.

Array substrate 300 may further include: the first top memory pattern 424, the first extends pattern 425, second and connects pattern 426, the second extension pattern 427 and second stored pattern 428.In this typical embodiment, the first top memory pattern 424, the first extends pattern 425, second and connects pattern 426, the second extension pattern 427 and second stored pattern, 428 formation drain lines.In certain embodiments, array substrate 300 (should be 400) may further include a plurality of first top memory patterns 424, a plurality of first extension pattern 425, a plurality of second connects pattern 426, a plurality of second and extends pattern 427 and a plurality of second stored pattern 428.

The first top memory pattern 424 is electrically connected to drain electrode 423, the first top memory patterns 424 and is positioned on the first bottom memory pattern STL1.First extends pattern 425 is electrically connected to the first top memory pattern 424 that is positioned on the pixel region left side.As selection, first extends pattern 425 can be positioned on the core of pixel region.As selection, second connects pattern 426 is electrically connected to the first extension pattern 425 and covers the first connection pattern CPL.The second extension pattern 427 is electrically connected to first on the pixel region left side and extends pattern 425.As selection, second extends the core that pattern 427 can be positioned at pixel region.The second top memory pattern 428 is electrically connected to second and extends on the pattern 427, and the second top memory pattern 428 is positioned on the second bottom memory pattern STL2.

Array substrate 400 may further include passivation layer (not shown) and organic insulator (not shown).The passivation layer (not shown) covers TFT.Passivation layer (not shown) and organic insulator (not shown) have contact hole, are partly exposed by this contact hole drain electrode 423.Active layer 414 between passivation layer (not shown) and organic insulator (not shown) protection source electrode 422 and the drain electrode 423.TFT is by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.Active layer 414 can comprise the semiconductor layer of semiconductor layer and implant impurity.

Array substrate 400 may further include the pixel electrode parts, and these pixel electrode parts are electrically connected to second by contact hole CNTCP and connect pattern 426.

Especially, the pixel electrode parts can comprise main electrode 444, for the first time electrode 442 and electrode 446 for the second time.Main electrode 444 is electrically connected to second by contact hole CNTCP and connects pattern 426.Electrode 442 is electrically connected to the first bottom memory pattern STL1 for the first time.For the second time electrode 446 be electrically connected to the second bottom memory pattern STL2 and with the first time electrode 442 be spaced apart.

In an illustrated embodiment, main electrode 444 has two Y shape patterns of openings, the center line symmetry of these two Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars (rod) that form about 90 degree interior angles.

For the first time electrode 442 has two linear patterns of openings, these two linear patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in one parallel.

For the second time electrode 446 has two linear patterns of openings, and these two patterns of openings are parallel with in two adjacent bars of each Y shape patterns of openings another substantially.The linear patterns of openings center line symmetry mutually of the linear patterns of openings of electrode 442 and electrode 446 second time for the first time.In the operation of the LCD device that comprises array substrate 400, a plurality of zones are formed at the position of the patterns of openings of being close to the pixel electrode parts that are arranged in liquid crystal layer, and liquid crystal layer is between array substrate 400 and filter substrate.

Main electrode 444 and first, second sub-electrode 442,446 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " indium tinoxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

Described zone is formed by main electrode 444, first and second sub-electrodes 442,446, and like this, orientation (rubbering) process of array substrate and/or filter substrate can be omitted.In addition, the both alignment layers (not shown) also can be omitted.

second sub-electrodes

442 and 446 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 444 is lowered.Therefore, the image displaying quality of LCD device improves.

Figure 16 is the vertical view of the LCD device of description another typical embodiment of the present invention.Figure 17 is for describing the vertical view of the array substrate shown in Figure 16.In an illustrated embodiment, contact hole is formed on the drain line of contiguous TFT.The width of the core of storage line is greater than the width of storage line remaining part.

With reference to Figure 16 and 17, array substrate 500 can comprise: the gate line 510 of Yan Shening in the horizontal direction; Be electrically connected to the gate electrode 512 of gate line 510; Parallel with gate line 510 substantially bottom memory pattern STL; And the first connection pattern CPL that pixel region is divided into two districts.In certain embodiments, array substrate 500 can comprise that a plurality of gate lines 510, a plurality of gate electrode 512, a plurality of pixel region, a plurality of bottom memory pattern STL and a plurality of first connect pattern CPL, and wherein pixel region limits by continuous gate line 210 and data wire 220.

Array substrate 500 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 500 may further include gate insulator (not shown) and active layer 514.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 510 and gate electrode 512.Active layer 514 is positioned on the gate insulator (not shown) corresponding to gate electrode 512.Active layer 514 has: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; Infiltrate impurity (such as, implanted) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or other contain the material of impurity.

Array substrate 500 can comprise: at the source electrode line 520 of longitudinal direction extension; Be electrically connected to the source electrode 522 of source electrode line 520; The drain electrode 523 that is spaced apart with source electrode 522.In certain embodiments, array substrate 500 can comprise multiple source polar curve 520, multiple source electrode 522 and a plurality of drain electrode 523.Each gate electrode 512, each semiconductor layer, semiconductor layer, each source electrode 522 and each drain electrode 523 that each is mixed with impurity form the thin-film transistor (TFT) that is associated.

Array substrate 500 may further include: the first top memory pattern 524 that is electrically connected to drain electrode 523; Be electrically connected to the first extension pattern 525 of the first top memory pattern 524 on first pixel region left side; And be electrically connected to the first extension pattern 525 to cover the second connection pattern 526 of the first connection pattern CPL.In certain embodiments, array substrate 500 may further include a plurality of first top memory patterns 524, a plurality of first extension pattern 525, a plurality of second connects pattern 526.In this typical embodiment, the first top memory pattern 524, first extends pattern 525 and is connected pattern 526 formation drain lines with second.

Array substrate 500 may further include passivation layer (not shown) and organic insulator (not shown).Passivation layer (not shown) and organic insulator (not shown) cover TFT.Active layer 514 between passivation layer (not shown) and organic insulator (not shown) protection source electrode 522 and the drain electrode 523.TFT is by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.Active layer 514 can comprise semiconductor layer and be mixed with the semiconductor layer of impurity.

Array substrate 500 may further include the pixel electrode parts, and these pixel electrode parts are electrically connected to second by contact hole CNTCP and connect pattern 526.The pixel electrode parts have patterns of openings.

Especially, the pixel electrode parts can comprise main electrode 544 and sub-electrode 542.Main electrode 544 is to the outstanding wedge shaped in the right side of pixel region.Sub-electrode 542 is positioned on the remaining part of the pixel region that does not form main electrode 544.

In an illustrated embodiment, main electrode 544 has two Y shape patterns of openings, the center line symmetry of this Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars that form about 90 degree interior angles.Sub-electrode 542 is divided into a plurality of parts.Each part of sub-electrode 542 has constant substantially width.

Sub-electrode 542 has four linear patterns of openings.Two linear patterns of openings parallel with one on top in two adjacent bars of each Y shape patterns of openings substantially.Two remaining linear patterns of openings are parallel with one of bottom in two adjacent bars of each Y shape patterns of openings substantially.Two substantially with two adjacent bars of each Y shape patterns of openings in the linear patterns of openings that parallels of one on top with remaining two substantially with two adjacent bars of each Y shape patterns of openings in the parallel linear patterns of openings in bottom center line symmetry mutually.

As selection, sub-electrode 542 can have wedge shaped and Y shape patterns of openings, and main electrode 544 can have linear patterns of openings.

In the operation of the LCD device that comprises array substrate 500, a plurality of zones are formed at the position of the patterns of openings of being close to the pixel electrode parts that are arranged in liquid crystal layer, and liquid crystal layer is between array substrate 500 and filter substrate.

Main electrode 544 and sub-electrode 542 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " indium tin oxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

Described zone is formed by main electrode 544 and sub-electrode 542, and like this, the process of alignment of array substrate 500 and/or filter substrate can be omitted.In addition, the both alignment layers (not shown) also can be omitted.

According to this typical embodiment, total gate-to-source electric capacity is divided into the gate-to-source electric capacity of gate-to-source capacitor and the extra gate-to-source electric capacity of extra gate-to-source capacitor.The corresponding sub-electrode 542 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 544 is lowered.Therefore, the image displaying quality of LCD device improves.

Herein among the typical embodiment of Tao Luning, a contact hole is formed between layer that forms gate line 510 and the layer that forms source electrode line 520, and another contact hole is formed between 520 layers of the layer that forms the pixel electrode parts and the formation source electrode lines.The structure of other of LCD device has three contact holes: a contact hole is between the layer of layer that forms gate line and formation source electrode line 520, and two contact holes are between the layer of layer that forms the pixel electrode parts and formation source electrode line in addition.Because each contact hole has increased the possibility that forms short circuit, the possibility of short circuit between the layer that shown embodiment has reduced to form the layer of gate line 510 and form source electrode line 520.Short circuit between the layer of the layer of formation gate line 510 and formation source electrode line 520 may cause the LCD device to break down.

In addition, in an illustrated embodiment, have only a sub-electrode to be formed at each pixel region.Be that the number of sub-electrode is reduced so that detection arrays substrate 500 easily.This can reduce the fault time of LCD device.

Figure 18 is for describing the vertical view according to the LCD panel of another typical embodiment of the present invention.Figure 19 is for describing the vertical view of the array substrate shown in Figure 18.In an illustrated embodiment, contact hole is formed on the drain line of contiguous TFT, on the drain line that is spaced apart with TFT and on the storage line.First and second extend pattern center line setting along pixel region on the longitudinal direction of pixel region.

With reference to Figure 18 and 19, array substrate 600 can comprise: the gate line 610 of Yan Shening in the horizontal direction; Be electrically connected to the gate electrode 612 of gate line 610; Be spaced apart with gate line 610 and first and second parallel with gate line 610 substantially bottom memory pattern STL1 and the STL2 at pixel region; And the first connection pattern CPL that pixel region is divided into two districts.In certain embodiments, array substrate 600 can comprise that a plurality of gate lines 610, a plurality of gate electrode 612, a plurality of pixel region and a plurality of first connect pattern CPL.

Array substrate 600 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 600 may further include gate insulator (not shown) and active layer 614.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 610 and gate electrode 612.Active layer 614 is positioned on the gate insulator (not shown) corresponding to gate electrode 612.Active layer 614 has: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; Contain impurity (such as, be injected into) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or it are mixed with the material of impurity.

Array substrate 600 can comprise: at the source electrode line 620 of longitudinal direction extension; Be electrically connected to the source electrode 622 of source electrode line 620; The drain electrode 623 that is spaced apart with source electrode 622.In certain embodiments, array substrate 600 can comprise multiple source polar curve 620, multiple source electrode 622 and a plurality of drain electrode 623.Each gate electrode 612, each semiconductor layer, semiconductor layer, each source electrode 622 and each drain electrode 623 that each is mixed with impurity form the thin-film transistor (TFT) that is associated.

Array substrate 600 may further include: the first top memory pattern 624, the first extends pattern 625, second and connects pattern 626, the second extension pattern 627 and the second top memory pattern 628.In certain embodiments, array substrate 600 may further include a plurality of first top memory patterns 624, a plurality of first extension pattern 625, a plurality of second connects pattern 626, a plurality of second and extends pattern 627 and a plurality of second top memory pattern 628.In this typical embodiment, the first top memory pattern 624, the first extends pattern 625, second and connects pattern 626, the second extension pattern 627 and second stored pattern, 628 formation drain lines.

Especially, the first top memory pattern 624 is electrically connected to drain electrode 623, the first top memory patterns 624 and is positioned on the first bottom memory pattern STL1.First extends the first top memory pattern 624 on the center line that pattern 625 is electrically connected to the pixel region that is positioned at the pixel line longitudinal direction.Second connects pattern 626 is electrically connected to the first extension pattern 625 and covers the first connection pattern CPL.Second extends first on the center line that pattern 627 is electrically connected to pixel region in a longitudinal direction extends pattern 625.The second top memory pattern 628 is electrically connected to second and extends pattern 627, and the second top memory pattern 628 is positioned on the second bottom memory pattern STL2.

Array substrate 600 can comprise passivation layer (not shown) and organic insulator (not shown) further.The passivation layer (not shown) covers TFT.Passivation layer (not shown) and organic insulator (not shown) have contact hole, are partly exposed by this contact hole drain electrode 623.Active layer 614 between passivation layer (not shown) and organic insulator (not shown) protection source electrode 622 and the drain electrode 623.TFT is by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.Active layer 614 can comprise semiconductor layer and be mixed with the semiconductor layer of impurity.

Array substrate 600 may further include the pixel electrode parts, and these pixel electrode parts are electrically connected to second by contact hole CNTCP and connect pattern 626.

Especially, the pixel electrode parts can comprise main electrode 644, for the first time electrode 642 and electrode 646 for the second time.Main electrode 644 is electrically connected to second by contact hole CNTCP and connects pattern 626.Electrode 642 is electrically connected to the first bottom memory pattern STL1 for the first time.For the second time electrode 646 be electrically connected to the second bottom memory pattern STL2 and with the first time electrode 642 be spaced apart.

In an illustrated embodiment, main electrode 644 has two Y shape patterns of openings, the center line symmetry of this Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars (rod) that form about 90 degree interior angles.

For the first time electrode 642 has two linear patterns of openings, these two linear patterns of openings substantially with two adjacent bars of each Y shape patterns of openings in one parallel.

For the second time electrode 646 has two linear patterns of openings, and these two patterns of openings are parallel with in two adjacent bars of each Y shape patterns of openings another substantially.The linear patterns of openings center line symmetry mutually of the linear patterns of openings of electrode 642 and electrode 646 second time for the first time.In the operation of the LCD device that comprises array substrate 600, a plurality of zones are formed at the position of the patterns of openings that is adjacent to the pixel electrode parts that are arranged in liquid crystal layer, and liquid crystal layer is between array substrate 600 and filter substrate.

Main electrode 644 and first, second sub-electrode 642,646 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " indium tinoxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

A plurality of zones are formed by main electrode 644, first and second sub-electrodes 642,646, and like this, the process of alignment of array substrate and/or filter substrate can be omitted.In addition, the both alignment layers (not shown) also can be omitted.

second sub-electrodes

642 and 646 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 644 is lowered.Therefore, the image displaying quality of LCD device improves.

In addition, first and second extend

pattern

625 and 627 is positioned on the center line of pixel region, short circuit occurs between the layer that is used to prevent to form the layer of source electrode line 620 and form gate line 610.

Figure 20 is for describing the vertical view according to the LCD device of another typical embodiment of the present invention.Figure 21 is for describing the vertical view of array substrate shown in Figure 20.In an illustrated embodiment, contact hole is formed on the drain line that is spaced apart with TFT.First and second extend pattern center line setting along pixel region on the longitudinal direction of pixel region.

With reference to Figure 20 and 21, array substrate 700 can comprise: the gate line 710 of Yan Shening in the horizontal direction; Be electrically connected to the gate electrode 712 of gate line 710; Be spaced apart with gate line 710 and first and second parallel with gate line 710 substantially bottom memory pattern STL1 and the STL2 at pixel region; And the first connection pattern CPL that pixel region is divided into two districts.In certain embodiments, array substrate 700 can comprise that a plurality of gate lines 710, a plurality of gate electrode 712, a plurality of pixel region and a plurality of first connect pattern CPL, and wherein pixel region limits by continuous gate line 210 and data wire 220.

Array substrate 700 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 700 may further include gate insulator (not shown) and active layer 714.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has gate line 710 and gate electrode 712.Active layer 714 is positioned on the gate insulator (not shown) corresponding to gate electrode 712.Active layer 714 has: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; Contain impurity (such as, be injected into) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or other are mixed with the material of impurity.

Array substrate 700 can comprise: at the source electrode line 720 of longitudinal direction extension; Be electrically connected to the source electrode 722 of source electrode line 720; The drain electrode 723 that is spaced apart with source electrode 722.In certain embodiments, array substrate 700 can comprise multiple source polar curve 720, multiple source electrode 722 and a plurality of drain electrode 723.Each gate electrode 712, each semiconductor layer, semiconductor layer, each source electrode 722 and each drain electrode 723 that each is mixed with impurity form the thin-film transistor (TFT) that is associated.

Array substrate 700 may further include: the first top memory pattern 724, the first extends pattern 725, second and connects pattern 726, the second extension pattern 727 and the second top memory pattern 728.In certain embodiments, array substrate 700 may further include a plurality of first top memory patterns 724, a plurality of first extension pattern 725, a plurality of second connects pattern 726, a plurality of second and extends pattern 727 and a plurality of second top memory pattern 728.In this typical embodiment, the first top memory pattern 724, the first extends pattern 725, second and connects pattern 726, the second extension pattern 727 and second stored pattern, 728 formation drain lines.

Especially, the first top memory pattern 724 is electrically connected to drain electrode 723, the first top memory patterns 724 and is positioned on the first bottom memory pattern STL1.First extends the first top memory pattern 724 on the center line that pattern 725 is electrically connected to the pixel region that is positioned at the pixel line longitudinal direction.Second connects pattern 726 is electrically connected to the first extension pattern 725 and covers the first connection pattern CPL.Second extends first on the center line that pattern 727 is electrically connected to pixel region in a longitudinal direction extends pattern 725.The second top memory pattern 728 is electrically connected to second and extends pattern 727, and the second top memory pattern 728 is positioned on the second bottom memory pattern STL2.

Array substrate 700 may further include passivation layer (not shown) and organic insulator (not shown).The passivation layer (not shown) covers TFT.Passivation layer (not shown) and organic insulator (not shown) have contact hole, are partly exposed by this contact hole drain electrode 723.Active layer 714 between passivation layer (not shown) and organic insulator (not shown) protection source electrode 722 and the drain electrode 723.TFT is by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.Active layer 714 can comprise semiconductor layer and be mixed with the semiconductor layer of impurity.

Array substrate 700 may further include the pixel electrode parts, and these pixel electrode parts are electrically connected to second by contact hole CNTCP and connect pattern 726.

Especially, the pixel electrode parts can comprise main electrode 742 and sub-electrode 744.Sub-electrode 744 has to the outstanding wedge shaped in pixel region right side.Main electrode 742 is positioned on the remaining part of the pixel region that does not form sub-electrode 744.

In an illustrated embodiment, sub-electrode 744 has two Y shape patterns of openings, the center line symmetry of this Y shape patterns of openings relative pixel region on the horizontal direction of pixel region.The core of each Y shape patterns of openings has two adjacent bars that form about 90 degree interior angles.Sub-electrode 744 is divided into a plurality of parts by Y shape patterns of openings.Each part of sub-electrode 744 has constant substantially width.

Main electrode 742 has four linear patterns of openings.In the linear patterns of openings two parallel with one on top in two adjacent bars of each Y shape patterns of openings substantially.Two of remainders in the linear patterns of openings are parallel with one of bottom in two adjacent bars of each Y shape patterns of openings substantially.Substantially with two adjacent bars of each Y shape patterns of openings in parallel two the linear patterns of openings in one on top with substantially with two adjacent bars of each Y shape patterns of openings in two linear patterns of openings of the parallel remainder in bottom center line symmetry mutually.

In the operation of the LCD device that comprises array substrate 700, a plurality of zones are formed at the position of the patterns of openings of being close to the pixel electrode parts that are arranged in liquid crystal layer, and liquid crystal layer is between array substrate 700 and filter substrate.

Main electrode 742 and sub-electrode 744 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous state indium tin oxide " indium tin oxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

According to this typical embodiment, total gate-to-source electric capacity is divided into the gate-to-source electric capacity of gate-to-source capacitor and the extra gate-to-source electric capacity of extra gate-to-source capacitor.The corresponding sub-electrode 742 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 744 is lowered.Therefore, the image displaying quality of LCD device improves.

Herein among the typical embodiment of Tao Luning, a contact hole is formed between layer that forms gate line 710 and the layer that forms source electrode line 720, and another contact hole is formed between 720 layers of the layer that forms the pixel electrode parts and the formation source electrode lines.The structure of other of LCD device has three contact holes: contact hole is at the layer that forms gate line and form between the layer of source electrode line, in addition two contact holes layer that the pixel electrode parts form and source electrode line form layer between.Because each contact hole has increased the possibility that forms short circuit, the possibility of short circuit between the layer that shown embodiment has reduced to form the layer of gate line 710 and form source electrode line 720.Short circuit between the layer of the layer of formation gate line 710 and formation source electrode line 720 may cause the LCD device to break down.

In addition, in an illustrated embodiment, have only a sub-electrode to be formed at each pixel region.Be that the number of sub-electrode is reduced so that detection arrays substrate 200 easily.This can reduce the fault time of LCD device.

And first and second extend

pattern

725 and 727 is positioned on the center line of pixel region, short circuit occurs between the layer that is used to prevent to form the layer of source electrode line 720 and form gate line 710.

In this typical embodiment, a TFT is formed in each pixel region.In certain embodiments, a plurality of TFT can be formed in each pixel region.

Figure 22 is for describing the vertical view according to the LCD device of another typical embodiment of the present invention.Figure 23 is for describing the vertical view of the array substrate shown in Figure 22.In an illustrated embodiment, two TFT are formed at each pixel region.Main pixel is positioned at the core of pixel region, and inferior pixel is positioned on the periphery of pixel region.

With reference to Figure 22 and 23, array substrate 800 can comprise: first grid polar curve 810M of Yan Shening and second grid line 810S in the horizontal direction; Be electrically connected to first, second gate electrode 812M and the 812S of first grid polar curve 810M and second grid line 810S respectively; Be spaced apart with second grid line 810S and first vertical with the first grid polar curve 810M substantially bottom memory pattern STL with first grid polar curve 810M at pixel region; And the first connection pattern CPL that pixel region is divided into two zones.First connects pattern CPL is electrically connected to the first bottom memory pattern STL adjacent with the right side of pixel region.In certain embodiments, array substrate 800 can comprise that a plurality of first bottom memory pattern STL are connected pattern CPL with a plurality of first.

Array substrate 800 can comprise the dielectric substrate (not shown), and this dielectric substrate comprises silicon nitride, silica and/or other insulating material.Array substrate 800 may further include gate insulator (not shown) and first, second active layer 814M and 814S.The gate insulator (not shown) is positioned on the dielectric substrate (not shown), and this dielectric substrate has first grid polar curve 810M and second grid line 810S and first, second gate electrode 812M and 812S.First, second active layer 814M and 814S lay respectively on the gate insulator (not shown) corresponding to first, second gate electrode 812M and 812S.First, second active layer 814M and 814S have: semiconductor layer, this semiconductor layer comprise amorphous silicon, polysilicon and/or other semi-conducting material; Contain impurity (such as, be injected into) semiconductor layer, this semiconductor layer comprises that N+ amorphous silicon, N+ polysilicon and/or other are mixed with the material of impurity.

Array substrate 800 can comprise: at the source electrode line 820 of longitudinal direction extension; Be electrically connected to first, second source electrode 822M and the 822S of source electrode line 820; First, second drain electrode 823M and the 823S that are spaced apart with first, second source electrode 822M and 822S.In certain embodiments, array substrate 800 can comprise multiple source polar curve 820.Each first grid electrode 812M, each semiconductor layer, semiconductor layer, each first source electrode 822M and each first drain electrode 823M that each is mixed with impurity form the main thin-film transistor (TFT) that is associated.Each second gate electrode 812S, each second source electrode 822S and each second drain electrode 823S form the inferior TFT that is associated.

Array substrate 800 may further include: the first extension pattern 825M that is electrically connected to the left side in the first drain electrode 823M and neighborhood pixels zone; Being electrically connected to first extends pattern 825M and is positioned at the first first top memory pattern 824M that connects on the pattern CPL; Be electrically connected to the second drain electrode 823S and be positioned at the second top memory pattern 824S on the first bottom memory pattern STL; And the second extension pattern 825S that is electrically connected to the right side in the second top memory pattern 824S and neighborhood pixels zone.In certain embodiments, array substrate 800 may further include a plurality of first extension pattern 825M, a plurality of first top memory pattern 824M, a plurality of second top memory pattern 824S and a plurality of second extend pattern 825S.In this typical embodiment, the first top memory pattern 824M and first extends pattern 825M and forms first drain line, and the second top memory pattern 824S and second extends pattern 825S and forms second drain line.

Array substrate 800 may further include the second connection pattern 826 that is electrically connected to the first drain electrode 823M and covers first and connects pattern CPL.In certain embodiments, array substrate 800 may further include a plurality of second connection patterns 826.

Array substrate 800 may further include passivation layer (not shown) and organic insulator (not shown).The passivation layer (not shown) covers main TFT and time TFT.Passivation layer (not shown) and organic insulator (not shown) have contact hole, are connected pattern 826 by this contact hole second top memory pattern 824S with second and are partly exposed.

Passivation layer (not shown) and organic insulator (not shown) are protected the first active layer 814M between the first source electrode 822M and the first drain electrode 823M and the second active layer 814S between the second source electrode 822S and the second drain electrode 823S.Main TFT and time TFT are by passivation layer (not shown) and organic insulator (not shown) and pixel electrode parts electric insulation.First, second active layer 814M and 814S can comprise semiconductor layer and be mixed with the semiconductor layer of impurity.

Array substrate 800 may further include main electrode 844 and sub-electrode 842.Main electrode 844 is electrically connected to second by contact hole CNTCP and connects pattern 826.Sub-electrode 842 is electrically connected to the second stored pattern 824S by the first contact hole CNTST1.

Main electrode 844 has to the outstanding wedge shaped in pixel region right side.Sub-electrode 842 is positioned on the remaining part of the pixel region that does not form main electrode 844.

Main electrode 844 has two V-arrangement patterns of openings, the center line symmetry of this V-arrangement patterns of openings relative pixel region on the horizontal direction of pixel region.One less end sections in the V-arrangement patterns of openings is opened.One less core in the V-arrangement patterns of openings is closed.One bigger core in the V-arrangement patterns of openings is opened.The core of each V-arrangement patterns of openings has two adjacent bars that form about 90 degree interior angles.Main electrode 844 is divided into a plurality of parts by the V-arrangement patterns of openings.The separated part of main electrode 844 is electrically connected to each other.Each part of main electrode 844 has constant substantially width.

Sub-electrode 842 has four linear patterns of openings.In the linear patterns of openings two parallel with one on top in two adjacent bars of each Y shape patterns of openings substantially.Two of remainders in the linear patterns of openings are parallel with one of bottom in two adjacent bars of each Y shape patterns of openings substantially.Substantially with two adjacent bars of each Y shape patterns of openings in parallel two the linear patterns of openings in one on top with substantially with two adjacent bars of each Y shape patterns of openings in two linear patterns of openings of the parallel remainder in bottom center line symmetry mutually.

In the operation of the LCD device that comprises array substrate 800, a plurality of zones are formed at the position of patterns of openings of the pixel electrode parts of contiguous liquid crystal layer.

Main electrode 844 and sub-electrode 842 comprise the electric conducting material that one or more are transparent, such as indium tin oxide " indium tin oxide (ITO) ", amorphous indium and tin oxide " indium tin oxide (a-ITO) ", indium-zinc oxide " indium zinc oxide (IZO) ", zinc oxide " zinc oxide (ZO) " and/or other transparent electric conducting material.

A plurality of zones are formed by main electrode 844 and sub-electrode 842, and like this, the process of alignment of array substrate and/or filter substrate can be omitted.In addition, the both alignment layers (not shown) also can be omitted.

According to some embodiments of the present invention, total gate-to-source electric capacity is divided into the gate-to-source electric capacity of gate-to-source capacitor and the extra gate-to-source electric capacity of extra gate-to-source capacitor.The corresponding sub-electrode 842 of the extra gate-to-source electric capacity of extra gate-to-source capacitor.As a result, the flyback voltage of main electrode 844 is lowered.Therefore, the image displaying quality of LCD device improves.

In addition, inferior pixel portion is rendered as black between zero gray scale and middle gray, has therefore reduced the after image of low gray scale.

And the number of the contact hole on the organic insulator is reduced, and this can improve the reliability of LCD device.

Herein among the embodiment of Tao Luning, a contact hole is formed between layer that forms gate line and the layer that forms source electrode line, another contact hole be formed at the layer that forms the pixel electrode parts and form source electrode line layer between.The structure of other of LCD device has three contact holes: a contact hole is between the layer of layer that forms gate line and formation source electrode line, and two contact holes are between the layer of layer that forms the pixel electrode parts and formation source electrode line in addition.Because each contact hole has increased the possibility that forms short circuit, the possibility of short circuit between the layer that shown embodiment has reduced to form the layer of gate line and form source electrode line.

In addition, have only a sub-electrode to be formed at each pixel region.That is, the number of sub-electrode is reduced so that detection arrays substrate easily, and the manufacturing time of LCD device can be reduced.

Moreover the part at the pixel region center line of drain line can reduce the possibility that occurs short circuit between source electrode line and the drain line.

The present invention is illustrated with reference to typical embodiment.Yet it should be apparent that according to aforesaid explanation, the modifications and variations that plurality of optional is selected are conspicuous for those skilled in the art.Therefore, the present invention includes all these selectable modifications and variations.The spirit and scope of the present invention are defined by the claims.

Claims

1, a kind of array substrate comprises:

Dielectric substrate;

Be arranged in the switch on the dielectric substrate of pixel region, this pixel region is limited by first grid polar curve and the first adjacent data wire, and the first grid polar curve and first data line bit are on dielectric substrate;

Be positioned at the main pixel portion on the pixel region, this main pixel portion comprises main capacitance;

Coupling capacitor, this coupling capacitor has the first end that is electrically connected to described switch; And

Inferior pixel region, this time pixel region comprise that at least one is electrically connected to the electric capacity of the second end of coupling capacitor.

2, array substrate as claimed in claim 1, wherein a plurality of patterns of openings are formed on the main pixel portion.

3, array substrate as claimed in claim 1, wherein a plurality of patterns of openings are formed on time pixel portion.

4, array substrate as claimed in claim 1, wherein main pixel portion is divided into two zones along first grid polar curve with pixel region.

5, array substrate as claimed in claim 1, wherein, main pixel portion is electrically connected to described switch, and wherein this switch comprises transistor.

6, array substrate as claimed in claim 1, wherein, main pixel portion comprises:

Be positioned at second on the dielectric substrate and connect pattern; And

Be positioned at this second main electrode that connects on the pattern, this main electrode is electrically connected to second and connects pattern.

7, array substrate as claimed in claim 6, wherein time pixel portion comprises:

Be positioned at the first bottom memory pattern on the dielectric substrate;

Be positioned at the electrode first time on the first bottom memory pattern, this, electrode was electrically connected to the first bottom memory pattern first time;

Be positioned at the second bottom memory pattern on the dielectric substrate; And

Be positioned on the second bottom memory pattern and the electrode second time that the first time, electrode was spaced apart, this, electrode was electrically connected to the second bottom memory pattern second time.

8, array substrate as claimed in claim 7, wherein two Y shape patterns of openings are formed on the main electrode, and each Y shape patterns of openings relative center line symmetry of pixel region on the horizontal direction of pixel region wherein.

9, array substrate as claimed in claim 8, wherein substantially with two adjacent bars of each Y shape patterns of openings in two parallel linear patterns of openings be formed at for the first time on the electrode.

10, array substrate as claimed in claim 9, wherein substantially with two adjacent bars of each Y shape patterns of openings in another two parallel linear patterns of openings be formed at for the second time on the electrode, and wherein be formed on the electrode for the first time two linear patterns of openings be formed at the electrode second time on the center line symmetry of two linear patterns of openings relative pixel region on the horizontal direction of pixel region.

11, array substrate as claimed in claim 1, wherein main capacitance comprises host liquid crystal electric capacity.

12, array substrate as claimed in claim 11, wherein main capacitance further comprises primary storage electric capacity.

13, array substrate as claimed in claim 1, wherein at least one electric capacity comprises the liquid crystal capacitance of time pixel portion.

14, array substrate as claimed in claim 13, wherein at least one electric capacity further comprises the storage capacitance of time pixel portion.

15, array substrate as claimed in claim 1, wherein pixel region is further limited by the second grid line and second data wire, this second grid line links to each other continuous on dielectric substrate with first grid polar curve, this second data wire is mutually continuous with first data wire on dielectric substrate.

16, a kind of array substrate comprises:

Dielectric substrate with pixel region;

Be positioned at the main grid polar curve on the pixel region;

Be positioned at the main switch on the dielectric substrate, this main switch is electrically connected to the main grid polar curve;

Be placed in the main pixel portion of the core of pixel region, this main pixel portion is electrically connected to main switch;

Be positioned at the inferior gate line on the pixel region;

Be positioned at the inferior switch on the dielectric substrate, this switch is electrically connected to time gate line; And

Be positioned at the inferior pixel portion of the periphery of pixel region.

17, array substrate as claimed in claim 16 further comprises:

Be positioned on the dielectric substrate with the first vertical substantially bottom memory pattern of gate line; And

First connects pattern, and this first connects pattern pixel region is divided into two zones along the horizontal direction of pixel region, and first connects the first bottom memory pattern that pattern is electrically connected to the right side of adjacent unit pixel.

18, a kind of liquid crystal indicator comprises:

Last substrate, substrate has transparent substrate and is positioned at common electrode on this transparent substrates on this;

Following substrate, this time substrate comprises:

Dielectric substrate, this dielectric substrate have the pixel region that is limited by first grid polar curve and the first adjacent data wire, and the first grid polar curve and first data line bit are on dielectric substrate;

Be positioned at the main pixel portion on the core, this main pixel portion comprises main capacitance;

Coupling capacitor, this coupling capacitor has the first end of the switch on the dielectric substrate of being electrically connected to, and

Inferior pixel portion, this time pixel portion comprise at least one electric capacity of the second end that is electrically connected to coupling capacitor, and this time pixel portion is positioned at the periphery of pixel region; And

Be arranged at the liquid crystal layer between substrate and the following substrate.

19, liquid crystal indicator as claimed in claim 18, wherein a plurality of patterns of openings are formed on main pixel portion and time pixel portion, and a plurality of patterns of openings is formed on the common electrode, like this, in the operation of liquid crystal indicator, a plurality of zones are formed in the liquid crystal layer.

20, a kind of liquid crystal indicator comprises:

Last substrate, substrate has transparent substrates and the common electrode that is positioned on the transparent substrates on this;

Following substrate, this time substrate comprises:

Dielectric substrate;

Being positioned at being used on the dielectric substrate transmits the gate line of signal;

Be positioned at the data wire that is used for communicated data signal on the dielectric substrate;

Be electrically connected to the switch of gate line and data wire, this switch is positioned on the dielectric substrate;

Be electrically connected to the main pixel portion of switch, this main pixel portion is positioned on the dielectric substrate;

First coupling capacitor, this first coupling capacitor has the first end that is electrically connected to switch;

Be electrically connected to the pixel portion first time of switch by first coupling capacitor, this, pixel portion was positioned on the dielectric substrate first time;

Second coupling capacitor, this second coupling capacitor has the end that is electrically connected to described switch; And

Be electrically connected to the pixel portion second time of described switch by second coupling capacitor, this, pixel portion was positioned on the dielectric substrate second time; And

21, liquid crystal indicator as claimed in claim 20, wherein main pixel portion comprises:

Host liquid crystal capacitor, this host liquid crystal capacitor have a other end that is electrically connected to the end of switch and receives common voltage; And

Primary storage capacitor, this primary storage capacitor have one and are electrically connected to the end of switch and the other end of reception storage voltage.

22, liquid crystal indicator as claimed in claim 20, wherein pixel portion comprises for the first time:

First liquid crystal capacitor, this first liquid crystal capacitor have one and are electrically connected to the end of first coupling capacitor and the end of another reception common voltage; And

First holding capacitor, this first holding capacitor have one and are electrically connected to the end of first coupling capacitor and the end of another reception storage voltage.

23, liquid crystal indicator as claimed in claim 20, wherein pixel portion comprises for the second time:

Second liquid crystal capacitor, this second liquid crystal capacitor have one and are electrically connected to the end of second coupling capacitor and the end of another reception common voltage; And

Second holding capacitor, this second holding capacitor have one and are electrically connected to the end of second coupling capacitor and the end of another reception storage voltage.