KR20080040391A - Plasma display, and driving device and method thereof - Google Patents

Abstract

A plasma display apparatus and an apparatus and a method for driving the same are provided to reduce the cost of a circuit by using a transistor having a low withstanding voltage in a sustain discharge driver. A scan IC(Integrated Circuit)(411) whose plural first output stages are connected to plural first electrodes, includes first and second input stages and selectively applies the voltage of the second input stage to the first electrodes. First and second transistors are connected to the first and second input stages. First and second capacitors which store first and second voltages, are series-connected between the first transistor and a node, respectively. Third and fourth capacitors which store third and fourth voltages, are series-connected between the second transistor and the node, respectively. A first inductor and a first diode are connected between a contact point of first and second capacitors and a first input stage of the scan IC. A second inductor and a second diode are connected between a contact point of third and fourth capacitors and a second input stage of the scan IC. Switching elements(Ys,Yg) selectively applies fifth and sixth voltages to the node.

Description

Plasma display device, driving device thereof and driving method thereof {PLASMA DISPLAY, AND DRIVING DEVICE AND METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 is a view showing a driving waveform according to a first embodiment of the present invention.

3 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 2.

4 is a diagram illustrating signal timing of the sustain discharge driving circuit 410 for generating the driving waveform of FIG. 2.

5A to 5H are views illustrating the operation of the sustain discharge driving circuit 410 of FIG. 3 according to the signal timing of FIG. 4, respectively.

6A to 6C are diagrams illustrating driving waveforms of the plasma display device according to the second to fourth embodiments, respectively.

The present invention relates to a plasma display device, a drive device thereof and a drive method thereof.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size.

In a plasma display device, one frame is divided into a plurality of subfields having respective weights and driven, and a gray level is displayed by a combination of weights of subfields in which a display operation occurs among the plurality of subfields. Cells to be turned on and cells not to be turned on during the address period of each subfield are selected, and sustain discharge is performed on the cells to be turned on to actually display an image during the sustain period.

In particular, since the high level voltage and the low level voltage are alternately applied to the electrodes performing sustain discharge in the sustain period, the transistor for applying the high level voltage and the low level voltage corresponds to at least the difference between the high level voltage and the low level voltage. Should have a voltage withstand voltage. As a result, the transistor having a high breakdown voltage increases the cost of the sustain discharge driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device, a driving device thereof, and a driving method thereof capable of reducing the unit cost of a sustain discharge driving circuit.

A plasma display device according to an aspect of the present invention includes a plurality of first electrodes, a plurality of first transistors each having a first end connected to the plurality of first electrodes, and a plurality of first ends connected to the plurality of first electrodes. A plurality of second transistors connected to each other, a third transistor having a first end connected to a second end of the plurality of first transistors, and a first end connected to a second end of the plurality of second transistors The fourth transistor is charged with first and second voltages, respectively, and the first and second capacitors connected with the second terminal and the node of the third transistor in series are respectively charged with the third and fourth voltages. Third and fourth capacitors connected in series between the second terminal of the fourth transistor and the node; a first power supply supplying a fifth voltage; and a fifth transistor connected between the node and the fifth voltage; Lower than 6th A sixth transistor connected between a second power supply for supplying a voltage and the node, a first charging path connected between the first power supply and the first capacitor, a connection between the second power supply and the fourth capacitor A second charge path, a first inductor and a first diode connected in series between a contact between the first and second capacitors and a second end of the plurality of first transistors, and the third and fourth And a second inductor and a second diode connected in series between the contacts between the capacitors and the second ends of the plurality of second transistors.

According to another aspect of the present invention, a method of driving a plasma display device including a first electrode and a second electrode for performing a display operation is provided. This driving method comprises the steps of: a) providing first and second capacitors charged with a first voltage and a second voltage, respectively, and connected in series between the plurality of first electrodes and the node, b) a third, respectively; Providing a third and fourth capacitor charged with a voltage and a fourth voltage and connected in series between the plurality of first electrodes and the node, c) supplying a fifth voltage and connecting to the first node Applying a sixth voltage to the first electrode through the first power source and the third and fourth capacitors; d) connecting the energy stored in the first power source and the second capacitor to the first electrode. Injecting the first electrode through a first inductor to increase the voltage of the first electrode, e) injecting energy stored in the first power supply and the second capacitor into the first electrode through the first inductor By the first Increasing the voltage of the pole; f) an eighth voltage to the first electrode through a second power supply, the first and second capacitors, which are connected between the nodes and supply a seventh voltage higher than the fifth voltage; (G) recovering energy stored in the first electrode to the second capacitor and the second power source through a second inductor connected to the first electrode to reduce the voltage of the first electrode; and h) recovering the energy stored in the first electrode to the second capacitor and the first power source through the second inductor to reduce the voltage of the first electrode.

According to still another feature of the present invention, a driving apparatus of a plasma display device including a plurality of first electrodes and a plurality of second electrodes is provided. The driving device has first and second input terminals, and a plurality of first output terminals are connected to the plurality of first electrodes, respectively, and the voltage of the second input terminal during the address period corresponds to one of the plurality of first electrodes. A scan integrated circuit selectively applied to a first electrode, a first transistor connected to a first input terminal of the scan integrated circuit, and a first terminal connected to a second input terminal of the scan integrated circuit. Charging two transistors, respectively, the first and second voltages, and charging the first and second capacitors, respectively, the third and fourth voltages connected in series between the second terminal and the node of the first transistor, Third and fourth capacitors connected in series between the second end of the second transistor and the node, in series between a contact between the first and second capacitors and a first input end of the scan integrated circuit. A second inductor and a second diode connected in series between a connected first inductor and a first diode, a contact between the third and fourth capacitors and a second input terminal of the scan integrated circuit, and And switching means for selectively applying a fifth voltage and a sixth voltage lower than the fifth voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that the voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Including case. In addition, since the threshold voltage of the semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is very low, and thus the threshold voltage is regarded as 0V and approximated.

First, a plasma display device, a driving device thereof, and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating a driving waveform according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as "A electrodes") A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs with each other in the row direction (hereinafter, " X electrodes "(X1 to Xn) and scan electrodes (hereinafter referred to as" Y electrodes ") (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X electrode and the Y electrode perform a display operation for displaying an image in the sustain period. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 110. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes an address period and a sustain period.

The address electrode driver 300 applies a driving voltage to the A electrodes A1-Am according to the driving control signal from the controller 200.

The scan electrode driver 400 applies a driving voltage to the Y electrodes Y1-Yn according to the driving control signal from the controller 200.

The sustain electrode driver 500 applies a driving voltage to the X electrodes X1-Xn according to the drive control signal from the controller 200.

In detail, during the address period of each subfield, the address electrode, the scan electrode, and the sustain electrode driver 300, 400, and 500 select cells to be turned on and cells not to be turned on from the plurality of discharge cells 110. During the sustain period of each subfield, as shown in FIG. 2, the scan electrode driver 400 alternately has a high level voltage (2 Vs) and a low level voltage (-Vs) at the plurality of Y electrodes Y1-Yn. The sustain discharge pulse is applied a number of times corresponding to the weight of the subfield. The sustain electrode driver 500 applies a sustain discharge pulse to the plurality of X electrodes X1-Xn in a phase opposite to that of the sustain discharge pulse applied to the Y electrodes Y1-Yn. In this way, the voltage difference between each Y electrode and each X electrode alternates between the 3 Vs voltage and the -3 Vs voltage, and thus, the sustain discharge is repeatedly generated a predetermined number of times in the cell to be turned on.

Next, the sustain discharge driving circuit for supplying the sustain discharge pulse of FIG. 2 will be described in detail with reference to FIGS. 3, 4 and 5A to 5H.

3 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 2. In FIG. 3, only the sustain discharge driving circuit 410 connected to the plurality of Y electrodes Y1 to Yn is illustrated for convenience of description, and the sustain discharge driving circuit 410 is formed in the scan electrode driver 400 of FIG. 1. Can be. The sustain discharge driving circuit 510 connected to the plurality of X electrodes X1 ′ Xn may also have the same structure as the sustain discharge driving circuit 410 of FIG. 3, and is different from the sustain discharge driving circuit 410 of FIG. 3. It may have a structure. In FIG. 3, only one X electrode and one Y electrode are illustrated in the sustain discharge driving circuit 410 for convenience of description, and the capacitive components formed by the X electrode and the Y electrode are illustrated as the panel capacitor Cp. .

As shown in FIG. 3, the sustain discharge driving circuit 410 includes transistors Ys, Yg, YH, YL, Sch, Scl, capacitors Cs1, Cs2, Cs3, Cs4, inductors Lr, Lf, and diodes ( D1, D2, D3, D4) and a scan integrated circuit (hereinafter referred to as " scanning IC ") 411. In FIG. 3, the transistors Ys, Yg, Y1, Y2, YH, YL, Sch, and Scl are shown as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors. In the YH, YL, Sch, and Scl), a body diode may be formed from the source to the drain direction. And other transistors having similar functions instead of NMOS transistors may be used as these transistors (Ys, Yg, YH, YL, Sch, Scl). In FIG. 3, the transistors Ys, Yg, YH, YL, Sch, and Scl are shown as one transistor, but the transistors Ys, Yg, YH, YL, Sch, and Scl are each connected in parallel. It may be formed of a transistor.

The scanning IC 411 has a first input terminal and a second input terminal, and the output terminal is connected to the Y electrode of the panel capacitor Cp. The scan IC 411 selectively applies the voltage at the first input terminal and the voltage at the second input terminal to the corresponding Y electrodes in order to select a cell to be turned on in the address period. Although one Y electrode is connected to the scan IC 411 in FIG. 3, the scan IC 411 may have a plurality of output terminals. That is, the plurality of Y electrodes Y1 to Yk may be connected to the plurality of output terminals of the scan IC 411. In this case, when the number of output terminals of the scanning IC 411 is smaller than the number of the Y electrodes Y1 to Yn, the plurality of scanning ICs 411 may be used. The scan IC 431 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode of the panel capacitor Cp. The source of the transistor YH is connected to the drain of the transistor Sch, and the drain of the transistor YL is connected to the source of the transistor Scl. The two capacitors Cs1 and Cs2 are connected in series between the drain of the transistor YH and the node N, and the two capacitors Cs3 and Cs4 are connected between the source of the transistor YL and the node N in series. Is connected. An inductor Lr and a diode D3 are connected in series between the contacts of the capacitors Cs1 and Cs2 and the first input terminal of the scan IC 411, and the contacts of the capacitors Cs3 and Cs4 and the scan IC 411. An inductor Lf and a diode D4 are connected in series between the second input terminals of the. That is, the anode of the diode D3 is connected to the inductor Lr, and the cathode of the diode D3 is connected to the drain of the transistor Sch. The anode of diode D4 is connected to the source of transistor Scl and the cathode of diode D4 is connected to inductor Lf. At this time, the diode D3 is for setting the rising path for blocking the current path formed by the body diode of the transistor and increasing the voltage of the Y electrode, and the diode D4 is formed due to the body diode of the transistor Scl. It is to set the falling path to cut off the current path and reduce the voltage of the Y electrode. Unlike in FIG. 3, the diode D3 may be located between the contact between the capacitors Cs1 and Cs2 and the inductor Lr. Similarly, the diode D4 may be located between the contact between the capacitors Cs3 and Cs4 and the inductor Lf.

The drain of the transistor Ys is connected to a power supply Vs for supplying a voltage Vs corresponding to two-thirds of the high level voltage (2Vs) and the low level voltage (-Vs) of the sustain discharge pulse, and the transistor Ys. The source of is connected to the node (N). The source of the transistor Yg is connected to a ground terminal 0 that supplies a 0 V voltage corresponding to 1/3 of the high level voltage (2 Vs) and the low level voltage (-Vs) of the sustain discharge pulse. ) Is connected to the node (N). At this time, the two transistors Ys and Yg operate as switching means for selectively applying a voltage of Vs or 0V to the node N.

An anode of the diode D1 is connected to the power supply Vs, and a cathode of the diode D1 is connected to the capacitor Cs1. In addition, the cathode of the diode D2 is connected to the ground terminal 0, and the anode of the diode D2 is connected to the capacitor Cs4. In this case, the diode D1 turns on the transistor Yg to form a charging path for charging the capacitors Cs1 and Cs2 to a voltage of Vs / 2, respectively, and the capacitors Cs1 and Cs2 are each Vs /. It is charged to 2 voltages. Similarly, diode D2 turns on transistor Ys to form a charge path for charging capacitors Cs3 and Cs4 to a voltage of Vs / 2, respectively, whereby capacitors Cs3 and Cs4 are each Vs / 2. Charged to voltage. Instead of diodes D1 and D2, other devices (e.g. transistors) may be used that can form a charge path.

Next, the operation of the sustain discharge driving circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 4 and 5A to 5H.

4 is a diagram illustrating signal timing of the sustain discharge driver circuit 410 for generating the driving waveform of FIG. 2, and FIGS. 5A to 5H are diagrams illustrating the sustain discharge driver circuit 410 of FIG. 3 according to the signal timing of FIG. 4, respectively. Is a view showing the operation. It is assumed that the transistors Yg, YL, and Scl are turned on before the mode 1 (M1) is started so that the -Vs voltage is applied to the Y electrode.

4 and 5A, in the mode 1 M1, the transistor Sch is turned on and the transistors YL, Scl are turned off, so that the ground terminal 0, the transistor Yg, the capacitor Cs2, and the inductor ( Resonance occurs in the path of the Y electrode of Lr, diode D3, transistor Sch and panel capacitor Cp (1). Then, the energy charged in the capacitor Cs2 is injected into the Y electrode through the inductor Lf so that the voltage of the Y electrode increases from the -Vs voltage to the 2Vs voltage. At this time, since the drain voltage of the transistor YH becomes the Vs voltage, when the voltage of the Y electrode becomes equal to or higher than the Vs voltage, the capacitor Cs1 and Cs2 and the ground terminal 0 are recovered through the body diodes of the transistors Sch and YH. The voltage at the Y electrode is clamped to the voltage Vs (①). At this time, since a 0V voltage is applied to the source of the transistor Ys, the Vs voltage is applied between the drain and the source of the transistor Ys. That is, the transistor Ys that is turned off may use a transistor having a voltage resistance of Vs.

Subsequently, in the mode 2 M2, the transistors YH and Yg are turned on and the transistors Yg are turned off, so that the power supply Vs, the transistors YH, Sch and the panel capacitor Cp are shown in FIG. 5B. Vs voltage is applied to the Y electrode through the path of the Y electrode (). In addition, the voltages Vs / 2 are charged to the capacitors Cs1 and Cs2 through the paths of the power supply Vs, the diode D1, the capacitors Cs1 and Cs2, the transistor Yg, and the ground terminal 0 (② '). ). At this time, a voltage of 2 Vs is applied between the turned-off transistor Scl and the source of the turned-off transistor YL. That is, each transistor Scl and YL may use a transistor having a voltage resistance of Vs.

In mode 3 M3, the transistor Ys is turned on and the transistor Yg is turned off, so that the power supply Vs, the transistor Ys, the capacitor Cs2, the inductor Lr, Resonance occurs in the path of the Y electrode of the diode D3, the transistor Sch and the panel capacitor Cp (3). Then, the energy charged in the capacitor Cs2 is injected into the Y electrode through the inductor Lr so that the voltage of the Y electrode increases from the Vs voltage to the 2Vs voltage. At this time, since the voltage Vs is applied to the drain of the transistor Yg, the voltage Vs is applied between the drain and the source of the transistor Yg. That is, the transistor Yg turned off may use a transistor having a Vs voltage.

Next, the transistor YH is turned on in the mode 4 M4 so that the power supply Vs, the capacitors Cs2 and Cs1, the transistors YH and Sch and the Y of the panel capacitor Cp are turned on as shown in FIG. 5D. A 2Vs voltage is applied to the Y electrode through the path of the electrode (④).

In mode 5 M5, the transistors Ys and Scl are turned on and the transistors YH and Sch are turned off, so that the Y electrode, the transistor Scl and the diode of the panel capacitor Cp as shown in FIG. 5E. Resonance occurs in the path of D4), the inductor Lr, the capacitor Cs3, the transistor Ys, and the power supply Vs. Then, as the energy stored in the panel capacitor Cp is recovered to the power supply Vs through the inductor Lf, the voltage of the Y electrode decreases from the voltage of 2Vs to the voltage of -Vs. At this time, since the source voltage of the transistor YL becomes 0V, when the Y electrode becomes 0V or less, the power supply Vs and the capacitor are supplied through the power supply Vs, the capacitors Cs3 and Cs4, and the body diode of the transistor YL. As the energy charged in (Cs3, Cs4) is injected into the Y electrode, the voltage of the Y electrode is clamped to the 0V voltage (⑤). At this time, a voltage of 2 Vs is applied between the source of the turned off transistor Sch and the drain of the turned off transistor YH. That is, each transistor Sch, YH may use a transistor having a voltage resistance of Vs.

In mode 6 (M6), transistors YL and Yg are turned on and transistors Ys are turned off, so that the Y electrode, transistors Scl and YL, diode ( A voltage of 0V is applied to the Y electrode through the path of D2) and ground terminal 0 (6). At this time, the voltages Vs / 2 are charged to the capacitors Cs3 and Cs4 through the path V of the power source Vs, the transistor Ys, the capacitors Cs3 and Cs4, the diode D2 and the ground terminal 0, respectively (6). ').

In mode 7 M7, transistor Yg is turned on and transistor YL is turned off, as shown in FIG. 5G, the Y electrode, panel transistor Scl, diode D4, and inductor of panel capacitor Cp. Resonance occurs in the paths of Lf, capacitor Cs3, transistor Yg, and ground terminal 0 (7). Then, as the energy stored in the panel capacitor Cp is recovered to the ground terminal 0 through the inductor Lf, the voltage of the Y electrode decreases from the voltage of 0V to the voltage of -Vs.

Finally, in the mode 8 (M8), the transistor YL is turned on, and as shown in FIG. 5H, the Y electrode of the panel capacitor Cp, the transistors Scl and YL, the capacitors Cs4 and Cs3 and the transistor ( The voltage -Vs is applied to the Y electrode through the path of Yg) and the ground terminal 0 (8).

As described above, according to the exemplary embodiment of the present invention, the transistors Sch, Scl, Ys, Yg, YH, and YL are voltages corresponding to the difference between the high level voltage (2Vs) and the low level voltage (-Vs) of the sustain discharge pulse. That is, a transistor having a withstand voltage of one third of Vs can be used, thereby reducing the circuit cost. In the sustain period, the mode 1 to mode 8 (M1 to M8) may be repeated as many times as the weight of the corresponding subfield so that 2Vs voltage and -Vs voltage may be alternately applied to the Y electrode.

In the above, generating the driving waveform according to the first embodiment of the present invention has been described with reference to FIGS. 5A to 5H. In the driving waveform shown in FIG. 2, the voltage difference between each Y electrode and each X electrode alternately has a 3Vs voltage and a -3Vs voltage. At this time, if the voltage magnitude of 3Vs is equal to the voltage magnitude of Vs', a driving waveform as shown in FIGS. 6A to 6C may be applied. 6A to 6C are diagrams illustrating driving waveforms of the plasma display device according to the second to fourth embodiments, respectively.

As shown in Fig. 6A, during the sustain period, the plurality of Y electrodes Y1 to Yn and the plurality of X electrodes X1 to Xn alternately have a high level voltage Vs' and a low level voltage 0V. The sustain discharge pulse may be applied in reverse phase. 6B, the high level voltage Vs '/ 2 and the low level voltage Vs' / 2 are alternated between the plurality of Y electrodes Y1 to Yn and the plurality of X electrodes X1 to Xn. The branch may also apply the sustain discharge pulse in the opposite phase. That is, the scan electrode driver 400 sustains discharge having a plurality of Y electrodes Y1 to Yn alternately having a high level voltage Vs' or Vs' / 2 and a low level voltage 0V or -Vs' / 2. The pulses are applied as many times as the weights of the corresponding subfields, and the sustain electrode driver 500 supplies sustain discharge pulses to the plurality of X electrodes X1 to Xn and the sustain discharge pulses applied to the Y electrodes Y1 to Yn. Apply in reverse phase. Even in this manner, the voltage difference between each Y electrode and each X electrode alternates between the Vs 'voltage and the -Vs' voltage, whereby the sustain discharge is repeatedly generated a predetermined number of times in the discharge cell to be turned on.

In addition, unlike the second and third embodiments of the present invention, the sustain discharge pulse may be applied to only one of the X electrode and the Y electrode. That is, as shown in FIG. 6C, in the sustain period, a sustain discharge pulse having a voltage of Vs 'and a voltage of -Vs' may be applied to the Y electrode while the voltage of 0V is applied to the X electrode. Even in this manner, the voltage difference between each Y electrode and each X electrode alternates between the Vs 'voltage and the -Vs' voltage, whereby the sustain discharge may be repeatedly generated a predetermined number of times in the discharge cell to be turned on.

In addition, the driving waveforms according to the second to fourth embodiments of the present invention may also be generated through the sustain discharge driving circuit 410 of FIG. 3. Specifically, in the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to a power supply 2Vs' / 3 which supplies a voltage of 2Vs' / 3, and the source of the transistor Y1 is Vs' / 3. When connected to a power supply Vs '/ 3 that supplies a voltage, a sustain discharge pulse having an alternating voltage of Vs' and 0V can be applied to the Y electrode through the path shown in FIGS. 5A to 5H. In the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to the power supply Vs' / 6 which supplies the voltage Vs' / 6, and the source of the transistor Y3 is connected to the voltage -Vs' / 6. Is connected to a power supply (-Vs' / 6), a sustain discharge pulse having alternating voltages Vs' / 2 and -Vs' / 2 is applied to the Y electrode through the path shown in FIGS. 5A to 5H. can do. In the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to the power supply Vs' / 3 which supplies the voltage Vs' / 3, and the source of the transistor Y3 is -Vs' / 3 voltage. When connected to the power supply (-Vs' / 3), the sustain discharge pulse having the voltage Vs' and -Vs' alternately applied to the Y electrode can be applied to the Y electrode through the path shown in FIGS. 5A to 5H. At this time, a 0V voltage is applied to the X electrode.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the transistor having a low breakdown voltage can be used in the sustain discharge driving circuit, the circuit cost can be reduced.

Claims (20)

A plurality of first electrodes, A plurality of first transistors each having a first end connected to the plurality of first electrodes, A plurality of second transistors each having a first end connected to the plurality of first electrodes, A third transistor having a first end connected to a second end of the plurality of first transistors, A fourth transistor having a first end connected to a second end of the plurality of second transistors, First and second capacitors charged with first and second voltages, respectively, connected in series between the second terminal and the node of the third transistor; Third and fourth capacitors charged with third and fourth voltages, respectively, and connected in series between the second terminal of the fourth transistor and the node; A fifth transistor connected between the first power supply supplying a fifth voltage and the node; A sixth transistor connected between the second power supply supplying a sixth voltage lower than the fifth voltage and the node; A first charging path connected between the first power supply and the first capacitor, A second charging path connected between the second power supply and the fourth capacitor, A first inductor and a first diode connected in series between a contact between the first and second capacitors and a second end of the plurality of first transistors, and A second inductor and a second diode connected in series between a contact between the third and fourth capacitors and a second end of the plurality of second transistors Plasma display device comprising a. The method of claim 1, The first charging path may include a third diode having an anode connected to the first power supply and a cathode connected to the first capacitor. The second charging path may include a fourth diode having a cathode connected to the second power supply and an anode connected to the fourth capacitor. The method of claim 2, The second, fourth and sixth transistors are turned on during a first period, the first and sixth transistors are turned on during a second period, and the first and third transistors are turned on during a third period. Is set to a turn on state, the first and fifth transistors are turned on for a fourth period, and the first, third and fifth transistors are turned on for a fifth period, and for a sixth period A controller configured to set the second and fifth transistors to a turn on state, to set the second and fourth transistors to a turn on state for a seventh period, and to set the second and sixth transistors to a turn on state for an eighth period. Plasma display device further comprising. The method of claim 3, The controller is configured to set the sixth transistor to the turned on state for the third period, to set the fifth transistor to the turned on state for the fourth period, When the sixth transistor is turned on, the first and second capacitors are charged with the first and second voltages, respectively, and when the fifth transistor is turned on, the second and third capacitors are respectively the third and third capacitors. A plasma display device charged at 4 voltages. The method of claim 3, The plurality of first, second transistors, the third and fourth transistors each include a body diode. The method according to any one of claims 1 to 5, And the fifth voltage is a positive voltage and the sixth voltage is a ground voltage. The method according to any one of claims 1 to 5, And the fifth and sixth voltages are positive voltages. The method according to any one of claims 1 to 5, The fifth voltage is a positive voltage, and the sixth voltage is a negative voltage. A method of driving a plasma display device including a first electrode and a second electrode performing a display operation, the method comprising: a) providing first and second capacitors charged with a first voltage and a second voltage, respectively, and connected in series between said plurality of first electrodes and nodes, b) providing third and fourth capacitors charged with a third voltage and a fourth voltage, respectively, connected in series between the plurality of first electrodes and the node; c) applying a sixth voltage to the first electrode through a first power supply connected to the first node and supplying a fifth voltage and the third and fourth capacitors, d) increasing the voltage of the first electrode by injecting energy stored in the first power supply and the second capacitor into the first electrode through a first inductor connected to the first electrode; e) injecting energy stored in the first power supply and the second capacitor into the first electrode through the first inductor to increase the voltage of the first electrode, f) applying an eighth voltage to the first electrode through a second power supply connected to the node and supplying a seventh voltage higher than the fifth voltage, the first and second capacitors; g) recovering the energy stored in the first electrode to the second capacitor and the second power supply through a second inductor connected to the first electrode to reduce the voltage of the first electrode; and h) recovering the energy stored in the first electrode to the second capacitor and the first power supply through the second inductor to reduce the voltage of the first electrode; Method of driving a plasma display device comprising a. The method of claim 9, The plasma display device, At least one first transistor connected in series between the first capacitor and the first electrode, The d) may include applying a seventh voltage to the first electrode through the first power source, the first and second capacitors, and the body diode of the at least one first transistor. Driving method. The method of claim 9, The plasma display device, At least one second transistor connected in series between the fourth capacitor and the first electrode, The step g) includes applying the fifth voltage to the first electrode through the body diode of the at least one second transistor, the third and fourth capacitors, and the second power source. Method of driving. The method according to any one of claims 9 to 11, Applying the seventh voltage to the first electrode between steps d) and e), and And applying the fifth voltage to the first electrode between the steps g) and h). The method of claim 12, The applying of the seventh voltage to the first electrode may include charging the first and second capacitors to the first and second voltages through the second power supply, respectively. The applying of the fifth voltage to the first electrode may include charging the third and fourth capacitors to the third and fourth voltages through the second power supply, respectively. . The method according to any one of claims 9 to 11, Applying the sixth voltage to the first electrode includes applying the eighth voltage to the second electrode, The applying of the eighth voltage to the first electrode includes applying the sixth voltage to the second electrode. In the driving device of the plasma display device including a plurality of first electrodes and a plurality of second electrodes, And a plurality of first output terminals are respectively connected to the plurality of first electrodes, and the voltage of the second input terminal is connected to a corresponding first electrode of the plurality of first electrodes during an address period. Scanning integrated circuits that selectively apply; A first transistor connected to a first input terminal of the scan integrated circuit, A second transistor connected to a second input terminal of the scan integrated circuit, First and second capacitors charged with first and second voltages, respectively, and connected in series between the first transistor and the node; Third and fourth capacitors charged with third and fourth voltages, respectively, and connected in series between the second transistor and the node; A first inductor and a first diode connected in series between a contact point of the first and second capacitors and a first input terminal of the scan integrated circuit, A second inductor and a second diode connected in series between the contacts of the third and fourth capacitors and the second input terminal of the scan integrated circuit, and Switching means for selectively applying a fifth voltage and a sixth voltage lower than the fifth voltage to the node Driving device comprising a. The method of claim 15, In a state in which the second transistor is turned on while the sixth voltage is applied to the node and a seventh voltage is applied to the first electrode through the third and fourth capacitors, The voltage of the first electrode is increased through the second capacitor, the first inductor, and the first diode while the sixth voltage is applied to the node, The voltage of the first electrode is further increased through the second capacitor, the first inductor, and the first diode while the fifth voltage is applied to the node, And a fifth voltage applied to the first electrode through the first and second capacitors while the fifth voltage is applied to the node. The method of claim 16, And a fifth voltage is applied through the body diode of the third transistor while the voltage of the first electrode is increased while the sixth voltage is applied to the node. The method of claim 15, In a state in which the first transistor is turned on while the fifth voltage is applied to the node and a seventh voltage is applied to the first electrode through the first and second capacitors, Reducing the voltage of the first electrode through the third capacitor, the second inductor, and the second diode while applying the fifth voltage to the node, After further reducing the voltage of the first electrode through the third capacitor, the second inductor and the second diode while the sixth voltage is applied to the node, And turning on the second transistor while applying a sixth voltage to the node to apply an eighth voltage to the first electrode through the third and fourth capacitors. The method of claim 18, And a sixth voltage is applied to the first electrode through the body diode of the second transistor while the voltage of the first electrode is decreased while the fifth voltage is applied to the node. The method according to any one of claims 16 to 19, The eighth voltage is applied to the second electrode while the seventh voltage is applied to the first electrode, and the seventh voltage is applied to the second electrode while the eighth voltage is applied to the first electrode. Driven device.

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