KR20080039717A - Lcd and drive method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to offer required data voltages to respective pixels by controlling the supplement of scan pulses based on signals inputted from a system. An LCD(Liquid Crystal Display) device includes an LCD panel(110), a timing controller(210), and a gate driver(220). The LCD panel is formed by crossing data and gate lines. The timing controller determines whether signals inputted from a system are distorted and supplies or masks a gate output enable signal according to the determined result. The gate driver sequentially supplies scan pulses to the gate lines in response to the gate output enable signal from the timing controller or stops the supplement of the scan pulses in response to the masked gate output enable signal from the timing controller.

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is a characteristic diagram of normal signals supplied from a system to a liquid crystal display.

4 is a characteristic diagram of abnormal signals supplied from a system to a liquid crystal display.

5 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 6 is a configuration diagram of the timing controller shown in FIG. 5. FIG.

7A and 7B are signal characteristic diagrams of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100 and 200: liquid crystal display 110: liquid crystal display panel

120: data driver 130, 220: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generator 190, 210: timing controller

211: flip-flop 212: phase frequency detector

213: masking discriminating unit 213-1: non-combination gate

214: signal generator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of controlling whether or not a scan pulse is supplied according to a state of signals input from a system.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on, thereby maintaining a constant voltage of the liquid crystal cell Clc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film for driving the liquid crystal cell Clc at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. A liquid crystal display panel 110 having a TFT (TFT: Thin Film Transistor) formed thereon, a data driver 120 for supplying data to the data lines DL1 to DLm of the liquid crystal display panel 110, and a liquid crystal display panel ( A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the 110, a gamma reference voltage generator 140 for generating a gamma reference voltage, and supplying the gamma reference voltage to the data driver 120; The liquid crystal display may generate a backlight assembly 150 for irradiating light to the liquid crystal display panel 110, an inverter 160 for applying an alternating voltage and current to the backlight assembly 150, and a common voltage Vcom. Common voltage generation for supplying to the common electrode of the liquid crystal cell Clc of the panel 110 The gate 170 and the gate driving voltage generator 180 for generating and supplying the gate high voltage VGH and the gate low voltage VGL to the gate driver 130, the data driver 120 and the gate driver A timing controller 190 for controlling 130.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. After sampling and latching the RGB, the liquid crystal cell Clc of the liquid crystal display panel 110 is converted into an analog data voltage capable of expressing gray scale based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. In this case, the gate driver 130 determines the high level voltage and the low level voltage of the scan pulse based on the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When the burst dimming signal determined according to the square wave signal inside is generated, the driving IC (not shown) for controlling the generation of the AC voltage and the current in the inverter 160 generates the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current supplied to the

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from an image processing scaler (not shown) included in a system such as a television receiver or a computer monitor, to the data driver 120, and also provides a clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated using the horizontal / vertical synchronizing signals H and V and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In addition, the timing controller 190 is a gate output used for supply timing control of the scan pulse in synchronization with the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data output enable signal DE inputted from the system. The enable signal GOE is supplied to the gate driver 130. The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data output enable signal DE are input to the timing controller 190 in synchronization with each other at regular intervals as shown in FIG. 3. The vertical sync signal Vsync, the horizontal sync signal Hsync, and the data output enable signal DE should be normally input in synchronization with each other. However, the timing controller 190 may enable the gate output to precisely adjust the supply timing of the scan pulse. The signal GOE is supplied to the gate driver 130.

However, if any one of the vertical sync signal Vsync, the horizontal sync signal Hsync, and the data output enable signal DE input from the system is distorted, the vertical sync signal input as shown in FIG. Vsync), horizontal sync signal Hsync, and data output enable signal DE are irregularly cycled, which causes the timing controller 190 to incorrectly output the gate output enable signal GOE to the gate driver 130. Supply. In this case, the gate driver 130 may not accurately adjust the timing of supplying the scan pulse due to the incorrect gate output enable signal GOE, and thus, the desired data voltage may not be supplied to each pixel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of controlling whether scan pulses are supplied according to the state of signals input from a system. have.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a driving method thereof capable of supplying a desired data voltage to each pixel by controlling whether scan pulses are supplied in accordance with states of signals input from a system.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel formed by crossing a plurality of data lines and a plurality of gate lines; A timing controller determining whether the signals inputted from the system are distorted and supplying the gate output enable signal or masking the gate output enable signal according to the determination result; And a gate sequentially supplying scan pulses to the gate lines in response to a normal gate output enable signal from the timing controller, or stopping supply of scan pulses in response to a masked gate output enable signal from the timing controller. It includes a drive unit.

The timing controller may include: a flip-flop configured to output a data output enable signal input from the system in a specific section of the vertical synchronization signal input from the system; A phase frequency for detecting a period of a clock signal, a horizontal synchronization signal and a vertical synchronization signal input from the system, and detecting a period of a data output enable signal input from the flip-flop to output a normal signal or an error signal according to a detection result. Detection unit; A masking discriminating unit which determines masking of the gate output enable signal using the signals output from the phase frequency detecting unit; And a signal generator for normally outputting the gate output enable signal or masking the gate output enable signal according to the output signal of the masking discriminator.

The flip-flop may output the input data output enable signal to the phase frequency detector in a rising interval of the input vertical synchronization signal.

The phase frequency detector detects the period of the clock signal by counting the period of the input clock signal, temporarily stores the detected clock signal period, and counts the period of the input horizontal synchronization signal to count the period of the horizontal synchronization signal. Detects a period and temporarily stores the detected horizontal sync signal period, detects a period of the input vertical sync signal, temporarily stores the detected vertical sync signal period, and a period of a data output enable signal input from the flip-flop And temporarily store the detected data output enable signal period.

The phase frequency detector may compare the detected clock signal period with a predetermined reference clock period and determine masking of the first normal signal “0” when the detected clock signal period matches the predetermined reference clock period. And outputs a first error signal " 1 " to the masking determination unit if the detected clock signal period does not match the predetermined reference clock period.

The phase frequency detection unit compares the detected horizontal synchronization signal period with a predetermined reference horizontal period and compares the second normal signal "0" when the detected horizontal synchronization signal period matches the predetermined reference horizontal period. And outputs a second error signal " 1 " to the masking determination unit if the detected horizontal synchronization signal period does not match the predetermined reference horizontal period as a result of the comparison.

The phase frequency detection unit compares the detected vertical synchronization signal period with a predetermined reference vertical period, and when the detected vertical synchronization signal period matches the predetermined reference vertical period, masking a third normal signal "0". And outputs a third error signal " 1 " to the masking determination unit if the detected vertical synchronization signal period does not match the predetermined reference vertical period.

The phase frequency detection unit compares the detected data output enable signal period with a predetermined data output period, and if the detected data output enable signal period matches the predetermined data output period, the fourth normal signal " 0 " Is output to the masking discrimination unit, and a fourth error signal "1" is output to the masking discrimination unit when the detected data output enable signal period and the predetermined reference vertical period are inconsistent.

The masking discriminator may include a logic sum gate having four input terminals connected to the output terminals of the phase frequency detector and one output terminal connected to the signal generator.

When the first to fourth normal signals "0" are input from the phase frequency detector, the logic sum gate outputs an output control signal "0" to the signal generator by performing a logical sum of the input first to fourth normal signals. It features.

The signal generator is configured to normally supply the gate output enable signal to the gate driver in response to the output control signal "0".

The logic sum gate outputs a masking signal " 1 " to the signal generator by summing the input signals when the error signal " 1 " of the first to fourth error signals is input from the phase frequency detector. do.

The signal generator may mask the gate output enable signal in response to the masking signal "1".

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device having a liquid crystal display panel having a plurality of gate lines, the method comprising: determining whether signals inputted from a system are distorted; Generating a normal gate output enable signal or a masked gate output enable signal according to the determination result; And sequentially supplying scan pulses in response to the normal gate output enable signal or stopping supply of scan pulses in response to the masked gate output enable signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, the liquid crystal display 200 of the present invention shown in FIG. 5 also has the same gamma reference voltage generator 140, the backlight assembly 150, and the inverter as in the liquid crystal display 100 shown in FIG. 2. 160, the common voltage generator 170 and the gate driving voltage generator 180, but these components are not shown in Figure 5 for convenience of description.

Referring to FIG. 5, in the liquid crystal display device 200 of the present invention, the data lines DL1 through DLm and the gate lines GL1 through GLn intersect with each other to drive the liquid crystal cell Clc at an intersection thereof. The liquid crystal display panel 110 includes a thin film transistor TFT and a data driver 120 for supplying data to the data lines DL1 to DLm of the liquid crystal display panel 110.

The liquid crystal display 200 of the present invention determines whether the signals inputted from the system are distorted, and normally supplies the gate output enable signal GOE or masks the gate output enable signal GOE according to the determination result. In response to the normal gate output enable signal GOE from the timing controller 210 and the gate controller GL1 to GLn in sequence, or from the timing controller 210. The gate driver 220 cuts off the supply of the scan pulse in response to the masked gate output enable signal GOE.

The timing controller 210 supplies the digital video data RGB supplied from the system to the data driver 120, and controls the data driving by using the horizontal / vertical synchronization signals Hsync and Vsync according to the clock signal DCLK. The signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 120 and the gate driver 220, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In addition, the timing controller 210 may output the gate output enable signal GOE in response to the clock signal DCLK, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data output enable signal DE input from the system. ) Is supplied to the gate driver 220. If distortion occurs in any one of the signals DCLK, Hsync, Vsync, and DE input from the system, the gate output enable signal GOE is masked.

The gate driver 220 sequentially supplies scan pulses to the gate lines GL1 to GLn in response to the gate output enable signal GOE from the timing controller 210. Here, the gate driver 220 generates a scan pulse in the low level section of the gate output enable signal GOE normally supplied from the timing controller 210. In particular, the gate driver 220 does not generate a scan pulse in a section in which the gate output enable signal GOE from the timing controller 210 is masked.

FIG. 6 is a configuration diagram of the timing controller shown in FIG. 5.

Referring to FIG. 6, the timing controller 210 flip-flops 211 that outputs a data output enable signal DE input from the system in a specific section of the vertical synchronization signal Vsync input from the system. And the period of the clock signal DCLK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync input from the system, and the period of the data output enable signal DE input from the flip-flop 211. A gate frequency output using a phase frequency detector (PFD) 212 that detects a normal signal " 0 " or an error signal " 1 " according to a detection result, and signals output from the phase frequency detector 212. According to the masking determination unit 213 for determining the masking of the enable signal GOE and the output signal of the masking determination unit 213, the gate output enable signal GOE is normally output or the gate output enable signal. Mas (GOE) And a signal generating unit 214 to.

The flip-flop 211 outputs a clock terminal CLK for receiving the vertical synchronization signal Vsync, an input terminal D for receiving the data output enable signal DE, and a data output enable signal DE. Has an output stage (Q). The flip-flop 211 receives a vertical synchronization signal Vsync from the system to the clock terminal CLK and simultaneously inputs a data output enable signal DE from the system to the input terminal D. The data output enable signal DE input to the input terminal D in the rising period of the input vertical synchronization signal Vsync is output to the phase frequency detector 212 through the output terminal D. That is, the flip-flop 211 checks whether the frequency of the data output enable signal DE is constant by increasing the period of the data output enable signal DE input from the system to the period of the vertical synchronization signal Vsync input from the system. Function.

The phase frequency detector 212 detects the period of the clock signal DCLK by counting the period of the clock signal DCLK input from the system, and temporarily stores the detected clock signal period, and at the same time, the horizontal synchronous signal input from the system. The period of Hsync is counted to detect the period of the horizontal sync signal Hsync, and the detected horizontal sync signal period is temporarily stored. At the same time, the phase frequency detector 212 detects the period of the vertical synchronization signal Vsync input from the system and temporarily stores the detected period of the vertical synchronization signal, and at the same time enables the data output enabled from the flip-flop 211. Detects the period of the signal DE and temporarily stores the detected data output enable signal period.

The phase frequency detector 212 determines whether the clock signal DCLK is distorted by comparing the detected clock signal period with a predetermined reference clock period. If the detected clock signal period matches the predetermined reference clock period, the phase frequency detector 212 determines that the clock signal DCLK is normal and outputs the first normal signal "0" to the masking discriminator 213. do. If the detected clock signal period is inconsistent with the predetermined reference clock period, the phase frequency detector 212 determines that a distortion has occurred in the clock signal DCLK and masks the first error signal “1”. )

The phase frequency detector 212 determines whether the horizontal sync signal Hsync is distorted by comparing the detected horizontal sync signal period with a predetermined reference horizontal period. If the detected horizontal synchronization signal period and the predetermined reference horizontal period coincide, the phase frequency detector 212 determines that the horizontal synchronization signal Hsync is normal and masks the second normal signal "0". Will output If the detected horizontal synchronization signal period is inconsistent with the predetermined reference horizontal period, the phase frequency detector 212 determines that distortion has occurred in the horizontal synchronization signal Hsync and masks the second error signal "1". Output to (213).

The phase frequency detector 212 determines whether the vertical synchronization signal Vsync is distorted by comparing the detected vertical synchronization signal period with a predetermined reference vertical period. If the detected vertical synchronization signal period and the predetermined reference vertical period coincide, the phase frequency detector 212 determines that the vertical synchronization signal Vsync is normal and masks the third normal signal "0". Will output If the detected vertical synchronization signal period and the predetermined reference vertical period do not match, the phase frequency detector 212 determines that distortion occurs in the vertical synchronization signal Vsync and masks the third error signal "1". Output to (213).

The phase frequency detector 212 determines whether the data output enable signal DE is distorted by comparing the detected data output enable signal period with a predetermined data output period. If the detected data output enable signal period coincides with the predetermined data output period, the phase frequency detection unit 212 determines that the data output enable signal DE is normal and masks the fourth normal signal " 0 ". Output to the unit 213. As a result of the comparison, if the detected data output enable signal period and the predetermined reference vertical period do not match, the phase frequency detector 212 determines that the distortion occurs in the data output enable signal DE, and thus the fourth error signal "1". Is output to the masking determination unit 213.

Here, the phase frequency detector 212 simultaneously outputs at least one normal signal and / or at least one error signal among the first to fourth error signals among the first to fourth normal signals to the masking determination unit 213. It is done.

The masking determination unit 213 has an OR gate 213-1 having four input terminals connected to the output terminals of the phase frequency detector 212 and one output terminal connected to the signal generator 214. )to be.

The logic sum gate 213-1 outputs an output control signal “0” to the signal generator 214 when all four signals input from the phase frequency detector 212 are normal signals “0”. If at least one of the four signals input from 212 is an error signal "1", the masking signal "1" is output to the signal generator 214. Here, the output control signal is a signal indicating the normal output of the gate output enable signal GOE, and the masking signal is a signal indicating the masking of the gate output enable signal GOE. When the gate output enable signal GOE is masked, the gate output enable signal GOE is maintained at a high level, and in this masting state, the supply of scan pulses from the gate driver 220 is cut off.

The signal generator 214 may output a gate output enable signal GOE in response to a clock signal DCLK, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data output enable signal DE input from the system. Is supplied to the gate driver 220. When the signal generation unit 214 receives the output control signal "0" from the masking determination unit 213, as shown in FIG. 7A, the gate output enable signal GOE in which the high level and the low level are repeatedly repeated. Is output to the gate driver 220. Here, the gate driver 220 generates a scan pulse in the low level section of the gate output enable signal GOE.

On the contrary, when the masking signal "1" is input from the masking determination unit 213, the signal generator 214 is a gate output such that the high level is maintained while the masking signal "1" is input as shown in FIG. 7B. Mask the GOE. When the output control signal "0" is input again after the masking signal "1" is input, the signal generator 214 outputs the gate output enable signal GOE in which the high level and the low level are repeatedly repeated. ) Here, the gate driver 220 does not supply the scan pulse in the masking period of the gate output enable signal GOE.

As such, when the distortion occurs in at least one of the signals input from the system, the supply of scan pulses is blocked, thereby preventing unwanted data from being supplied to the pixels.

As described above, according to the present invention, by supplying a desired data voltage to each pixel by controlling whether scan pulses are supplied according to the states of signals input from the system, gray scales can be accurately implemented in each pixel. .

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (25)

A liquid crystal display panel formed by crossing a plurality of data lines and a plurality of gate lines; A timing controller determining whether the signals inputted from the system are distorted and supplying the gate output enable signal or masking the gate output enable signal according to the determination result; And A gate driver configured to sequentially supply scan pulses to the gate lines in response to a normal gate output enable signal from the timing controller or to stop supply of scan pulses in response to a masked gate output enable signal from the timing controller Liquid crystal display comprising a. The method of claim 1, The timing controller, A flip-flop for outputting a data output enable signal input from the system in a specific section of the vertical synchronization signal input from the system; A phase frequency for detecting a period of a clock signal, a horizontal synchronization signal and a vertical synchronization signal input from the system, and detecting a period of a data output enable signal input from the flip-flop to output a normal signal or an error signal according to a detection result. Detection unit; A masking discriminating unit which determines masking of the gate output enable signal using the signals output from the phase frequency detecting unit; And A signal generator for normally outputting the gate output enable signal or masking the gate output enable signal according to an output signal of the masking discriminator Liquid crystal display comprising a. The method of claim 2, And the flip-flop outputs the input data output enable signal to the phase frequency detector in the rising period of the input vertical synchronization signal. The method of claim 2, The phase frequency detector detects the period of the clock signal by counting the period of the input clock signal, temporarily stores the detected clock signal period, and counts the period of the input horizontal synchronization signal to count the period of the horizontal synchronization signal. Detects a period and temporarily stores the detected horizontal sync signal period, detects a period of the input vertical sync signal, temporarily stores the detected vertical sync signal period, and a period of a data output enable signal input from the flip-flop And temporarily store the detected data output enable signal period. The method of claim 4, wherein The phase frequency detector may compare the detected clock signal period with a predetermined reference clock period and determine masking of the first normal signal “0” when the detected clock signal period matches the predetermined reference clock period. And outputs a first error signal " 1 " to the masking discrimination unit if the detected clock signal period does not match the predetermined reference clock period as a result of the comparison. The method of claim 5, wherein The phase frequency detection unit compares the detected horizontal synchronization signal period with a predetermined reference horizontal period, and when the detected horizontal synchronization signal period matches the predetermined reference horizontal period, masking the second normal signal "0". And outputting a second error signal " 1 " to the masking determination unit if the detected horizontal synchronization signal period and the predetermined reference horizontal period do not match as a result of the comparison. The method of claim 6, The phase frequency detection unit compares the detected vertical synchronization signal period with a predetermined reference vertical period, and when the detected vertical synchronization signal period matches the predetermined reference vertical period, masking a third normal signal "0". And outputting a third error signal " 1 " to the masking determination unit if the detected vertical synchronization signal period and the predetermined reference vertical period do not match. The method of claim 7, wherein The phase frequency detection unit compares the detected data output enable signal period with a predetermined data output period, and if the detected data output enable signal period matches the predetermined data output period, the fourth normal signal " 0 " Is output to the masking discrimination unit, and if the detected data output enable signal period and the predetermined reference vertical period are inconsistent, a fourth error signal "1" is output to the masking discrimination unit. Device. The method of claim 8, The masking discriminator includes a logic sum gate having four input terminals connected to the output terminals of the phase frequency detector and one output terminal connected to the signal generator. Liquid crystal display comprising a. The method of claim 9, When the first to fourth normal signals "0" are input from the phase frequency detector, the logic sum gate outputs an output control signal "0" to the signal generator by performing a logical sum of the input first to fourth normal signals. A liquid crystal display device. The method of claim 10, And the signal generator supplies the gate output enable signal to the gate driver in response to the output control signal " 0 ". The method of claim 9, The logic sum gate outputs a masking signal " 1 " to the signal generator by summing the input signals when the error signal " 1 " of the first to fourth error signals is input from the phase frequency detector. Liquid crystal display device. The method of claim 12, And the signal generator masks the gate output enable signal in response to the masking signal " 1. " A driving method of a liquid crystal display device having a liquid crystal display panel having a plurality of gate lines formed therein, Determining whether the signals inputted from the system are distorted; Generating a normal gate output enable signal or a masked gate output enable signal according to the determination result; And Sequentially supplying scan pulses in response to the normal gate output enable signal or stopping supply of scan pulses in response to the masked gate output enable signal Method of driving a liquid crystal display comprising a. The method of claim 14, The determining step, Outputting a data output enable signal input from the system in a specific section of the vertical synchronization signal input from the system; Detecting a period of a clock signal, a horizontal synchronization signal, and a vertical synchronization signal input from the system, and detecting a period of the output data output enable signal to generate one or more normal signals or one or more error signals according to a detection result ; And Determining masking of the gate output enable signal using the one or more normal signals or one or more error signals; Method of driving a liquid crystal display comprising a. The method of claim 15, And in the signal generating step, outputting the input data output enable signal in a rising interval of the input vertical synchronization signal. The method of claim 15, In the signal generating step, counting the period of the input clock signal to detect the period of the clock signal, and temporarily stores the detected clock signal period, counting the period of the input horizontal synchronization signal to count the period of the horizontal synchronization signal Detect a period and temporarily store the detected horizontal synchronization signal period, detect the period of the input vertical synchronization signal, temporarily store the detected vertical synchronization signal period, detect the period of the output data output enable signal, And temporarily storing the detected data output enable signal period. The method of claim 17, In the signal generating step, when the detected clock signal period and the predetermined reference clock period coincide with each other by comparing the detected clock signal period with a predetermined reference clock period, a first normal signal “0” is generated. And a first error signal " 1 " is generated when the detected clock signal period and the predetermined reference clock period do not match. The method of claim 18, In the signal generating step, when the detected horizontal synchronous signal period is compared with a predetermined reference horizontal period, a second normal signal "0" is generated when the detected horizontal synchronous signal period matches the predetermined reference horizontal period. And if the detected horizontal synchronization signal period is inconsistent with the predetermined reference horizontal period, a second error signal " 1 " is generated. The method of claim 19, In the signal generating step, a third normal signal "0" is generated when the detected vertical synchronous signal period and the predetermined reference vertical period coincide with each other by comparing the detected vertical synchronous signal period with a predetermined reference vertical period. And if the detected vertical synchronization signal period and the predetermined reference vertical period do not match, a third error signal "1" is generated. The method of claim 20, In the signal generating step, comparing the detected data output enable signal period with a predetermined data output period and comparing the detected data output enable signal period with the predetermined data output period results in a fourth normal signal " And a fourth error signal " 1 " when the detected data output enable signal period and the predetermined reference vertical period do not match. The method of claim 21, And in the masking determination step, an output control signal "0" is generated when the first to fourth normal signals are generated. The method of claim 22, And in the gate output enable signal generating step, generating the normal gate output enable signal in response to the output control signal " 0 ". The method of claim 21, And in the masking determining step, a masking signal "1" is generated when at least one error signal of the first to fourth error signals is generated. The method of claim 24, And in the gate output enable signal generating step, generating the masked gate output enable signal in response to the masking signal " 1 ".

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