KR20080037343A - Mother substrate for display apparatus - Google Patents

Abstract

A mother substrate for a display device is provided to increase the density of a periphery of a measuring mark in a measuring unit by forming a dummy pattern at the periphery of the measuring mark. A mother substrate for a display device comprises a thin film transistor layer and a measuring unit(202). The thin film transistor layer is formed on a display cell region. The measuring unit is formed at a peripheral region enclosing the display cell region. The measuring unit includes a measuring mark(122c) and a dummy pattern(122b). The measuring mark measures an etch degree of the thin film transistor layer. The dummy pattern is densely formed at a periphery of the measuring mark. The measuring unit includes a first measuring unit, a second measuring unit, and a third measuring unit. The first measuring unit includes a first measuring mark formed of a gate metal layer and a first dummy pattern formed at a periphery of the first measuring mark. The second measuring unit includes a second measuring mark formed of a source metal layer and a second dummy pattern formed at a periphery of the second measuring mark. The third measuring unit includes a third measuring mark formed of a transparent metal layer and a first dummy pattern formed at a periphery of the third measuring mark.

Description

Motherboard for display {MOTHER SUBSTRATE FOR DISPLAY APPARATUS}

1 is a plan view of a mother substrate for a display device according to a first embodiment of the present invention.

FIG. 2A is an enlarged view of the measuring unit of FIG. 1. FIG.

FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 1.

3A is a plan view of a measuring unit according to a second exemplary embodiment of the present invention.

FIG. 3B is a cross-sectional view taken along the line II-II 'of FIG. 3A.

4A is a plan view of a measuring unit according to a third exemplary embodiment of the present invention.

4B is a cross-sectional view taken along the line III-III ′ of FIG. 4A.

5A is a perspective view of a measuring unit according to a fourth exemplary embodiment of the present invention.

5B is a conceptual diagram conceptually illustrating a cross section of the measuring unit of FIG. 5A.

<Explanation of symbols for main parts of the drawings>

500: mother substrate for display device DCA: display cell area

SA: outer area TFT: thin film transistor

202, 204, 206: first, second, third measuring unit

122b. 152b and 172b: first, second and third dummy patterns

122c, 152c, 172c: first, second and third measurement marks

208: fourth measuring unit

124c, 154c, 174c: first, second and third measurement bars

124b, 154b, 174b: first, second and third patterns

The present invention relates to a mother substrate for a display device, and more particularly to a mother substrate for a display device including a measurement unit for measuring the etching degree of the thin film transistor layer.

In general, to fabricate an array substrate, a gate metal layer is formed on a base substrate, the gate metal layer is patterned to form a gate pattern, a gate insulating layer is formed on the base substrate including the gate pattern, and the gate insulating layer A source pattern is formed by patterning a source metal layer formed thereon. Subsequently, a passivation layer is formed on the base substrate including the source pattern, and the pixel electrode is formed in contact with the switching element.

The gate metal layer, the source metal layer, or the passivation layer is patterned using a photolithography process. In the photolithography process, a photoresist layer is formed on a target thin film, and the patterned photoresist layer is used to pattern the thin film using the patterned photoresist layer. At this time, whether the etching degree of the thin film is appropriate is measured by using the CD (Critical Dimension Bar) formed in the peripheral area of the display cell area to measure the etching degree of the patterned thin film.

The etching degree measured using the CD bar is different depending on the region where the pattern is complicated and the density is high, and the region where the pattern is simply formed, even when the same thin film is patterned. This is because the interference effect of interfering patterns adjacent to each other in the etching process is different.

In this respect, since the density of the display cell region and that of the region where the CD bar is formed are different from each other, when the etching degree of the thin film of the display cell region is measured using the CD bar, the display cell region is substantially separated from the density of the display cell region. The etching degree measured by the CD bar is larger than the etching degree of the thin film. Accordingly, there is a problem that the reliability of the CD bar is lowered and the reliability of the adjustment of the etching conditions based on the etching degree measured by the CD bar is lowered, thereby lowering the reliability of the manufacturing process.

Accordingly, the technical problem of the present invention has been conceived in this respect, and an object of the present invention is to provide a mother substrate for a display device including a measuring unit which improves reliability in measuring an etching degree.

A mother substrate for a display device for realizing the above object of the present invention is formed in a thin film transistor layer formed in a display cell region and an outer region surrounding the display cell region, and a measurement mark measuring an etching degree of the thin film transistor layer. And a measuring unit having a dummy pattern densely formed around the measuring mark.

According to the mother substrate for the display device, it is possible to improve the reliability of the etching accuracy measured using the measurement unit, it is possible to improve the reliability of the etching process and the quality of the product.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a mother substrate for a display device according to a first embodiment of the present invention.

FIG. 2A is an enlarged view of the measuring unit of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 1.

1 to 2B, the base substrate 110 of the mother substrate 500 for a display device includes a display cell area DCA and an outer area SA surrounding the display cell area DCA. . The display cell area DCA includes a display area DA in which a plurality of pixel areas are formed to display an image, and a peripheral area PA of the display area DA.

A thin film transistor layer in which a plurality of thin films is stacked is formed in the display area DA of the display cell area DCA, and a plurality of terminals necessary for driving are provided in the peripheral area PA of the display cell area DCA. In the outer area SA, test terminals, measurement terminals, and the like, which are necessary for a manufacturing process of the mother substrate 500 for the display device, are formed. The display cell area DCA including the display area DA and the peripheral area PA and the outer area SA are cut by the display substrate mother substrate 500 in units of display cells by a subsequent process. Are separated from each other.

The thin film transistor layer formed on the display area DA may include a gate pattern formed of a gate metal layer, a gate insulating layer 130 formed on the gate pattern, and a gate metal layer formed on the gate insulating layer 130. And a passivation layer 160 formed on the source pattern, and a pixel electrode PE formed on the passivation layer 160 and connected to the switching element TFT.

The gate pattern of the thin film transistor layer is formed by patterning the gate metal layer made of a low resistance metal material, and includes a gate line GL and a gate electrode GE of the switching element TFT connected to the gate line GL. ). The gate insulating layer 130 is made of, for example, silicon nitride (SiNx). The source pattern is formed by patterning the source metal layer, and includes a source wiring DL that intersects the gate wiring GL and partitions a pixel region, and a source of the switching element TFT connected to the source wiring DL. An electrode SE and a drain electrode DE of the switching element TFT spaced apart from the source electrode SE are included. The passivation layer 160 is made of, for example, silicon nitride (SiNx).

In the outer area SA, a first measurement unit 202 including a first measurement mark 122c and a first dummy pattern 122b densely formed around the first measurement mark 122c is formed. The first measuring unit 202 is separated from the display cell area DCA in the cutting step of individualizing the display substrate from the mother substrate 500 for the display device.

The first measurement mark 122c and the first dummy pattern 122b of the first measurement unit 202 are made of the same metal layer, and are made of the gate metal layer. In the forming of the gate pattern, the first measuring unit 202 is formed using the same mask as the mask forming the gate pattern. The gate insulating layer 130 and the passivation layer 160 are sequentially stacked on the first measuring unit 202.

In order to pattern the gate metal layer, a photoresist layer is applied on the gate metal layer, a photoresist pattern formed by patterning the photoresist layer is formed, and the gate metal layer is wet-etched using the photoresist pattern as a mask. do. The gate metal layer is patterned to form the gate pattern, and the gate pattern is formed by being relatively embedded in the wet pattern than the photoresist pattern. In this case, the degree of embedding of the gate pattern relative to the photoresist pattern, that is, the degree of etching of the gate pattern may be measured using the first measuring unit 202.

The first measuring unit 202 has a box shape by the first edge line 122a formed at the outermost side of the first dummy pattern 122b. The first measurement mark 122c and the first dummy pattern 122b are disposed in an inner region of the box-shaped first measurement unit 202. The first measurement mark 122c substantially corresponds to a pattern capable of measuring an etching degree of the gate metal layer, and the peripheral density of the first measurement mark 122c is increased by the first dummy pattern 122b. The density of the display cell area DCA, that is, the gate line GL and the gate electrode GE are corrected to be equal to or similar to a degree adjacent to each other.

A plurality of first measurement marks 122c may be formed in the first measurement unit 202, and when a plurality of first measurement marks 122c are formed, the sizes of the first measurement marks 122c may be Can be formed differently. Each first measurement mark 122c is formed in a bar shape, for example.

For example, the first dummy pattern 122b may not be overlapped with the first measurement mark 122c and may be formed in a line shape having directivity in one direction. The first dummy pattern 122b may have a shape similar to that of the gate line GL of the display cell area DCA, and an extension direction of the line may be the same as an extension direction of the gate line GL. Can be. Accordingly, the extending direction of the first measurement mark 122c may be perpendicular to the extending direction of the line shape. The density of the first dummy pattern 122b can be adjusted by adjusting the interval of the line shape of the first dummy pattern 122b, and the peripheral density of the first measurement mark 122c is the display cell area. It can be the same as or similar to the density of (DCA). For example, the line-shaped interval of the first dummy pattern 122b is formed to be equal to the interval of the gate line GL of the display cell area DCA.

An etching degree of the first measuring unit 202 may be measured to estimate and determine an etching degree of the gate pattern formed in the first half of the display cell area. By measuring only the etching degree of the first measuring unit 202, the etching degree of the first measuring unit 202 is used by using the etching degree of the gate pattern formed in the first half of the display cell area DCA. An etching degree of the gate pattern may be estimated. Since the first measuring unit 202 includes the first dummy pattern 122b, reliability of estimating an etching degree of the gate pattern using the first measuring unit 202 may be improved. Accordingly, the etching condition of the gate pattern of the display cell area DCA may be adjusted using the first measuring unit 202, thereby improving reliability of the etching process of the gate metal layer.

3A is a plan view of a measuring unit according to a second exemplary embodiment of the present invention.

FIG. 3B is a cross-sectional view taken along the line II-II 'of FIG. 3A.

Referring to FIGS. 1, 3A, and 3B, the second measuring unit 204 may include a second dummy pattern 152b densely formed around the second measuring mark 152c and the second measuring mark 152c. Include.

The second measurement mark 152c and the second dummy pattern 152b of the second measurement unit 204 have the same metal layer, and the same source as the source wiring DL formed in the display cell area DCA. It consists of a metal layer. The second measuring unit 204 is formed using the same mask as the mask for patterning the source pattern. The second measuring unit 204 is formed on the gate insulating layer 130, and the passivation layer 160 is formed on the second measuring unit 204.

The second measuring unit 204 is formed in a box shape by a second edge line 152a formed at the outermost side of the second dummy pattern 152b. The edge shape of the second measurement unit 204 and the second measurement mark 152c may be the same as the shape of the first measurement unit 202 and may be formed jointly. The second measurement mark 152c and the second dummy pattern 152b are disposed in an inner region of the box-shaped second measurement unit 204. The plurality of second measurement marks 152c may be arranged in an inner region of the second measurement unit 204, and the second measurement marks 152c may have a bar shape. For example, the second dummy pattern 152b may be formed in a line shape in which a plurality of second dummy patterns 152b extend in the same direction as the extension direction of the source wiring DL and are arranged in parallel in a direction perpendicular to the extension direction. In this case, the second dummy pattern 152b may have a line shape perpendicular to the first dummy pattern 122b. For example, an interval between the lines of the second dummy pattern 152b may be equal to an interval between the source lines DL of the display cell area DCA.

The peripheral density of the second measurement mark 152c is increased by the second dummy pattern 152b. An etching degree of the source metal layer may be measured by the second measurement mark 152c, and a peripheral density of the second measurement mark 152c is determined by the second dummy pattern 152b. The density of DCA), that is, the source pattern including the source wiring DL is corrected to be equal to or similar to the extent to which they are adjacent to each other.

Conventionally, the metal pattern is not formed around the second measurement mark, or the first measurement mark made of the gate metal layer is disposed so that the density of the existing measurement unit and the density of the display cell area are different from each other. Accordingly, even when the etching degree is measured using the conventional measuring unit, the etching degree of the source pattern which can be estimated from the etching degree of the measuring unit is different from the actual value, so that the reliability of the conventional measuring unit is lowered. There was this.

However, the etching degree measured by the second measuring unit 204 by forming the second dummy pattern 152b around the second measuring mark 152c according to the present invention is the actual etching of the source pattern. Since the value is the same as or similar to the degree, the second measurement unit 204 may have reliability for the degree of etching of the source pattern estimated. Accordingly, the etching conditions of the source pattern of the display cell area DCA may be adjusted using the second measuring unit 204, thereby improving reliability of the etching process.

4A is a plan view of a measuring unit according to a third exemplary embodiment of the present invention.

4B is a cross-sectional view taken along the line III-III ′ of FIG. 4A.

Referring to FIGS. 1, 4A, and 4B, the third measuring unit 206 may include a third dummy pattern 172b densely formed around the third measuring mark 172c and the second measuring mark 172c. Include. The third measurement mark 172c of the third measurement unit 206 and the third dummy pattern 172b have the same metal layer and the same transparent metal layer as the pixel electrode PE formed in the display cell area DCA. Is done. The third measuring unit 206 is formed using the same mask as the mark patterning the pixel electrode PE. The third measuring unit 206 is formed on the passivation layer 160 formed on the gate insulating layer 130.

The third measuring unit 206 is formed in a box shape by a third edge line 172a formed at the outermost side of the third dummy pattern 172c. The third measurement mark 172c and the third dummy pattern 172b are disposed in an inner region of the box-shaped third measurement unit 206. The plurality of third measuring marks 172c are arranged in an inner region of the third measuring unit 206, and the third measuring marks 172c have the same bar shape as the first and second measuring marks. Can be made.

The third dummy pattern 172b may be formed in a pattern having a surface like the pixel electrode PE formed in the display cell area DCA. The third dummy pattern 172b is patterned, for example, in a square shape. The third dummy pattern 172b corrects the peripheral density of the third measurement mark 172c to be the same as or similar to the density of the display cell area DCA, and thus the third dummy pattern 172b. The shape of is preferably formed in consideration of the shape of the pixel electrode PE and the distance between the adjacent pixel electrodes PE.

As described above, the first, second and third measurement units 202, 204, and 206 illustrated in FIGS. 1, 2A, and 4B have the first, second and third measurement marks 122c, The peripheral density of the first, second and third measurement marks 122c, 152c, and 172c is formed by forming the first, second and third dummy patterns 122b, 152b, and 172b around the 152c and 172c, respectively. The degree is corrected to be the same as or similar to the density of the display cell area DCA. Accordingly, the gate metal layer, the source metal layer, and the transparent metal layer of the display cell area DCCA estimated by the degree of etching measured using the first, second, and third measuring units 202, 204, and 206. The reliability of the etching process may be improved by improving the reliability of the etching degree.

Meanwhile, the first, second and third measuring units 202, 204, and 206 are formed at the same time in the process of forming each thin film of the thin film transistor layer, so that the outer portion of the mother substrate 500 for one display device is formed. It is preferable that the said 1st, 2nd and 3rd measuring parts 202, 204, and 206 are formed simultaneously in the area SA.

The first, second, and third measuring units 202, 204, and 206 may be independently formed in the outer area SA, thereby lowering the utilization of the outer area SA. And the third measuring units 202, 204, and 206 are formed independently of each other, so that the third measuring units 202, 204, and 206 are not interfered with by the lower or upper metal layer when measuring the etching degree using the respective measuring units. The reliability of the etching degree of each thin film estimated from the etching degree can be further improved.

5A is a perspective view of a measuring unit according to a fourth exemplary embodiment of the present invention.

5B is a conceptual diagram conceptually illustrating a cross section of the measuring unit of FIG. 5A. Hereinafter, the gate line GL and the source line DL, the display cell area DCA, and the outer area SA of FIG. 1 will be described with reference to FIGS. 5A and 5B. The first, second and third measuring units 202, 204 and 206 in FIG. 5A are indicated by reference numerals 208a, 208b and 208c, respectively.

The fourth measuring unit 208 has a structure in which the first, second and third measuring units 202, 204, and 206 illustrated in FIGS. 2A, 3A, and 4A are sequentially stacked and overlapped with each other. The measurement marks 122c, 152c, and 172c of the first, second, and third measurement units 202, 204, and 206 are referred to as first, second, and third measurement bars for convenience of description, respectively. The dummy patterns 122b, 152b, and 172b of are referred to as first, second, and third patterns for convenience of description.

5A and 5B, the fourth measuring unit 208 includes a first measuring unit 208a including a first measuring bar 124c and a first pattern 124b, and the first measuring unit 208a. A second measurement part 208b formed on the second measurement bar 154c and including a second measurement bar 154c and a second pattern 154b, and a third measurement bar 174c formed on the second measurement part 208c. And a third measuring unit 208c including a third pattern 174b.

The first measurement bar 124c is formed of the same gate metal layer as the gate pattern of the display cell area DCA, and the etching degree of the gate metal layer may be measured using the first measurement bar 124c. Can be. The second measurement bar 154c may be formed of the same source metal layer as the source pattern, and the etching degree of the source metal layer may be measured using the second measurement bar 154c. The third measurement bar 174c may be formed of the same transparent metal layer as the pixel electrode PE, and the etching degree of the transparent metal layer may be measured using the third measurement bar 174c.

The first, second and third measuring bars 124c, 154c, and 174c may be formed independently of each other so as not to overlap each other. For example, the first, second, and third measurement bars 124c, 154c, and 174c may be formed in each area by dividing the internal area of the fourth measurement unit 208 into three parts. A plurality of first, second and third measuring bars 124c, 154c, and 174c may be respectively formed in the three divided regions, and for example, the plurality of first measuring bars 124c may have different sizes. Is formed.

The first pattern 124b is formed around the first measurement bar 124c and is formed of the gate metal layer. The first pattern 124b may extend in the same direction as the extension direction of the gate line GL and may have a line shape arranged in parallel in a direction perpendicular to the extension direction.

The second pattern 154b is formed around the second measurement bar 154c and is formed of the source metal layer. The second pattern 154b may be formed to be perpendicular to the line shape of the first pattern 124b, for example. The second pattern 154b is formed to overlap the first measurement bar 124c and the first pattern 124b on the first measurement bar 124c and the first pattern 124b.

The third pattern 174b is formed around the third measurement bar 174c and is formed of the transparent metal layer. For example, the third pattern 174b may have a square shape. The third pattern 174b is formed on the first and second patterns 124b and 154b, the first and second measurement bars 124c and 154c, and the first and second patterns 124b and 154b and overlap the first and second measurement bars 124c and 154c.

The fourth measuring unit 208 has a peripheral density of the first, second and third measuring bars 124c, 154c and 174c due to the first, second and third patterns 124b, 154b and 174b. Is corrected to be the same as or similar to the density of the display cell area DCA, thereby providing reliability in estimating the etching degree of each layer through the etching degree measured by the fourth measuring unit 208, 208) and the reliability of the etching process can be improved.

Although the cross section of the fourth measuring unit 208 shown in FIG. 5B is slightly different from the actual cross section, FIG. 5B illustrates the first, second and third patterns 124b and 154b of the fourth measuring unit 208. , 174b) increases the peripheral density of the first, second and third measurement bars 124c, 154c, and 174c than the density of the case where only the measurement bar corresponding to each layer is formed. It is a figure shown.

On the other hand, by using the fourth measuring unit 208 to measure the degree of etching of each floor by using a lower portion of the fourth measuring unit 208 in the outer area (SA), the utilization of the outer area (PA) There is an advantage to increase.

According to such a mother substrate for a display device, a peripheral pattern of the measurement mark is increased by forming a dummy pattern around the measurement mark of the measurement unit for measuring the etching degree of each thin film of the thin film transistor layer formed in the display cell region, The density of the measurement unit may equally or similarly correct the density of the display cell area.

Accordingly, the etching degree of each thin film can be estimated through the etching degree measured using the measuring unit, and the reliability of the estimated etching rate of each thin film can be improved, thereby improving the reliability of the etching process of the thin film. You can.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (8)

A thin film transistor layer formed in the display cell region; And And a measurement unit formed in an outer region surrounding the display cell region and having a measurement mark measuring an etching degree of the thin film transistor layer and a dummy pattern densely formed around the measurement mark. The method of claim 1, wherein the measuring unit A first measurement unit having a first measurement mark formed of a gate metal layer and a first dummy pattern formed around the first measurement mark and formed of the gate metal layer; A second measurement part having a second measurement mark formed of a source metal layer and a second dummy pattern formed around the second measurement mark and formed of the source metal layer; And And a third measurement part having a third measurement mark formed of a transparent metal layer and a third dummy pattern formed around the third measurement mark and formed of the transparent metal layer. The method of claim 2, wherein the first, second and third measuring unit The mother substrate for a display device, characterized in that formed adjacent to each other in the outer region. The mother substrate of claim 2, wherein the first, second, and third measurement units are formed to overlap the outer area. The method of claim 4, wherein the first, second and third dummy patterns overlap each other. And the first, second and third measurement marks are non-overlapping with each other. The mother substrate of claim 2, wherein the first and second dummy patterns have a line shape extending in a direction perpendicular to each other. The mother substrate of claim 6, wherein the third dummy pattern is patterned in a square shape. The thin film transistor layer of claim 2, wherein the thin film transistor layer A gate pattern including a gate wiring formed of the gate metal layer; A source pattern formed on the gate pattern and including a source wiring formed of the source metal layer; And And a pixel electrode formed on the source pattern and formed of the transparent electrode layer.

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