KR20080032276A - Display substrate and method for manufacturing the same - Google Patents

Abstract

A display substrate and a manufacturing method thereof are provided to form a first electrode as a common electrode after forming an active layer and a gate insulating layer, thereby preventing metal deposition and accordingly suppressing defects and reduction of an aperture ratio. A first metal pattern is formed on a first substrate(110), and includes a gate line and a storage line. A gate insulating layer(120) is formed on the first substrate where the first metal pattern is formed. A second metal pattern is formed on the gate insulating layer, and includes a data line for defining a unit pixel by crossing the gate line. A first electrode is formed in correspondence with the unit pixel on the gate insulating layer where the second metal pattern is formed, and electrically connected with the storage line. A passivation layer(160) is formed on the gate insulating layer where the first electrode is formed. A second electrode(170) is formed in correspondence with the unit pixel on the passivation layer.

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 10 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: display substrate 200: opposing substrate

300: liquid crystal layer 110: base substrate

120: gate insulating layer 142: first cover electrode

142: second cover electrode 151: first electrode

152: third cover electrode 160: passivation layer

170: second electrode 171: first line

172: second line 400: liquid crystal display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display substrate and a method for manufacturing the same, and more particularly, to a display substrate and a method for manufacturing the same in a field field switching mode.

In general, a transverse electric field type liquid crystal display panel is composed of a display substrate, an opposing substrate, and a liquid crystal layer interposed between the display substrate and the opposing substrate, and the display substrate includes a plurality of liquid crystal layers intersecting each other. Unit pixels are defined.

 In the unit pixel, a thin film transistor, a common electrode, and a pixel electrode are formed. The thin film transistor includes a gate electrode, a first insulating layer formed on the gate electrode, an active layer overlapping the gate electrode on the first insulating layer, and a source electrode and a drain electrode formed to partially overlap the active layer on the active layer. A second insulating film is formed on the thin film transistor, and the pixel electrode is formed on the second insulating film corresponding to the unit pixel. The common electrode is formed on the same layer as the gate electrode corresponding to the unit pixel, and the pixel electrode is connected to the first line and the first line parallel to the data line to form a transverse electric field therebetween. It is patterned to include a plurality of parallel second lines.

On the other hand, the common electrode is formed of a transparent conductive material such as indium tin oxide to improve the aperture ratio of the unit pixel.

In this case, when the common electrode is formed of a transparent conductive material such as indium tin oxide, a metal component may be precipitated from the common electrode by a high temperature deposition process for forming the first insulating layer and the active layer. The metal component deposited from the common electrode rapidly reduces the transmittance and display characteristics of the liquid crystal display panel.

In order to suppress this, when the deposition process for forming the first insulating film and the active layer is performed at a low temperature, the film quality of the first insulating film and the active layer may be changed, resulting in deterioration of the reliability of the liquid crystal display panel and various defects such as afterimage defects. There is a problem.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for reducing defects.

Another object of the present invention is to provide a method of manufacturing the display substrate.

In order to achieve the above object of the present invention, the display substrate according to the embodiment includes a first metal pattern, a gate insulating layer, a second metal pattern, a first electrode, a passivation layer, and a second electrode.

The first metal pattern is formed on the first substrate, and includes a gate wiring and a storage wiring. The gate insulating layer is formed on the first substrate on which the first metal pattern is formed. The second metal pattern includes a data line formed on the gate insulating layer and crossing the gate line to define a unit pixel. The first electrode is formed to correspond to the unit pixel on the gate insulating layer on which the second metal pattern is formed, and is electrically connected to the storage wiring. The passivation layer is formed on the gate insulating layer on which the first electrode is formed. The second electrode is formed on the passivation layer corresponding to the unit pixel.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including a gate wiring and a storage wiring on a substrate, and forming the first metal pattern on the substrate. Forming a gate insulating layer on the substrate, forming a second metal pattern on the gate insulating layer, the second metal pattern including a data line crossing the gate line to define a unit pixel; Forming a patterned first electrode corresponding to the unit pixel on the formed gate insulating layer, forming a passivation layer on the gate insulating layer on which the first electrode is formed, and the passivation corresponding to the unit pixel Forming a second electrode on the layer.

According to such a display substrate and a method of manufacturing the same, in the conventional transverse electric field structure display substrate in which the common electrode is formed under the gate insulating layer, metal precipitation phenomenon occurring at the common electrode when the gate insulating layer is formed can be prevented.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1.

1 and 2, the liquid crystal display panel 400 includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 interposed between the display substrate 100 and the opposing substrate 200. It includes.

The display substrate 100 includes a base substrate 110. The base substrate 110 is made of a transparent material through which light can pass. In one example, the base substrate 110 is a glass substrate. A plurality of unit pixels P are defined on the base substrate 110 by gate lines GL and data lines DL intersecting the gate lines GL. A thin film transistor TFT connected to the gate line GL and the data line DL, a storage line STL extending in the same direction as the gate lines GL, and a first electrode in the unit pixel P 151 and the second electrode 170 are formed.

In detail, the gate lines GL and the storage line STL are first metal patterns formed by patterning the same metal layer. In addition, the first metal pattern includes a gate electrode G protruding from the gate line GL.

A gate insulating layer 120 is formed on the base substrate 110 on which the first metal pattern including the gate lines GL, the gate electrode G, and the storage line STL is formed. For example, the gate insulating layer 120 is formed of silicon nitride (SiNx), and the first insulating hole H1 exposes the storage wiring STL in the unit pixel P in the gate insulating layer 120. Is formed. In addition, a second hole H2 exposing one end of the gate line GL and the storage line STL is also formed. One end of the gate line GL and the storage line STL is an area in which the gate pad part GP and the storage pad part STP are formed to electrically contact an external driving chip.

The data lines DL, the source electrode S, and the drain electrode D are formed on the gate insulating layer 120. The data lines DL, the source electrode S, and the drain electrode D are second metal patterns formed by patterning the same metal layer. The source electrode S protrudes from the data line DL and partially overlaps the gate electrode G. The drain electrode D is formed spaced apart from the source electrode S by a predetermined interval and partially overlaps the gate electrode G.

The second metal pattern may further include a first cover electrode 142 overlapping the storage line STL and contacting the storage line STL through the first hole H1. In addition, the second metal pattern may further include a second cover electrode 143 formed corresponding to the gate pad part GP and the storage pad part STP.

An active layer A patterned in the same manner as the second metal pattern is formed between the gate insulating layer 120 and the second metal pattern. For example, the active layer A has a structure in which a semiconductor layer 131 made of amorphous silicon and an ohmic contact layer 132 made of n + ion-doped amorphous silicon are sequentially stacked.

In this case, the ohmic contact layer 132 is removed from the source electrode S and the drain electrode D to expose the semiconductor layer 131. The exposed region of the semiconductor layer 131 is a region in which the electrical channel CH of the thin film transistor TFT is formed.

The gate electrode G, the source electrode S, the drain electrode D, and the active layer A constitute the thin film transistor TFT in the unit pixel P.

Meanwhile, when the second cover electrode 143 is formed on the gate pad part GP and the storage pad part STP, the gate pad part GP and the storage pad part STP may correspond to the gate pad part GP and the storage pad part STP. The second hole H2 is formed in the active layer A. Accordingly, one end of the second cover electrode 143 and the gate line GL and one end of the storage line STL contact each other.

The first electrode 151 patterned to correspond to the unit pixel P is formed on the base substrate 110 on which the second metal pattern is formed.

For example, the first electrode 151 is made of a transparent conductive material. As the transparent conductive material, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used.

In addition, the display substrate according to the exemplary embodiment of the present invention is formed on the same layer as the first electrode 151 on the same layer, and is patterned to be the same as the second metal pattern to cover the second metal pattern. It may further include an electrode 152.

The first electrode 151 is in electrical contact with the storage electrode STL through the first hole H1 formed in the gate insulating layer 120. That is, when the first cover electrode 142 is omitted, the first electrode 151 is in direct contact with the storage wiring STL, and when the first cover electrode 142 is formed, the first electrode 151 is formed. ) Is electrically connected to the storage line STL through the first cover electrode 142.

That is, the first electrode 151 formed in the plurality of unit pixels P is a common electrode to which a common voltage is applied from the storage line STL.

The passivation layer 160 is formed on the base substrate 110 on which the first electrode 151 and the third cover electrode 152 are formed. The passivation layer 160 may be formed of, for example, silicon nitride, silicon oxide, or the like. In the passivation layer 160, a contact hole 161 exposing one end of the drain electrode D is formed. In addition, the passivation layer 160 has a third hole H3 corresponding to the data pad part DP formed at one end of the gate pad part GP, the storage pad STP, and the data line DL. Is formed.

The second electrode 170 is formed on the passivation layer 160 corresponding to the unit pixel P. Like the first electrode 151, the second electrode 170 is made of a transparent conductive material. Indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used as the transparent conductive material.

The second electrode 170 is electrically connected to the drain electrode D through the contact hole 161 and receives a pixel voltage provided from the data line DL.

In this case, the second electrode 170 is connected to the first line 171 and the first line 171 extending in the same direction as the data line DL and extends in the same direction as the gate line GL. A plurality of second lines 172.

Since different voltages are applied to the first electrode 151 and the second electrode 170, an electric field of a transverse electric field is formed between the plurality of second lines 172 and the first electrode 151. The liquid crystal molecules of the liquid crystal layer 300 are rearranged by the electric field.

Accordingly, light provided from the rear surface of the liquid crystal display panel 400 is transmitted to display an image on the counter substrate 200.

Hereinafter, a method of manufacturing a display substrate according to an exemplary embodiment of the present invention will be described.

3 to 10 are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 2.

1 and 3, a first metal layer (not shown) is formed on the base substrate 110. The first metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the first metal layer may be formed of two or more layers having different physical properties.

Subsequently, a first photoresist film (not shown) is formed on the first metal layer. The first photoresist film is made of, for example, a positive photoresist in which the exposed region is dissolved by a developer.

Next, the first mask MASK1 is aligned on the base substrate 110 on which the first photoresist film is formed. The first mask MASK1 includes a light transmitting part 4 for transmitting light and a light blocking part 2 for blocking light. Next, the first photoresist film is exposed using the first mask MASK1, and a series of photolithography (PHOTOLITHOGRAPHY) processes for developing and curing the exposed first photoresist film are performed. Accordingly, the first photoresist pattern PR1 is formed on the metal layer.

Subsequently, the first metal layer is patterned by an etching process using the first photoresist pattern PR1 to form a first metal pattern including gate lines GL, a gate electrode G, and a storage line STL. do.

The gate lines GL extend in parallel to each other on the base substrate 110. The gate electrode G is formed to protrude from the gate line GL. The storage line STL extends in parallel with the gate lines GL between the gate lines GL.

An etching process of forming the first metal pattern is, for example, a wet etching process. After the etching process is completed, an ashing process of removing the first photoresist pattern PR1 remaining on the first metal pattern is performed.

The ashing process is performed by an oxygen plasma treatment, and is performed every time the etching process using the photoresist pattern is finished.

 The first photoresist film may be made of a negative photoresist. In this case, the arrangement of the light blocking portion 4 and the light transmitting portion 2 is reversed in the first mask MASK1.

Referring to FIG. 4, the gate insulating layer 120 is formed on the base substrate 110 on which the first metal pattern is formed by using a chemical vapor deposition method. For example, the gate insulating layer 120 may be formed of silicon nitride or silicon oxide. In addition, the gate insulating layer 120 may be formed in a double layer structure having different materials and forming processes.

Subsequently, the semiconductor layer 131 and the ohmic contact layer 132 are sequentially formed on the gate insulating layer 120 using the chemical vapor deposition method.

The semiconductor layer 131 is made of, for example, amorphous silicon, and the ohmic contact layer is made of, for example, amorphous silicon doped with a high concentration of n-type ions.

Next, a second photoresist pattern PR2 is formed on the ohmic contact layer 132 by a photolithography process using the second mask MASK2. Subsequently, the ohmic contact layer 132, the semiconductor layer 131, and the gate insulating layer 120 are simultaneously patterned by an etching process using the second photoresist pattern PR2 to form the photoresist in the unit pixel P. The first hole H1 exposing the storage line STL is formed. In addition, a second hole H2 exposing one end of the gate line GL and one end of the storage line STL is formed.

When the etching process using the second photoresist pattern PR2 is completed, an ashing process of removing the second photoresist pattern PR2 is performed.

Referring to FIG. 5, a second metal layer 140 is formed on the ohmic contact layer 132 on which the first and second holes H1 and H2 are formed. The second metal layer 140 may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, and may be deposited by a sputtering process. In addition, the second metal layer 140 may be formed of two or more layers having different physical properties.

Next, a third photoresist pattern PR3 is formed on the second metal layer 140 by a photolithography process using the third mask MASK3.

The third photoresist pattern PR3 may include a data line region (not shown) in which the data line DL is formed, a source electrode region SEA in which the source electrode S of the thin film transistor TFT is formed, and a channel CH. ) Is formed in the drain electrode region DEA in which the channel region CHA and the drain electrode D are formed. The third photoresist pattern PR3 may also be formed in the storage wiring region STA in which the storage wiring STL is formed.

In detail, the third photoresist pattern PR3 is formed to have a first thickness t1 in the source electrode region SEA, the drain electrode region DEA, the data wiring region (not shown), and the storage wiring region STA. A first pattern PR31 and a second pattern PR32 formed in the channel region CHA at a second thickness t2 are included.

The first pattern PR31 is an area patterned through the light blocking part 2 of the second mask, and the second pattern PR32 is an area patterned through the diffraction part 6 of the second mask MASK2. to be. The diffraction section 6 is provided with a slit (SLIT) pattern for diffracting the light to provide a smaller amount of light than that provided by the exposure section 4. Accordingly, the second pattern PR32 is formed to the second thickness t2 that is thinner than the first thickness t1.

Referring to FIG. 6, the second metal layer 140, the ohmic contact layer 132, and the semiconductor layer 131 are sequentially etched using the third photoresist pattern PR3.

Accordingly, referring to FIG. 5, a second metal pattern including the data line DL, the electrode pattern 141, and the first cover electrode 142 is formed. In this case, the second metal pattern may further include a second cover electrode 143 overlapping one end of the gate line GL and one end of the storage line STL.

The electrode pattern 141 extends from the data line DL to be formed in each unit pixel P, and has a shape in which a source electrode S and a drain electrode D are connected to each other.

Subsequently, the semiconductor layer 131 and the ohmic contact layer 132 are etched using the third photoresist pattern PR3. For example, etching of the semiconductor layer 131 and the ohmic contact layer 132 may be performed by dry etching. Accordingly, an active layer A having a structure patterned in the same manner as the second metal pattern and having the semiconductor layer 131 and the ohmic contact layer 132 stacked thereon is formed under the second metal pattern.

Referring to FIG. 7, the third photoresist patterns PR31 and PR32 are removed by a predetermined thickness in an ashing process using an oxygen plasma. The removed thickness is greater than or equal to the second thickness t2 and less than the first thickness t1.

The second pattern PR32 formed in the channel region CHA is removed by the ashing process, and the source electrode region SEA, the drain electrode region DEA, the data wiring region (not shown), and the storage wiring region ( The third pattern PR33 of the third thickness t3 remains in the STA.

Subsequently, the electrode pattern 141 is etched using the third pattern PR33 to form a source electrode S and a drain electrode D spaced apart from the source electrode S by a predetermined distance. Next, the ohmic contact layer 132 exposed at the spaced portion between the source electrode S and the drain electrode D is etched to form a channel CH exposing the semiconductor layer 131.

Accordingly, the thin film transistor TFT including the gate electrode G, the source electrode S, the drain electrode D, and the active layer A is formed on the base substrate 110.

Subsequently, the third pattern PR33 remaining on the thin film transistor TFT is removed by an ashing process using an oxygen plasma.

1 and 8, a first transparent electrode layer (not shown) is formed on the base substrate 110 on which the thin film transistor TFT is formed. The first transparent electrode layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be formed by a sputtering method.

Subsequently, after forming a fourth photoresist pattern PR4 on the first transparent electrode layer by a photolithography process using a fourth mask MASK4, the fourth process is performed by an etching process using the fourth photoresist pattern PR4. The first transparent electrode layer is patterned to form a first electrode 151 corresponding to the unit pixel P.

Meanwhile, in the method of manufacturing the display substrate according to the exemplary embodiment of the present invention, the first transparent electrode layer is patterned to further add not only the first electrode 151 but also a third cover electrode 152 covering the second metal pattern. It may be formed.

The third cover electrode 152 is formed to prevent etching to the second metal pattern during an etching process for forming the first electrode 151.

Subsequently, an ashing process of removing the fourth photoresist pattern PR4 is performed.

 1 and 9, on the base substrate 110 on which the first electrode 151 and the third cover electrode 152 including the first electrode 151 and the third cover electrode 152 are formed. The passivation layer 160 is formed in this. The passivation layer 160 may be formed by, for example, a chemical vapor deposition method, and may be formed of silicon nitride or silicon oxide.

Subsequently, after the fifth photoresist pattern PR5 is formed on the passivation layer 160 by the photolithography process using the fifth mask MASK5, the etching process using the fifth photoresist pattern PR5 is performed. The passivation layer 160 is patterned. Accordingly, in the passivation layer 160, a contact hole 161 exposing one end of the drain electrode D and one end of the data line, one end of the gate line, and one end of the storage line STL. The third hole H3 corresponding to the negative portion is formed. Accordingly, a data pad DP, a gate pad GP, and a storage pad STP are formed to connect the data line DL, the gate line GL, and the driving chip to a separate driving chip. do. Subsequently, the fifth photoresist pattern PR5 is removed by an ashing process using an oxygen plasma.

1 and 10, a second transparent electrode layer (not shown) is formed on the passivation layer 160 where the contact hole 161 and the third hole H3 are formed. For example, the second transparent electrode layer may be formed of indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be formed by a sputtering method.

Next, after the sixth photoresist pattern PR6 is formed on the second transparent electrode layer by the photolithography process using the sixth mask MASK6, the etching process using the sixth photoresist pattern PR6 is performed. The second transparent electrode layer is patterned to form a second electrode 170 including a first line 171 and a plurality of second lines 172.

In detail, the first line 171 is patterned to extend in the same direction as the data line DL in the unit pixel P, and the plurality of second lines 172 are connected to the first line ( And patterned to extend in the same direction as the gate line GL.

Subsequently, the sixth photoresist pattern PR6 is removed by an ashing process using an oxygen plasma. As a result, the display substrate 100 according to the exemplary embodiment of the present invention is completed.

As described above, according to the manufacturing method of the display substrate according to the exemplary embodiment of the present invention, after forming the active layer A and the gate insulating layer 120 formed by the high temperature deposition process, the first electrode (the common electrode) 151 is formed. Accordingly, it is possible to prevent the metal precipitation phenomenon occurring in the conventional manufacturing process of the display substrate in which the first electrode 151, which is the common electrode, is formed under the active layer A and the gate insulating layer 120. As a result, a decrease in the aperture ratio of the liquid crystal display panel due to metal precipitation can be suppressed and a defect of the liquid crystal display panel can be reduced.

In addition, according to a conventional method of manufacturing a display substrate, a first electrode which is a common electrode is formed using a first mask, a gate wiring is formed using a second mask, and an active layer is formed using a third mask. Although the data wiring is formed using the fourth mask, the passivation layer is patterned using the fifth mask, and the pixel electrode is patterned using the sixth mask. A total of six masks are used. Therefore, a display substrate having a novel structure can be manufactured without increasing the number of masks as compared with the related art.

As described above, according to the present invention, since the first electrode, which is a common electrode, is formed after the active layer and the gate insulating layer formed by the high temperature deposition process are formed, the first electrode is formed by the active layer and the gate insulating layer. The metal precipitation phenomenon which occurs in the manufacturing process of the conventional display substrate which was formed in the lower part can be prevented. As a result, defects in the display substrate and reduction of the aperture ratio due to metal precipitation can be suppressed.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (15)

A first metal pattern formed on the first substrate and including a gate wiring and a storage wiring; A gate insulating layer formed on the first substrate on which the first metal pattern is formed; A second metal pattern formed on the gate insulating layer and including a data line crossing the gate line and defining a unit pixel; A first electrode formed corresponding to the unit pixel on the gate insulating layer on which the second metal pattern is formed, and electrically connected to the storage wiring; A passivation layer formed on the gate insulating layer on which the first electrode is formed; And And a second electrode formed on the passivation layer corresponding to the unit pixel. The display substrate of claim 1, wherein a first hole is formed in the gate insulating layer to expose the storage wiring in the unit pixel. The display substrate of claim 2, wherein the second metal pattern further comprises a first cover electrode contacting the storage wiring through the first hole. The display substrate of claim 1, wherein the second metal pattern further comprises a source electrode protruding from the data line and a drain electrode spaced apart from the source electrode by a predetermined distance. The display substrate of claim 4, further comprising an active layer formed between the second metal pattern and the gate insulating layer to correspond to the data line, the source electrode, and the drain electrode. The display substrate of claim 4, wherein a second hole is formed in the passivation layer to expose one end of the drain electrode, and the second electrode is electrically connected to the drain electrode through the second hole. The display substrate of claim 5, further comprising a second cover electrode formed on the same layer as the first electrode and patterned in the same manner as the second metal pattern to cover the second metal pattern. The display substrate of claim 7, wherein the first electrode and the second cover electrode are formed of a transparent electrode layer that transmits light. The method of claim 1, wherein the second electrode includes a first line extending in the same direction as the data line and a plurality of second lines connected to the first line and extending in the same direction as the gate line. Display substrate. Forming a first metal pattern including a gate wiring and a storage wiring on the substrate; Forming a gate insulating layer on the substrate on which the first metal pattern is formed; Forming a second metal pattern on the gate insulating layer, the second metal pattern including data lines defining unit pixels crossing the gate lines; Forming a first electrode patterned corresponding to the unit pixel on the gate insulating layer on which the second metal pattern is formed; Forming a passivation layer on the gate insulating layer on which the first electrode is formed; And And forming a second electrode on the passivation layer corresponding to the unit pixel. The method of claim 10, further comprising: forming an active layer between the gate insulating layer and the second metal pattern; And And simultaneously patterning the gate insulating layer and the active layer to form a first hole exposing the storage wiring formed in the unit pixel. The method of claim 11, wherein the forming of the second metal pattern is performed. Forming a metal layer on the active layer in which the first hole is formed; Patterning the metal layer to form the second metal pattern; And And patterning the active layer on which the first hole is formed into the same shape as the second metal pattern. The method of claim 12, wherein the forming of the second metal pattern further comprises forming a first cover electrode overlapping the storage line through the first hole. The display of claim 12, wherein the forming of the first electrode further comprises forming a second cover electrode that is patterned in the same manner as the second metal pattern to cover the second metal pattern. Method of manufacturing a substrate. The display device of claim 10, wherein the second electrode extends in a same direction as the data line in the unit pixel and a plurality of second lines connected to the first line and extended in the same direction as the gate line. Method of manufacturing a display substrate characterized in that it is patterned to include.

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