KR20080030386A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent the generation of short between a gate and a bit line contact by forming a nitride-based spacer for the bit line contact on a surface of a contact hole for the bit line contact. A first interlayer dielectric(50) is formed on a semiconductor substrate(10) divided into a cell region and a peripheral region. A gate and a junction region are formed on each region of the semiconductor substrate. The first interlayer dielectric has a contact hole for a landing plug defines a landing plug formation region of the cell region. A landing plug(60) is formed in the contact hole for a landing plug. A second interlayer dielectric(70) is formed on the whole surface of the substrate including the landing plug. The second interlayer dielectric is etched until upper sides of the junction region and the gate of the peripheral region are exposed to form a first contact hole for defining the bit line contact formation region of the peripheral region. A spacer for a bit line contact is formed on both sidewalls of the first contact hole. The second interlayer dielectric is etched to form a second contact hole for defining the bit line contact formation region of the cell region. A barrier layer(90) is formed on a surface of the second contact hole and on the second interlayer dielectric including the spacer for a bit line contact of the peripheral region. A conductive layer for a bit line contact is formed on the barrier layer to gap-fill the first and second contact holes where the barrier layer is formed.

Description

Method of manufacturing semiconductor device

1 to 4 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor substrate 20: gate

30: gate spacer 40: junction region

50: first interlayer insulating film 60: landing plug

70: second interlayer insulating film 80: bit line contact spacer

90a: titanium film 90b: titanium nitride film

90: barrier film 100: tungsten film

Cl, C2, C3: contact hole

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can improve the SAC fail between the gate and the bit line.

As the design rules of semiconductor devices, which are being developed recently, have been reduced, the distances between gates of not only cell regions but also peripheral regions have been narrowed, and the distances between bit line contacts and gates have also narrowed.

On the other hand, the bit line contact is formed on the junction region and the gate of the semiconductor substrate at the same time. As the semiconductor device becomes highly integrated and the distance between the gates becomes narrow, both side walls of the gate during the etching process for forming the bit line contact on the substrate are formed. There is a problem that the spacer formed in the disappearance.

As such, when the spacer for insulation between the bit line and the gate is lost, there is a high possibility that the metal film of the gate and the bit line contact are shorted, which degrades the device characteristics. This will adversely affect the yield improvement of the

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing short circuits between gates and bit lines.

In order to achieve the above object, the present invention is divided into a cell region and a peripheral region, and defining a landing plug forming region of the cell region on a semiconductor substrate having a gate and a junction region having a spacer in each region. Forming a first interlayer insulating film having a contact hole for a landing plug; Forming a landing plug in the landing plug contact hole; Forming a second interlayer insulating film on an entire surface of the substrate including the landing plug; Etching the second interlayer insulating layer until the junction region of the peripheral region and the upper side portion of the gate are exposed to form a first contact hole defining a bit line contact forming region of the peripheral region; Forming a spacer for bit line contacts on both side walls of the first contact hole; Etching the second interlayer insulating layer to form a second contact hole defining a bit line contact forming region in the cell region; Forming a barrier layer on the second interlayer insulating layer including a surface of the second contact hole and a spacer for a bit line contact in the peripheral area; And forming a bit line contact conductive film on the barrier film so that the first and second contact holes in which the barrier film is formed are filled.

The bit line contact spacer may be formed to a thickness of 250 to 300 ∼.

The forming of the bit line contact spacers on both sidewalls of the first contact hole may include forming an insulating layer for spacers on the second interlayer insulating layer including the first contact hole; And etching the entire surface of the insulating film for spacers.

The spacer insulating film is formed of a nitride film.

The barrier film is formed of a laminated film of a titanium film and a titanium nitride film.

The conductive film is formed of a tungsten film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principles of the present invention will be described. According to the present invention, a nitride film-based bit line contact spacer is formed on a contact hole surface for a bit line contact that exposes a junction region of a semiconductor substrate and an upper portion of a gate when forming a bit line contact in a peripheral region. Characterized in that form.

In this case, as the spacer for the bit line contact is formed on the surface of the contact hole, the self alignment contact (SAC) fail between the bit line contact and the gate can be prevented, thereby improving the characteristics of the device.

1 to 4 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 10 is provided, which is divided into a cell region C and a peripheral region P, and each of which has a gate 20 having a gate spacer 30 formed therein.

Then, the junction region 40 is formed in the substrate surface on both sides of the gate 20 on which the spacer 30 is formed.

Next, after depositing the first interlayer insulating layer 50 on the entire surface of the substrate to cover the gate 20, the landing plug contact hole exposing the junction region 40 of the cell region C is etched. To form.

Subsequently, a conductive film is deposited on the first interlayer insulating film 50 including the contact hole, and then etched to form a landing plug 60 in the contact hole.

Subsequently, a second interlayer insulating film 70 is formed on the entire surface of the substrate including the landing plug 60.

Referring to FIG. 2, after forming a mask pattern (not shown) exposing the bit line contact forming region of the peripheral area P on the second interlayer insulating layer 70, the mask pattern is used as an etching mask. The second interlayer insulating layer 70 is etched to form first contact holes C1 and C2 exposing the junction region 40 of the peripheral region P and the upper side portion of the gate 20.

In this case, when the second interlayer insulating layer 70 is etched, the spacer 30 formed on both sidewalls of the gate 20 is lost.

Referring to FIG. 3, after depositing an insulating film for a spacer based on a nitride layer on a second interlayer insulating film 70 including the first contact holes C1 and C2, the insulating film is etched to the entire surface to form the contact hole C1,. C2) Bit line contact spacers 80 having a thickness of 250 to 300 Å are formed on both side walls.

The bit line contact spacers 80 formed on both sidewalls of the first contact holes C1 and C2 complement the spacers 30 lost on both sidewalls of the gate 20. Subsequent short line contact between the bit line contact and the gate 20 can be prevented, thereby improving self alignment contact (SAC).

In other words, the spacer 30 formed on both sidewalls of the gate 20 of the peripheral region P is lost during the etching process of the interlayer insulating layer 70 for forming the bit line contact holes C1 and C2. This increases the possibility of shorting between gate and bitline contacts.

Accordingly, in the present invention, the bit line contact spacer 80 is formed on the surface of the bit line contact contact holes C1 and C2 so that the bit line contact spacer 80 is lost. As a supplementary function of the gate line, the short circuit between the gate 20 and the bit line contact may be prevented when the subsequent bit line contact is formed.

Referring to FIG. 4, after forming the second contact hole C3 defining the bit line contact forming region of the cell region C by etching the second interlayer insulating layer 70, the second interlayer insulating layer 70 is formed. A titanium (TiN) film 90a as a barrier layer 90 on the second interlayer insulating film 70 including a contact hole C3 surface and a bit line contact spacer 80 in the peripheral region P. ) And a titanium nitride (TiN) film 90b are sequentially deposited, and then a bit line contact conductive film is formed on the titanium nitride film 90b so that the first and second contact holes C1, C2, and C3 are buried. A tungsten (W) film 100 is deposited.

As described above, according to the present invention, as the bit line contact spacer 80 is formed on the surfaces of the first contact holes C1 and C2 of the peripheral area P, the short circuit between the bit line contact and the gate is prevented. It can be prevented.

Subsequently, although not illustrated, the conductive layer and the barrier layer are etched to form bit line contacts on the contact hole, and then a series of known subsequent steps are sequentially performed to manufacture a semiconductor device according to an exemplary embodiment of the present invention.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

As described above, the present invention provides a nitride film-based bit line contact spacer on a contact hole surface for a bit line contact that exposes a junction region of a semiconductor substrate and an upper side portion of a gate where a spacer is formed when forming a bit line contact in a peripheral region. By forming, the bit line contact spacer can prevent the short circuit between the gate and the bit line contact.

Therefore, the present invention can prevent the self alignment contact (SAC) fail between the bit line contact and the gate, thereby improving the characteristics of the device.

Claims (6)

A first interlayer dielectric layer having a landing plug contact hole defining a landing plug forming region of the cell region on a semiconductor substrate partitioned into a cell region and a peripheral region and having a gate and a junction region having spacers in each region; Forming a; Forming a landing plug in the landing plug contact hole; Forming a second interlayer insulating film on an entire surface of the substrate including the landing plug; Etching the second interlayer insulating layer until the junction region of the peripheral region and the upper side portion of the gate are exposed to form a first contact hole defining a bit line contact forming region of the peripheral region; Forming a spacer for bit line contacts on both side walls of the first contact hole; Etching the second interlayer insulating layer to form a second contact hole defining a bit line contact forming region in the cell region; Forming a barrier layer on the second interlayer insulating layer including a surface of the second contact hole and a spacer for a bit line contact in the peripheral area; And Forming a conductive film for bit line contact on the barrier film such that the first and second contact holes in which the barrier film is formed are filled; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The bit line contact spacer is formed to a thickness of 250 ~ 300 Å semiconductor device manufacturing method. The method of claim 1, Forming a bit line contact spacer on both side walls of the first contact hole, Forming an insulating film for a spacer on the second interlayer insulating film including the first contact hole; And And etching the entire surface of the insulating film for spacers. The method of claim 3, wherein And the insulating film for spacers is formed of a nitride film. The method of claim 1, The barrier film is a semiconductor device manufacturing method, characterized in that formed by a laminated film of a titanium film and a titanium nitride film. The method of claim 1, And the conductive film is formed of a tungsten film.

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