KR20060095610A - Method of forming landing plug poly of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a landing plug poly of a semiconductor device. According to an aspect of the present invention, there is provided a method of forming a landing plug poly of a semiconductor device, the method including: providing a silicon substrate on which several gates are formed; Depositing a nitride film for a spacer on an entire surface of the substrate to cover the gate; Etching the nitride film for spacers to form nitride film spacers on both sidewalls of the gates, and exposing a substrate portion between the gates; Depositing a polysilicon film to bury a substrate portion between gates on the substrate resultant; CMPing the polysilicon film until the gate is exposed; Forming a mask pattern on the substrate result that exposes a portion of the substrate other than a contact region; Performing a self-aligned contact etching process on the substrate resultant using the mask pattern to remove a polysilicon layer other than a contact region; Depositing an interlayer insulating film on the substrate resultant; And CMP the substrate resultant until the gates are exposed.

Description

Method for forming Landing Plug Poly of semiconductor device

1A to 1D are cross-sectional views of processes for describing a method for forming a landing plug poly of a semiconductor device according to the related art.

2A to 2E are cross-sectional views of processes for describing a method for forming a landing plug poly of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

21: semiconductor substrate 23: gate hard mask

24: gate electrode 27: nitride film for spacer

28: landing plug poly 31: interlayer insulating film

The present invention relates to a method of forming a landing plug poly of a semiconductor device, and more particularly, to a method of forming a landing plug poly of a semiconductor device capable of shortening a process step and reducing a production cost.

As the integration of semiconductor devices proceeds, in order to have more unit cells in a limited space in the manufacture of semiconductor devices, the size of the contact size is also reduced along with the reduction of the substantial area of the unit cells. Accordingly, there is a great difficulty in forming a contact hole for electrically connecting the silicon substrate and the bit line and the silicon substrate and the capacitor, and a self-aligned contact as a technique for solving the problem. SAC) process technology has been proposed.

The SAC technology forms a landing plug contact (hereinafter referred to as LPC) that exposes a portion of a cell region in which a bit line and a capacitor are to be formed, and then connects the contact hole to a landing plug poly for a bit line and a capacitor. LPP) facilitates the electrical connection between the silicon substrate and the bitline and capacitor to be formed subsequently.

1A to 1D are cross-sectional views illustrating a landing plug poly forming process of a conventional semiconductor device.

Referring to FIG. 1A, a gate 4 including a gate oxide film (not shown), a polysilicon film, a tungsten film, and a gate hard mask 3 is formed on a semiconductor substrate 1, and covers the gate 4. The nitride film 7 for spacers is deposited.

Referring to FIG. 1B, a BPSG (Boron Phosphorous Silicate Glass) film 8 is deposited on the entire surface of the substrate, and an annealing process is performed to improve buried characteristics of the BPSG film 8.

Next, the BPSG film 8 is CMP so that the gate hard mask 3 is exposed. Subsequently, after the nitride film 9 for the LPC hard mask is deposited on the resultant, a photosensitive film pattern 10 exposing the region where the LPC is to be formed is formed. Then, the nitride film 9 for LPC hard mask is etched using the photosensitive film pattern 10 to form a pattern.

Referring to FIG. 1C, an LPC 12 is formed by etching portions of an interlayer insulating film between exposed gates using the etched nitride film 9 for an LPC hard mask. Then, in order to prevent the gate hard mask from being damaged in the process of etching the spacer nitride film 7 at the bottom of the LPC, the USG film 11 is deposited by the buffer oxide film.

Referring to FIG. 1D, the USG film 11 and the spacer nitride film are etched back to expose the substrate region between the gates. A polysilicon film is then deposited to embed the LPC on the substrate output. Next, the entire substrate product is CMP until the gate hardmask 3 is exposed to form a landing plug poly 13 between the gates.

However, in order to form the landing plug poly as described above, a number of processes are required. In the present case, since the process takes 15 hours or more to 15 processes or more, process delay and process cost are problematic.

Accordingly, the present invention is to provide a method for forming a landing plug poly of a semiconductor device that can reduce the production steps and reduce the production cost as proposed to solve the conventional problems as described above.

In order to achieve the above object, the present invention comprises the steps of providing a silicon substrate formed with several gates; Depositing a nitride film for a spacer on an entire surface of the substrate to cover the gate; Etching the nitride film for spacers to form nitride film spacers on both sidewalls of the gates, and exposing a substrate portion between the gates; Depositing a polysilicon film to bury a substrate portion between gates on the substrate resultant; CMPing the polysilicon film until the gate is exposed; Forming a mask pattern on the substrate result that exposes a portion of the substrate other than a contact region; Performing a self-aligned contact etching process on the substrate resultant using the mask pattern to remove a polysilicon layer other than a contact region; Depositing an interlayer insulating film on the substrate resultant; And CMPing the substrate resultant until the gates are exposed.

The interlayer insulating layer may be deposited by high density plasma chemical vapor deposition (HDPCVD).

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating processes of forming a landing plug poly in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a gate 24 including a gate oxide film (not shown), a polysilicon film, a tungsten film, and a gate hard mask 23 is formed on the semiconductor substrate 21. Then, a nitride film 27 for spacers is deposited on the resultant to cover the gate 24.

Referring to FIG. 2B, the spacer nitride layer 27 is etched so as to remain only on both sidewalls of the gate 24. At this time, the etching selectivity is adjusted to etch the buffer oxide film (not shown) formed on the silicon substrate together with the spacer nitride film deposited on the bottom portion between the gates 24 to expose the substrate portions between the gates 24. Let's do it.

Referring to FIG. 2C, a polysilicon film is deposited on the substrate resultant to fill a portion of the substrate between the gates. Then, CMP until the gate hard mask 23 is exposed.

Referring to FIG. 2D, a nitride film for an LPC hard mask is deposited on the substrate resultant. Then, on the LPC hard mask nitride film, although not shown in detail, a mask 30 for exposing portions other than the region where the landing plug poly is to be formed is formed on the contrary, and then used for the LPC hard mask. The nitride film 29 is etched.

Next, using the etched nitride film 29 for the LPC hard mask, a polysilicon film other than the contact region, that is, the region where the landing plug poly is to be formed, is etched to selectively remove the landing plug poly 28 only between the gates. Form.

Referring to FIG. 2E, an interlayer insulating layer 31 is deposited on the substrate resultant. The interlayer insulating layer 31 is preferably deposited by high density plasma chemical vapor deposition.

Next, the substrate product is CMP until the gate hard mask 23 is exposed to complete the formation of the landing plug poly according to the present invention.

As described above, the present invention exposes the silicon substrate during etching of the nitride film for the spacer, and then, instead of the interlayer insulating film, first deposits the polysilicon film, removes the polysilicon film other than the contact area, and then deposits the interlayer insulating film. After the LPC is formed, the USG film deposition and etching process are not performed. Therefore, the process step is reduced, resulting in an effect of shortening the process time of about 2.8 hours.

While the invention has been shown and described with reference to certain preferred embodiments, the invention is not so limited, and the invention is not limited to the scope and spirit of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

As described above, since the present invention does not go through the deposition and etching process of the buffer oxide film when the landing plug poly is formed, it is possible to shorten the process step and reduce the production cost. Therefore, the present invention can shorten the process step of the landing plug poly itself, as well as improve the reliability and manufacturing yield of the semiconductor device.

Claims (2)

Providing a silicon substrate having several gates formed thereon; Depositing a nitride film for a spacer on an entire surface of the substrate to cover the gate; Etching the nitride film for spacers to form nitride film spacers on both sidewalls of the gates, and exposing a substrate portion between the gates; Depositing a polysilicon film to bury a substrate portion between gates on the substrate resultant; CMPing the polysilicon film until the gate is exposed; Forming a mask pattern on the substrate result that exposes a portion of the substrate other than a contact region; Performing a self-aligned contact etching process on the substrate resultant using the mask pattern to remove a polysilicon layer other than a contact region; Depositing an interlayer insulating film on the substrate resultant; And And CMP said substrate resultant until said gates are exposed. The method of claim 1, The interlayer dielectric layer is deposited according to a high density plasma chemical vapor deposition (HDPCVD) method having good buried characteristics.

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