KR20080029656A - Gate dielectric and emthod for fabrication of the same - Google Patents

Abstract

A gate dielectric and a method for manufacturing the same are provided to enhance a speed of the gate dielectric and a charge storage time property. A method for manufacturing a gate dielectric comprises forming a tunnel oxide layer(13) on a substrate(11) forming a charge storage layer including a dielectric laminated by interposing at least one layer on the tunnel oxide layer forming an oxide layer on the charge storage layer; and forming a gate conductive layer(18A) on the oxide layer. The charge storage layer is formed of a dielectric layer/conductive layer structure or a dielectric layer/conductive layer/dielectric layer structure. The conductive layer is formed of any one of poly silicon, tungsten, and tungsten silicon layers.

Description

GATE DIELECTRIC AND EMTHOD FOR FABRICATION OF THE SAME

1 shows a typical SONOS device.

2 is a view showing the structure of a gate dielectric according to the first embodiment of the present invention.

3 is a view showing a structure of a gate dielectric according to a second embodiment of the present invention.

4A to 4G illustrate a method of manufacturing a gate dielectric having the structure shown in FIG. 2.

Explanation of symbols on the main parts of the drawings

11 semiconductor substrate 12 device isolation film

13 gate insulating film 14A-18A gate pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a process of forming a gate dielectric during a semiconductor device manufacturing process.

Semiconductor memory devices used to store data can generally be classified as either volatile or non-volatile memory devices. Volatile memory devices lose stored data as power supply is interrupted, while nonvolatile memory devices retain stored data even when power supply is interrupted. Thus, in situations where power is not always available, frequently interrupted, or when low power usage is required, such as in mobile phone systems, memory cards and other applications for storing music and / or video data. Devices are widely used.

In general, cell transistors of a nonvolatile memory device have a stacked gate structure. In the stacked gate structure, for example, a flash element includes a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode sequentially stacked on the channel region of the cell transistor. On the other hand, a nonvolatile memory device having a SONOS (silicon / oxide / nitride / oxide / silicon) structure includes a silicon film (S, silicon substrate) having a channel region therein, an oxide film (O) forming a tunneling layer, and a charge. And a nitride film (N, Si ₃ N ₄ ) for trapping, an oxide film (O, CVD oxide film) used as a shielding layer, and a silicon film (S, polysilicon film) used as a control gate electrode. As a diagram supporting this, FIG. 1 shows a SONOS device.

The difference between the flash device and the SONOS device is that in terms of structure, the flash device stores charge in a floating gate, while the SONOS device stores charge in a nitride film.

In the case of a flash device using polysilicon as a floating gate, if the defect is present in the polysilicon, the retention time of the charge is remarkably decreased, while the nitride film is insensitive to process defects. The SONOS device used is less susceptible to problems like flash devices in terms of the charge storage capability.

In addition, the flash device is limited to low voltage operation and high speed because at least 70 kW of tunnel oxide must be applied to the bottom of the floating gate. However, since the SONOS device applies a direct tunneling oxide under the nitride film, it is possible to implement a low voltage operating and high speed memory device.

However, the SONOS device having such an advantage also has a disadvantage in that it does not store much charge because a trap site is small in the charge storage layer (= nitride film having an insulator property), which serves to store charge. As a result, there is a problem in that the speed for storing or removing electric charges is slowed.

Therefore, there is a need for a material having excellent charge storage capability as a charge storage material in a SONOS device.

The present invention has been proposed to solve the above problems of the prior art, and a first object of the present invention is to provide a gate dielectric having excellent charge storage capability and a method of manufacturing the same.

According to an aspect of the present invention for achieving the above object, a tunnel oxide film formed on a substrate and a charge storage layer comprising a dielectric formed on the tunnel oxide film, laminated via at least one conductive layer A gate dielectric is provided.

And forming a tunnel oxide film on the substrate and forming a charge storage layer including a dielectric stacked on the tunnel oxide film via at least one conductive layer. .

The present invention provides a two-layered film or a first high dielectric constant of a high k dielectric / conductor layer instead of a nitride film having a low charge storage capability used as a charge storage layer in a SONOS device. (k) Three layer films of dielectric film / conductive layer / second high dielectric constant film are used.

Here, it means that the interface between each laminated film becomes a trap site, and the conductive layer plays a role of storing charge.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a view showing the structure of a gate dielectric according to the first embodiment of the present invention.

Referring to FIG. 2, the gate dielectric is formed on the substrate 31 on which the device isolation layer 32 is formed. The tunnel insulating layer 33 / the first high dielectric constant 34, the conductive layer 35, and the second high dielectric constant 36 are formed on the substrate 31. ), The charge blocking film 37 / the gate conductive film 38 is stacked in this order.

Here, the film serving as the charge storage layer is a laminated film of the first high dielectric constant film 34 / the conductive layer 35 / the second high dielectric constant film 36, and each interface thereof is a trap site, and the conductive layer ( 35) stores the charge.

At this time, the first high dielectric constant film 34 and the second high dielectric constant film 36 may be formed of any one of metal-based oxide films—Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X. It is preferable to form one film-or a silicate series-any one of HfSiO _X , ZrSiO _X and LaSiO _{X. X} is a natural number. And, the thickness is formed to 30 ~ 100Å, it is preferable to be formed by CVD (chemical vapor deposition) method or ALD (atomic layer deposition) method.

In addition, the conductive layer 35 is a material other than an insulator such as polysilicon, tungsten (W), and tungsten silicon film (WSi), and has a thickness of 5 to 100 kPa. In addition, the conductive layer 35 is preferably formed by any one of a CVD method, a PECVD method, an ALD method, and a PVD method.

3 is a view showing the structure of a gate dielectric according to a second embodiment of the present invention.

Referring to FIG. 3, the gate dielectric layer includes a tunnel insulating film 53, a high dielectric constant dielectric film 54, a conductive layer 55, a charge blocking film 56 and a gate conductive film on the substrate 51 on which the device isolation film 52 is formed. 57 has a structure in which they are sequentially stacked.

Here, the film serving as the charge storage layer is a laminated film of the high dielectric constant dielectric film 54 / conductive layer 55, and each interface thereof is a trap site, and the conductive layer 55 plays a role of storing charge. .

In this case, the high-k dielectric film 54 is a metal-based oxide film-any one of Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X -or silicate series- It is preferably formed of a film of any one of HfSiO _X , ZrSiO _X and LaSiO _{X. X} is a natural number. And, the thickness is formed to 30 ~ 100Å, it is preferable to be formed by CVD (chemical vapor deposition) method or ALD (atomic layer deposition) method.

In addition, the conductive layer 55 is a material other than an insulator such as polysilicon, tungsten (W), and tungsten silicon film (WSi), and has a thickness of 5 to 100 kPa. In addition, the conductive layer 35 is preferably formed by any one of a CVD method, a PECVD method, an ALD method, and a PVD method.

A method of manufacturing a gate dielectric having such a structure will be described below.

First, a method of manufacturing a gate dielectric having the structure as shown in FIG. 2 is the same as that of FIGS. 4A to 4G.

As shown in FIG. 4A, a tunnel insulation layer 13 is formed on a substrate isolation layer 12 formed by performing a typical shallow trench isolation (STI) process and an ion implantation process such as a well process. Form.

In this case, the tunnel insulating layer 13 may be formed of a SiO ₂ film grown and formed through a thermal oxidation process or a deposition process, or may be formed of a high-k dielectric film having a higher dielectric constant than the SiO ₂ film (dielectric constant = 3.9).

Next, as shown in FIG. 4B, the first high-k dielectric film 14 is formed on the resultant product in which the tunnel insulating film 13 is formed.

In this case, the first high dielectric constant 14 is a metal-based oxide film-any one of Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X -or silicate-based- It is preferable to form the film of any one of HfSiO _X , ZrSiO _X and LaSiO _{X. X} is a natural number. The thickness is preferably 30 to 100 GPa, and is preferably formed by CVD (chemical vapor deposition) or ALD (atomic layer deposition).

Next, as shown in FIG. 4C, the conductive layer 15 is formed on the resultant formed with the first high-k dielectric film 14.

Here, the conductive layer 15 is a material other than an insulator such as polysilicon, tungsten (W), and tungsten silicon film (WSi), and has a thickness of 5 to 100 kPa. In addition, the conductive layer 15 may be formed by any one of a CVD method, a plasma enhanced chemical vapor deposition (PECVD) method, an ALD method, and a physical vapor deposition (PVD) method.

Next, as shown in FIG. 4D, the second high dielectric constant dielectric film 16 is formed on the resultant product on which the conductive layer 15 is formed.

In this case, the second high dielectric constant dielectric film 16 is a metal-based oxide film-any one of Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X -or a silicate series- It is preferable to form the film of any one of HfSiO _X , ZrSiO _X and LaSiO _{X. X} is a natural number. And it is preferable to form in thickness of 30-100 micrometers, and to form by a CVD system or an ALD system.

Next, as shown in FIG. 4E, the charge blocking layer 17 is formed on the resultant formed with the second high-k dielectric layer 16.

The charge blocking layer 17 may be formed of a SiO ₂ film or a high-k dielectric film having a higher dielectric constant than that of the SiO ₂ film (dielectric constant = 3.9). And the thickness is formed in 30-100 kPa.

The charge blocking film 17 isolates the gate conductive film (formed in a subsequent process) and the charge storage layers 14 to 16 that store the charge, thereby preserving stored charges, and generating an electric field from the gate conductive film. It forms a role.

Next, as shown in FIG. 4F, the gate conductive film 18 is formed on the resultant on which the charge blocking film 17 is formed.

Here, the gate conductive film 18 generally uses a polysilicon film.

Next, as illustrated in FIG. 4G, a hard mask (not shown) for gate patterning is formed on the resultant product on which the gate conductive film 18 is formed, and the first mask is formed from the gate conductive film 18 as an etch barrier. The high dielectric constant 14 is etched to form gate patterns 14A to 18A.

Thereafter, impurities are ion implanted into both substrates 11 of the gate patterns 14A to 18A to form source / drain regions (not shown).

Thus, the gate dielectric according to the first embodiment is obtained.

Subsequently, in the method of manufacturing the gate dielectric having the structure as shown in FIG. 3, after the process shown in FIG. 4C, the process of FIG. 4D is omitted and the charge blocking film 17 is formed on the conductive layer 15.

That is, after the tunnel insulating film 13, the high dielectric constant film 14, the conductive layer 15, the charge blocking film 17 and the gate conductive film 18 are sequentially stacked on the substrate 11, a gate pattern process is performed. To obtain the gate dielectric according to the second embodiment.

In the present invention, the laminated film used as the charge storage layer (first high-k dielectric film / conductive layer / second high-k dielectric film or high-k dielectric film / conductive layer) is characterized in that each layer forms an interface to form a trap site. Trap sites in each dielectric film and conductive layer are also included. In this case, the interface of each layer is represented as a representative because the trap site is the strongest, and the conductive layer serves to store the charge so that the threshold voltage (Vth) window of program and erase is established. There is an advantage that can be increased.

That is, since the space for storing the charge is formed as compared to the nitride film as the conventional charge storage layer, the ability to store the charge is high, and the time for storing and removing the charge is shortened, thereby improving the speed of the device. .

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention obtains a gate dielectric having excellent charge storage capability by applying the above-described two-layer or three-layer film as a charge storage layer.

Therefore, it is possible to improve characteristics related to reliability, such as speed improvement and charge storage time characteristics of the gate dielectric.

Claims (12)

A tunnel oxide film formed on the substrate; And A charge storage layer formed on the tunnel oxide film and including a dielectric stacked over at least one conductive layer. Gate dielectric comprising a. The method of claim 1, An oxide film formed on the charge storage layer; And A gate conductive film formed on the oxide film A gate dielectric further comprising. The method of claim 1, And the charge storage layer has a dielectric film / conductive layer structure or a dielectric film / conductive layer / dielectric film structure. The method of claim 3, The dielectric film is a metal-based oxide film having a high dielectric constant-any one of Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X -or a silicate series—HfSiO _X , ZrSiO _X And LaSiO _X , wherein the film is a gate dielectric. The method of claim 4, wherein The thickness of the dielectric film is a gate dielectric, characterized in that 30 ~ 100Å. The method of claim 3, The conductive layer is formed of any one of polysilicon, tungsten (W) and tungsten silicon film (WSi), the thickness of the gate dielectric, characterized in that 5 ~ 100Å. Forming a tunnel oxide film on the substrate; And Forming a charge storage layer on the tunnel oxide layer, the charge storage layer including a dielectric stacked through at least one conductive layer; Method of manufacturing a gate dielectric comprising a. The method of claim 7, wherein Forming an oxide film on the charge storage layer; And Forming a gate conductive film on the oxide film Method of manufacturing a gate dielectric further comprising. The method of claim 7, wherein The charge storage layer is formed of a dielectric film / conductive layer structure or a dielectric film / conductive layer / dielectric film structure method of manufacturing a gate dielectric. The method of claim 9, The dielectric film is a metal-based oxide film having a high dielectric constant-any one of Si ₃ N ₄ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O _3, and LaO _X -or a silicate series—HfSiO _X , ZrSiO _X And LaSiO _X , which is a film, the method for producing a gate dielectric. The method of claim 10, The dielectric film is a method of manufacturing a gate dielectric, characterized in that formed to a thickness of 30 ~ 100Å. The method of claim 9, The conductive layer is formed of any one of polysilicon, tungsten (W) and tungsten silicon film (WSi), the method of manufacturing a gate dielectric, characterized in that formed in a thickness of 5 ~ 100Å.

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