KR20080029101A - Printed circuit board and manufacturing method thereof - Google Patents

Abstract

A PCB(Printed Circuit Board) and a manufacturing method thereof are provided to reduce an etching amount due to permeation of a plating solution into an interface between a sliver core substrate and a copper plating layer. A manufacturing method of a PCB includes the steps of: laminating a plating resist on a core substrate with a metal layer on a surface and selectively etching a part of the plating resist in correspondence to a circuit pattern(S20); applying power to the metal layer to selectively deposit a first plating layer on the metal layer to correspond to the circuit pattern(S30); and applying power to the metal layer to deposit a second plating layer on the first plating layer to correspond to the circuit pattern(S40).

Description

Printed circuit board and manufacturing method thereof

1 is a flow chart showing a method of manufacturing a printed circuit board according to an embodiment of the present invention.

2 is a flowchart illustrating a manufacturing process of a printed circuit board according to an exemplary embodiment of the present invention.

Figure 3a is a flow chart showing a manufacturing process of a printed circuit board according to another embodiment of the present invention.

Figure 3b is a flow chart showing a manufacturing process of a printed circuit board according to another embodiment of the present invention.

Figure 4a is a photograph of the surface of the DC plating layer according to an embodiment of the present invention.

Figure 4b is a photograph of the surface of the pulse plating layer according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: core substrate 102: metal layer

104: plating resist 106: DC plating layer

108: pulse plated layer

The present invention relates to a printed circuit board and a method of manufacturing the same.

A method of forming a circuit pattern on the surface of a printed circuit board, comprising a thin electroless copper plating on a core board and laminating a photosensitive resist thereon, and then exposing and developing a portion of the resist selectively to correspond to the circuit pattern. After the electroplating of the portion where the circuit pattern is to be formed, a so-called 'additive' method of removing the resist and the electroless copper plating layer is applied.

Here, as a plating method for electroplating, a pulse plating method using an AC power supply and a DC plating method using a DC power supply are used. In the case of the pulse plating method, the growth rate of the plating layer is fast but the crystal structure of copper is large, whereas the DC plating method is characterized in that the growth rate of the plating layer is slow but the crystal structure is fine.

In the case of electroplating by the pulse plating method, the precipitated crystal structure is large. If the grain boundary between the crystal and the crystal is etched by acid in a later step, the surface becomes rough and uneven, and the unevenness of the solder resist Residual residue or poor surface flatness may eventually lead to poor bonding of flip chips. In addition, since the plating layer by the pulse plating method is more easily etched by acid, undercut may occur under the circuit during the formation of the microcircuit, which causes a problem in forming the microcircuit.

On the other hand, when the circuit is formed by the DC plating method, rough surface irregularities and undercuts of the circuit, which have been a problem in the pulse plating method, are less likely to occur.However, the thickness variation of the copper plating is larger than that of the pulse plating method, and the growth rate of the plating layer is slower. There is a problem that the productivity is lower.

The present invention provides a printed circuit board and a method of manufacturing the same, which can increase the surface flatness of the substrate, reduce the occurrence of undercut under the circuit, reduce the thickness variation of copper plating, and increase the growth rate of the plating layer.

According to an aspect of the present invention, (a) laminating a plating resist on a core substrate having a metal layer laminated on its surface, and selectively removing a portion thereof in accordance with a circuit pattern, (b) applying power to the metal layer And selectively depositing a first plating layer on the metal layer to correspond to the circuit pattern, and (c) depositing a second plating layer on the first plating layer to correspond to the circuit pattern by applying power to the metal layer. A method is provided.

More specifically, a portion of the plating resist is raised on the core substrate, and the first plating layer is selectively grown. The second plating layer corresponding to the first plating layer may be selectively grown.

Prior to step (a), a thin electroless copper plating may be deposited on the core substrate to deposit a metal layer, and the plating resist may include a dry film which is a photosensitive resist, and step (a) may selectively remove the dry film by exposing and developing the film. It may include the step.

After step (c), power is applied to the metal layer (c1), the third plating layer is deposited on the second plating layer to correspond to the circuit pattern by the same plating method as in step (b), and the plating resist and the corresponding metal layer are deposited. It may include the step of removing.

When step (b) is performed by the direct current plating method, step (c) is performed by the pulse plating method, which has a small grain boundary and strong acid resistance, so that the etching amount due to the penetration of the plating solution between the core substrate and the electroplating interface is obtained. Can be greatly reduced. Therefore, by depositing the first plating layer in contact with the core substrate by the direct current plating method, it is possible to reduce the amount of etching of the problematic portions by etching with acid, and the second plating layer has a large grain boundary, rapid plating growth, and pattern followability. This is preferable, and it is preferable to deposit by the pulse plating method with a small plating imbalance.

If step (b) is performed by the pulse plating method, step (c) may be performed by the direct current plating method. As the second plating layer is performed by the direct current plating method, the surface of the mounting pad can be formed into a good copper surface. In the case of the DC plating method, it can be carried out under a current density condition of 1.5 A / cm ² to 2.0 A / cm ² and a voltage condition of 2V to 3V.

In addition, according to another aspect of the present invention, the core substrate, the metal layer laminated on the surface of the core substrate, the first plating layer selectively laminated on the metal layer corresponding to the circuit pattern and the first layer laminated on the first plating layer corresponding to the circuit pattern There is provided a printed circuit board comprising a two plating layer.

It may further include a third plating layer laminated on the second plating layer corresponding to the circuit pattern, the third plating layer is preferably deposited by the same plating method as the first plating layer. In addition, the first plating layer may be deposited by direct current plating, and the second plating layer may be deposited by pulse plating.

Other aspects, features, and advantages other than the foregoing will be apparent from the following detailed description of the invention including the drawings and the claims.

Hereinafter, a preferred embodiment of a printed circuit board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

1 is a flowchart illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.

In this embodiment, DC plating, pulse plating, and DC plating are sequentially performed on the core substrate on which the metal layer is laminated, thereby increasing the surface flatness of the substrate, reducing the occurrence of undercut at the bottom of the circuit, reducing the thickness variation of copper plating, and the growth rate of the plating layer. It is characterized by increasing the productivity.

To this end, first, electroless copper plating is performed on the core substrate to stack a metal layer (S10) to enable electrical conduction. The electroless copper plating layer is thinly laminated by chemical plating, and is a plating method for imparting conductivity to the surface of an insulator such as resin, ceramic, glass, or the like.

 The plating resist is laminated on the core substrate on which the metal layer is laminated by electroless copper plating, and a part of the plating resist is selectively removed according to the circuit pattern (S20), thereby placing a predetermined portion of the plating resist on the core substrate. At this time, the plating resist includes a dry film, which is a photosensitive resist, and the photosensitive resist reacts to light by exposing the dry film to irradiate ultraviolet rays, and by performing a developing process, leaving a hardened portion exposed to ultraviolet rays. The other portions can be dissolved to selectively remove the plating resist corresponding to the circuit pattern.

The power is applied to the metal layer to selectively deposit the first plating layer on the portion where the electroplating starts, for example, 1 μm to 3 μm, to correspond to the circuit pattern (S30). Here, the "selectively" depositing means depositing the electroplating layer only on a portion of the entire surface of the electroless plating layer, that is, a part of the electroless plating layer.

Power is applied to the first plating layer metal layer to deposit a second plating layer on the first plating layer to correspond to the circuit pattern (S40). At this time, for example, when the first plating layer is laminated by the DC plating method, the second plating layer may be laminated by the pulse plating method. On the other hand, when the first plating layer is laminated by the pulse plating method, the second plating layer may be laminated by the DC plating method.

Looking at the case where the first plating layer is performed by the DC plating method and the second plating layer is performed by the pulse plating method, the DC plating method has a small grain boundary and strong acid resistance, so that the etching amount due to the penetration of the plating solution between the core substrate and the electroplating interface is strong. Can be greatly reduced.

More specifically, when the first plating layer in contact with the core substrate is deposited by the direct current plating method, the deposited direct current plated layer has a small grain boundary and a small erosion by acid. Therefore, the direct current plating method can greatly reduce the etching amount due to the penetration of the plating liquid between the core substrate and the copper plating interface, which is a problem during soft etching by the blackening treatment in the subsequent step and coordination of the copper surface of sulfuric acid fruit water.

Further, by forming the second plating layer by the pulse plating method, it is possible to form a pulse plating layer having a large grain boundary, a fast plating growth, and a pattern followability in which the plating layer grows along the circuit pattern, and having a small imbalance in plating.

On the other hand, when the first plating layer is performed by the pulse plating method and the second plating layer is performed by the direct current plating method, the grain boundary is large, the plating growth is fast, and the pattern followability is good. The pulsed plating layer having a feature of small plating imbalance can be formed as the first plating layer. In addition, by forming the DC plating layer on the circuit surface portion, the smoothness of the circuit surface can be improved by utilizing the property that the grain boundary of the DC plating is small.

In addition, as the second plating layer is deposited by the direct current plating method, the etching amount can be controlled during the etching process of removing the plating resist and the corresponding metal layer, so that the undercut that has been a problem by etching with acid is problematic. The etching amount of the portion can be greatly reduced.

The pulse plating method is an electroplating method performed using a current having a pulse waveform, that is, an AC power supply. In addition, the pulse plating method has good physical properties of the deposit, that is, porosity, ductility, hardness, electrical conductivity, abrasion resistance, and the like, and the plating layer thickness distribution due to the polarity which is periodically reversed is improved.

In contrast to electroplating such as electroless plating, electroplating can control the reaction speed of a system by manipulating a given current density, and easily select the amount of reaction driving force by adjusting the electrode potential. Current waveforms used in electroplating include negative pulses represented by periods without current or positive pulses, direct current with superimposed modulation, and continuous negative pulses by continuous positive and negative pulses, 'galvanostatic' or 'potentiostatic' pulses. , Pulses of square or modulated sine wave.

Meanwhile, by applying power to the metal layer, the third plating layer may be further deposited on the second plating layer to correspond to the circuit pattern (S50). Here, when the first plating layer is formed by the DC plating method, it is preferable that the second plating layer is formed by the pulse plating method, and the third plating layer is formed by the DC plating method again. Therefore, the interface portion between the core substrate and the electrolytic copper plating layer is formed by the direct current plating method, the middle part is formed by the pulse plating method, and the circuit surface part of the finish forms the plating layer by the direct current plating method to form a circuit having a desired thickness. Can be. For example, when forming a circuit having a thickness of 20 μm, the first 1 to 3 μm is formed by direct current plating, the intermediate 14 to 18 μm is formed by pulse plating, and the remaining 1 to 3 μm is formed by direct current plating. Can be.

More specifically, by performing direct current plating on the interface portion between the core substrate and the electroplating layer, the etching amount of the interface between the core substrate and the electroplating layer may be reduced, for example, 1.9 μm to 2.3 μm. In addition, the intermediate portion has good pattern followability, which is a degree of growth of the plating layer along the circuit pattern, and performs pulse plating with small unbalance of plating, and the circuit surface can be plated again by direct current plating to flatten the surface.

The DC plating method and the pulse plating method may be performed at a current density condition of 1.5 A / cm ² to 2.0 A / cm ² and a voltage condition of 2V to 3V, and the pulse plating method is performed at 20 msec: 1.2 msec to 30 msec: positive and negative electrodes: A time ratio of 1.5 msec, the anode and the cathode can be performed at a current ratio of 2.5: 1. However, the embodiment is not limited to this numerical range.

In addition, the DC plating layer is characterized in that the grain size is small, for example, it can be less than 1 ㎛, the planar growth, the crystal is dense and the hardness is weak, while the pulse plated layer is characterized in that the grain size is large For example, it can be 4 micrometers-6 micrometers, it grows in columnar shape, and has a rough crystal and strong hardness.

Finally, the plating resist selectively stacked on the core substrate on which the first plating layer to the third plating layer is deposited so as to correspond to the circuit pattern, and the metal layer at the position where the plating resist is stacked are removed to leave only the circuit pattern (S60). As a result, a circuit pattern of the printed circuit board according to the present embodiment is formed.

2 is a flowchart illustrating a manufacturing process of a printed circuit board according to an exemplary embodiment of the present invention. Referring to FIG. 2, a core substrate 100, a metal layer 102, a plating resist 104, a direct current plating layer 106, and a pulse plating layer 108 are illustrated.

As shown in FIG. 2 (a), the electroplating copper plating is used to deposit the plating resist 104 on the core substrate 100 having the metal layer 102 laminated thereon, as shown in FIG. 2 and selectively remove a part of the plating resist 104 in accordance with the circuit pattern, as shown in FIG. More specifically, the plating resist 104 includes a dry film, by irradiating the dry film with ultraviolet rays, thereby causing the photosensitive resist to respond to light as the dry film is subjected to the exposure process, and also by performing the developing process. After the exposure to ultraviolet light, the hardened part is left, and the other part is dissolved to selectively remove the plating resist corresponding to the circuit pattern.

Next, power is applied to the metal layer 102, and the DC plating layer 106 is selectively deposited on the metal layer 102 to correspond to the circuit pattern by using the DC plating method. More specifically, by applying power to the metal layer 102, to selectively correspond to the circuit pattern, the DC plating layer 106 selectively at the portion where the DC plating starts, for example, 1 ㎛ to 3 ㎛ Deposit. Here, the "selective" deposition means that the direct current plating layer 106 is deposited only on a portion of the entire surface of the electroless plating layer, that is, a part of the electroless plating layer.

The DC plating layer 106 is characterized in that the size of the grain boundary is small, for example, smaller than 1 ㎛, there is a characteristic that the crystal grows planar, dense and weak hardness. In addition, since the DC plating layer 106 has strong acid resistance, the amount of etching due to the penetration of the plating liquid into the interface portion of the electrolytic copper plating layer in contact with the core substrate 100, that is, the interface portion of the DC plating layer 106 may be greatly reduced.

More specifically, when the DC plating layer 106 is deposited on the core substrate 100, since the DC plating layer 106 has a small grain boundary and small erosion by acid, soft etching or sulfuric acid by the blackening treatment of the subsequent step is performed. The etching amount due to the penetration of the plating liquid between the core substrate 100 and the copper plating layer interface portion, which is a problem when coordinating the fruit surface, can be reduced.

As shown in (d) of FIG. 2, a pulse plating layer 108 is deposited on the DC plating layer 106 so as to correspond to a circuit pattern by applying power to the metal layer 102, and the pulse plating layer 108 corresponding to the DC plating layer 106. ) May grow selectively. In addition, the pulse plating layer 108 is preferably deposited to correspond to the circuit pattern by applying power to the metal layer as in the deposition process of the DC plating layer.

In the pulse plating method, as described above, the pattern followability, which is the extent to which the plating layer grows, is good, and because the plating imbalance is small, it is preferable to be plated in the middle part of the entire plating layer. In addition, the plating deviation problem does not occur, it is possible to increase the productivity.

In FIG. 2E, power is applied to the metal layer 102 to deposit the DC plating layer 106 on the pulse plating layer 108 to correspond to the circuit pattern.

Therefore, the core substrate 100 and the electrolytic copper plating layer interface portion are formed by the direct current plating method, the middle part is formed by the pulse plating method, and the circuit surface part of the finish is formed again by the direct current plating method to form a plating layer of desired thickness. A circuit can be formed. For example, when forming a circuit having a thickness of 20 μm, the first 1 to 3 μm is formed by direct current plating, the intermediate 14 to 18 μm is formed by pulse plating, and the remaining 1 to 3 μm is formed by direct current plating. Can be.

Next, as shown in Figs. 2F and 2G, the plating resist 104 and the metal layer 102 at the position are removed to complete the present preferred embodiment.

On the other hand, in the present embodiment, the electroplating is performed on the core substrate 100 in the order of DC plating method, pulse plating method and DC plating method. Accordingly, by forming the first plating layer on the core substrate 100 using the DC plating method, the etching amount due to the penetration of the plating liquid between the core substrate 100 and the electrolytic plating layer interface portion is obtained by using the property of the crystal grain boundary of the DC plating being small. The second plating layer, which is the middle portion, can be reduced, and the pattern followability, which is the extent to which the plating layer is grown, is formed by a pulse plating method with a small plating imbalance, and the productivity can be increased, and the third plating layer is used as a circuit surface portion of the finish. In addition, since the plating layer is formed by the DC plating method, irregularities of the circuit surface portion can be prevented and a flat surface can be realized according to the characteristics of the DC plating layer.

3A is a flowchart illustrating a manufacturing process of a printed circuit board according to another exemplary embodiment of the present invention, and FIG. 3B is a flowchart illustrating a manufacturing process of a printed circuit board according to another exemplary embodiment of the present invention.

3A and 3B, a core substrate 100, a metal layer 102, a plating resist 104, a DC plating layer 106, and a pulse plating layer 108 are illustrated.

The present embodiment differs from the embodiment shown in FIG. 2 in the order in which the electroplating layer is deposited and the number of the electroplating layers to be deposited. The description will be omitted.

Referring to FIG. 3A (d), the electroplating layer is a DC plating layer 106 and a pulse plating layer on the core substrate 100 on which the metal layer 102 is stacked and the plating resist 104 is selectively grown to correspond to the circuit pattern. In the order of 108, two layers of electroplating layers are formed.

Therefore, in the present embodiment, the electroplating layer corresponding to the core substrate 100 is formed by direct current plating, and thus, due to the penetration of the plating solution between the core substrate 100 and the electroplating layer interface part using a small grain boundary of the direct current plating. Since the etching amount can be reduced and the etching amount of the pulse plating layer 108 deposited on the DC plating layer 106 can also be reduced, the uneven state of the pulse plating layer 108 of the circuit surface portion can be partially prevented. .

Referring to (d) of FIG. 3B, the electroplating layer is a pulse plating layer 108 and a direct current plating layer on the core substrate 100 on which the metal layer 102 is stacked and the plating resist 104 is selectively grown to correspond to the circuit pattern. In the order of 106).

In this embodiment, a pulse plating layer is formed on a portion corresponding to the core substrate 100, and a DC plating layer 106 is formed on a portion of the circuit surface on which the components of the substrate are mounted. The plating growth rate is achieved by the pulse plating layer 108. Because of the large size, the productivity of the substrate can be increased, and the plating deviation can be reduced. In addition, the circuit surface is electroplated by a direct current plating method having a small grain boundary, so that smoothness of the circuit surface on which the component is mounted can be obtained.

Figure 4a is a photograph of the surface of the DC plating layer according to a preferred embodiment of the present invention, Figure 4b is a photograph of the surface of the pulse plating layer according to a preferred embodiment of the present invention.

Referring to the photograph shown, as shown in the photograph of the surface of the DC plating layer of FIG. 4A, since the grain size is small and the grain boundaries are small, the DC plating layer is mounted. When deposited on the circuit surface, it has the advantage of flattening the copper surface and not causing unevenness.

In addition, as can be seen from the photograph of the surface of the pulsed plating layer of FIG. 4B, since the grain size is large and the grain boundary is large, the growth rate of the plating layer is large and the plating deviation is small, thereby increasing the productivity of the plating layer. have.

Many embodiments other than those described above are within the scope of the present invention.

As described above, the method of manufacturing the printed circuit board according to the preferred embodiment of the present invention can greatly reduce the etching amount due to the penetration of the plating liquid between the core substrate and the copper plating layer interface portion, and can smoothly implement the circuit surface on which the component is mounted. In addition, it is possible to improve the productivity of the substrate by solving the plating deviation problem.

Claims (11)

(a) laminating a plating resist on a core substrate having a metal layer laminated on the surface thereof, and selectively removing a portion thereof in accordance with a circuit pattern; (b) applying power to the metal layer to selectively deposit a first plating layer on the metal layer to correspond to the circuit pattern; And (c) depositing a second plating layer on the first plating layer to correspond to the circuit pattern by applying power to the metal layer. The method of claim 1, Before the step (a), further comprising the step of laminating the metal layer by electroless copper plating on the core substrate. The method of claim 1, The plating resist includes a dry film, and the step (a) includes exposing and developing the dry film to selectively remove the printed circuit board. The method of claim 1, After step (c), and (c1) applying a power to the metal layer, and depositing a third plating layer on the second plating layer so as to correspond to the circuit pattern by the same plating method as in the step (b). The method of claim 1, After the step (c), further comprising the step of removing the plating resist and the corresponding metal layer. The method of claim 1, The step (b) is performed by a direct current plating method, and the step (c) is performed by a pulse plating method. The method of claim 6, The DC plating method is a method of manufacturing a printed circuit board, characterized in that performed at a current density condition of 1.5 A / cm 2 to 2.0 A / cm 2 and a voltage condition of 2V to 3V. A core substrate; A metal layer laminated on the surface of the core substrate; A first plating layer selectively stacked on the metal layer corresponding to the circuit pattern; And A printed circuit board comprising a second plating layer laminated on the first plating layer corresponding to the circuit pattern. The method of claim 8, The printed circuit board further comprises a third plating layer laminated on the second plating layer corresponding to the circuit pattern. The method of claim 9, The third plating layer is a printed circuit board, characterized in that deposited by the same plating method as the first plating layer. The method of claim 8, The first plating layer is deposited by a direct current plating method, the second plating layer is a printed circuit board, characterized in that deposited by the pulse plating method.

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