KR20080027979A - Dual port memory device having dual memory interface, memory device and method of operating the dual port memory device - Google Patents

Abstract

A dual port memory device having dual memory interface, a memory device and a method of operating the dual port memory device are provided to connect processors with different memory interfaces selectively. A dual port memory device(100) includes a memory array(160), a dual interface part(180) and a first memory interface part. The dual interface part accesses the memory array according to first type memory interface or accesses the memory array according to second type memory interface on the basis of a control signal and an address inputted through a first port in response to a selection signal. The first memory interface part accesses the memory array through the second type memory interface on the basis of a control signal and an address inputted through a second port.

Description

TECHNICAL FIELD [0001] The present invention relates to a dual port memory device having a dual memory interface, a memory device, and a dual port memory device having a dual memory interface. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

1 is a conceptual diagram illustrating a dual-port memory device used in a processor A having a conventional SDRAM External Bus Interface (EBI) and a processor B having an SDRAM external bus interface (EBI).

2 is a conceptual diagram showing a dual-port memory device used in a processor A having a conventional SRAM external bus interface (EBI) and a processor B having an SRAM external bus interface (EBI).

3 is a block diagram illustrating a dual port SDRAM according to an embodiment of the present invention connected to a processor having a PSRAM external interface bus and a processor having an SDRAM external interface bus.

4 is a block diagram illustrating a dual port SDRAM according to an embodiment of the present invention connected to two processors having an SDRAM external interface bus.

Fig. 5 is a block diagram showing the first selector of Fig. 3 or Fig.

FIG. 6 is a block diagram illustrating a PSRAM interface and an SDRAM interface of FIG. 3 according to an embodiment of the present invention.

FIG. 7 is a block diagram illustrating a PSRAM interface and an SDRAM interface of FIG. 3 according to another embodiment of the present invention.

FIG. 8 is a block diagram showing the second selector of FIG. 3 and FIG. 4. FIG.

9 is a block diagram showing the configuration of a first selector when a PSRAM interface unit and a second SDRAM interface unit share one input / output buffer as shown in FIG.

10 is a block diagram showing the configuration of a second selection unit in a case where one PSRAM interface unit and a second SDRAM interface unit share one input / output buffer as shown in FIG.

11 is a timing chart showing a read and write operation when the dual port SDRAM operates in the SDRAM mode according to an embodiment of the present invention.

FIG. 12 is a timing chart showing a read and write operation when the dual port SDRAM according to an embodiment of the present invention operates in the PSRAM mode.

Description of the Related Art

100: Dual port memory device 110:

120: interface unit 130: PSRAM interface unit

140: second SDRAM interface unit 150: second selection unit

160: DRAM memory array 170: first SDRAM interface

180: Dual interface part

The present invention relates to a dual port memory device, and more particularly, to a dual port memory device, a memory device, and a dual port memory device having a dual memory interface applicable to a portable terminal.

Various processors, such as a baseband processor, a video processor, and a multimedia processor, used in portable terminals such as mobile phones, have an SRAM external interface (or PSRAM external interface) and an SDRAM external interface.

Dual-port memories are often used in processors having SRAM external interface (or PSRAM external interface) and SDRAM external interface.

The dual port memory has two input / output ports. In the first processor, data is accessed through the first port. In the second processor, data is accessed through the second port. Thus, Is possible.

In the case of using a dual port memory, data is transferred from the host computer to the host computer via the host processor interface, The transmission speed is faster and the performance of the entire system can be improved. Also, if a dual port memory is used, there is an effect that one memory can be reduced in terms of the mounting area.

1 and 2 are conceptual diagrams illustrating a dual port memory used in two processors accessing a memory having the same kind of memory cell structure. Specifically, FIG. 1 is a conceptual diagram showing a dual-port memory used in a processor A having a conventional SDRAM external bus interface (EBI) and a processor B having an SDRAM external bus interface (EBI) Is a conceptual diagram showing a dual-port memory used in a processor A having an SRAM external bus interface (EBI) and a processor B having an SRAM external bus interface (EBI). Here, the external bus interface (EBI) acts as a kind of memory controller.

As shown in FIGS. 1 and 2, a dual port memory having two ports can be used for two processors accessing a memory having the same kind of memory cell structure. That is, in the case of FIG. 1, a dual-port memory having a memory cell array made up of DRAMs can be connected to two processors having an SDRAM external bus interface (EBI). In the case of FIG. 2, a dual-port memory in which the memory cell array is composed of SRAM can be used in connection with two processors having an SRAM external bus interface (EBI).

However, because the unit memory cell structure differs between the two processors having the external bus interface (EBI) for different kinds of memories, it is difficult to use the dual port memory.

A static random access memory (SRAM) is a volatile memory in which data is extinguished when the power is turned off, and data stored in the memory cell is retained while power is present, even though reflesh is not performed. The unit memory cell of the SRAM generally has a structure consisting of four transistors having a latch structure and two transistors having a transfer gate structure, six transistors in total. Since the data is stored in the unit memory cell of the latch structure, the refresh operation for saving the data is not required.

SDRAM (Synchronous Dynamic RAM) is a volatile memory that periodically refreshes data to store data by periodically charging the capacitor, and has a unit memory cell structure of a DRAM of one transistor and one capacitor.

The PSRAM (Pseudo SRAM) uses the same interface as the SRAM, but the unit memory cell structure has a unit memory cell structure of the DRAM and incorporates a refresh circuit.

It is difficult to form both the SRAM memory cells and the DRAM memory cells having different memory cell structures in the memory cell array region on the dual port memory due to many limitations in the semiconductor memory manufacturing process.

That is, when the processor A has the SRAM external bus interface (EBI) and the processor B has the SDRAM external bus interface (EBI), the SRAM memory cell and the DRAM memory cell are fabricated in the memory cell array area Is difficult due to many limitations in the semiconductor memory fabrication process.

In addition, when the SRAM memory cells and the DRAM memory cells are formed in the memory cell array region on the dual port memory, the SRAM memory cells are formed of six transistors and the die size is increased, It is difficult to integrate.

Therefore, it is general to implement a dual-port memory array using only one type of SRAM or DRAM memory cell structure. In this case, it is more efficient in terms of the layout area required to use the DRAM than to use the SRAM as the memory array of the dual port memory.

In a portable terminal such as a cellular phone, a dual port memory that can be used for both SRAM external interface (or PSRAM external interface) and processors having SDRAM external interface is required.

A conventional dual port memory accesses data with a processor having an SDRAM external interface as the first port and a processor with a SDRAM external interface or a processor with a PSRAM external interface as the second port accesses data The memory interface logic was fixed.

Therefore, the conventional dual port memory, which is connected to the processor having the SDRAM external interface as the first port and connected to the processor having the SDRAM external interface as the second port, has a PSRAM (or SRAM) external I could not connect it to a processor with an interface.

That is, the conventional dual-port memory has a disadvantage that it can not be used by being connected to a processor having an SDRAM external interface selectively or by connecting it to a processor having an external interface of PSRAM (or SRAM).

Accordingly, when more and more processors are used in a single portable terminal, there is a disadvantage that the application range is limited because there is a limit to the available processors by connecting to the conventional dual port memory.

Accordingly, it is a first object of the present invention to provide a dual port memory device having a dual memory interface that can be selectively connected to a processor having different types of memory interfaces.

A second object of the present invention is to provide a memory device having a dual memory interface which can be selectively used in connection with a processor having different kinds of memory interfaces.

A third object of the present invention is to provide a method of operating a dual port memory having a dual memory interface which can be selectively connected to a processor having different types of memory interfaces.

According to an aspect of the present invention, there is provided a dual port memory device including: a memory array; A dual interface for accessing the memory array according to a first mode memory interface or for accessing the memory array according to the second mode memory interface based on an address and a control signal input via a first port in response to a selection signal; And a first memory interface unit for accessing the memory array through the second mode memory interface based on an address and a control signal input through a second port.

Wherein the dual interface provides an address and a control signal input via the first port in response to the selection signal to a first path accessing the memory array according to the first mode memory interface, To a second path accessing the memory array according to the first path; Based on an address and a control signal provided through the first path, an address and data for accessing the memory array in accordance with a first mode memory interface or outputting an address and data for accessing the memory array based on an address and a control signal provided through the second path, An interface for outputting an address and data for accessing the memory array according to the second mode memory interface; And an address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface and a control signal in response to the selection signal And a second selection unit.

The interface unit includes: a first-type memory interface unit for outputting an address and data for accessing the memory array according to the first-type memory interface, based on an address and a control signal provided through the first path; And a second mode memory interface unit for outputting an address and data for accessing the memory array according to the second mode memory interface based on the address and control signal provided through the second path.

Wherein the interface unit comprises: an input / output buffer connected between the first selector and the second selector for buffering data to be accessed by the memory array; Buffering data to be accessed to the memory array in the input / output buffer according to the first mode memory interface based on an address and a control signal provided through the first path, and decoding the address provided through the first path A first memory interface unit for outputting the first memory interface; And buffering data to be accessed to the memory array in the input / output buffer according to the second mode memory interface based on an address and a control signal provided through the second path, and decoding the address provided through the second path And outputting the second mode memory interface unit.

The first selector may include a plurality of demuxes for de-muxing the address and control signals input through the first port in response to the selection signal.

The second selector includes a mux for mobilizing an address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface in response to the select signal can do. The first type memory interface may be a PSRAM interface. The second manner memory interface may be an SDRAM interface, and the memory array may have a DRAM cell structure.

According to an aspect of the present invention, there is provided a memory device including: a memory array; And a dual interface unit for accessing the memory array in accordance with the first mode memory interface or for accessing the memory array in accordance with the second mode memory interface based on the address and control signals input via the first port in response to the select signal .

Wherein the dual interface provides an address and control signal input via the first port in response to the selection signal to a first path accessing the memory array according to the first mode memory interface, To a second path accessing the memory array according to the first path; Based on an address and a control signal provided through the first path, an address and data for accessing the memory array in accordance with a first mode memory interface or outputting an address and data for accessing the memory array based on an address and a control signal provided through the second path, An interface for outputting an address and data for accessing the memory array according to the second mode memory interface; And an address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface in response to the selection signal And a second selector.

According to an aspect of the present invention, there is provided a method for operating a dual port memory device, comprising: Accessing the memory array along an interface and accessing the memory array according to a second mode memory interface based on the address and control signals input via the first port while the select signal is active .

The method of operating the dual port memory device may further include accessing the memory array in accordance with the second mode memory interface based on the address and control signals input via the second port.

The dual port memory device operating method provides an address and a control signal input through the first port to the first path accessing the memory array according to the first mode memory interface while the selection signal is inactive And providing the memory array with a second path accessing the memory array according to the second mode memory interface while the select signal is in the active state.

Accessing the memory array in accordance with the first-type memory interface based on the address and control signal input through the first port while the selection signal is inactive is performed in response to an address and a control signal provided through the first path And outputting an address and data for accessing the memory array according to the first mode memory interface based on the first mode memory interface.

Accessing the memory array in accordance with the second mode memory interface based on the address and control signal input through the first port while the selection signal is in an active state may include accessing the address and control signal provided through the second path And outputting an address and data for accessing the memory array in accordance with the second mode memory interface.

The method of operating the dual port memory device may further comprise the steps of receiving an address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface, And selecting one address.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be interpreted that there is no other element in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In describing the drawings, like reference numerals have been used for like elements.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals will be used for the same constituent elements in the drawings, and redundant explanations for the same constituent elements will be omitted.

3 is a block diagram illustrating a dual port SDRAM according to an embodiment of the present invention connected to a processor having a PSRAM external interface bus and a processor having an SDRAM external interface bus. 4 is a block diagram illustrating a dual port SDRAM according to an embodiment of the present invention connected to two processors having an SDRAM external interface bus.

FIG. 5 is a block diagram illustrating the first selector of FIG. 3 or FIG. 4. FIG. 6 is a block diagram illustrating a PSRAM interface and an SDRAM interface of FIG. 3 according to an embodiment of the present invention. 3 is a block diagram illustrating a PSRAM interface and an SDRAM interface of FIG. 3 according to an embodiment. FIG. 8 is a block diagram showing the second selector of FIG. 3 and FIG. 4. FIG. The dual port SDRAM 100 has a unit memory cell structure of DRAM.

The dual port SDRAM 100 of FIG. 3 is connected to a processor A 50 having a PSRAM external interface bus (EBI) 52 through an A port and operates in a PSRAM mode. The dual port SDRAM 100 includes an address 51 following a PSRAM interface, And receives data 53 and data 59 to decode the row / column address through the PSRAM interface 120 and performs an internal refresh operation to access the DRAM memory array 160.

The dual port SDRAM 100 of FIG. 4 is connected to the processor A 70 having an SDRAM external interface bus (EBI) 72 through an A port and operates in the SDRAM mode. The dual port SDRAM 100 includes an address 71, a control signal 73, And receives the clock 77 and the data 79 and decodes the row / column address through the second SDRAM interface 140 to access the SDRAM memory array 160.

Here, the PSRAM mode indicates a dual port SDRAM operation mode when the dual port SDRAM is connected to a processor having a PSRAM external interface bus, and the SDRAM mode indicates a dual port SDRAM mode when the dual port SDRAM is connected to a processor having an SDRAM external interface bus. Lt; / RTI >

The dual port SDRAM 100 accesses the data with the processor B 60 having the SDRAM external interface (EBI, 62) through the B port. Processor B 60 having SDRAM external interface bus 62 is coupled to address 61 and a plurality of control signals (not shown) via a plurality of address pins, a plurality of control signal pins and a plurality of data pins of dual port SDRAM 100 And the dual port SDRAM 100 outputs and outputs the data 69 using the first SDRAM interface 170 through the B port.

Referring to FIG. 3, a dual port SDRAM 100 according to an exemplary embodiment of the present invention includes a dual interface unit 180, a DRAM memory array 160, and a first SDRAM interface 170. The dual interface unit 180 includes a first selection unit 110, an interface unit 120, and a second selection unit 150.

The dual interface unit 180 may access the DRAM memory array 160 via the PSRAM interface 130 in response to the select signal 54 (see FIG. 3), or via the second SDRAM interface 140, (160).

The first selector 120 provides the address 51, the plurality of control signals 53 and the data 59 to the PSRAM interface 130 via the first signal path in response to the selection signal 54, A plurality of control signals 73, a clock 77 and data 79 to the second SDRAM interface 140 via a second signal path.

The selection signal 54 may be input via the external pin of the dual port SDRAM 100. [ The selection signal 54 is used to determine whether the dual port SDRAM 100 is connected to a processor having a PSRAM external interface bus or to a processor having an SDRAM external interface bus in the process of connecting the dual port SDRAM 100 to a specific processor It can be set to have a predetermined state in advance by the chip set designer.

Specifically, the select signal 54 can be preset to have an active state when the dual port SDRAM 100 is connected to the processor A 70 having the SDRAM external interface bus (EBI) 72 through the A port Port SDRAM 100 is connected to the processor A 50 having the PSRAM external interface bus (EBI) 52 through the A port, it can be preset to have the inactive state. Here, the active state is, for example, a high state, and the inactive state is a low state. Alternatively, the active state may have a low state, and the inactive state may have a high state.

The first selector 120 may include a plurality of demultiplexers 92 and 94 and a demultiplexer / demultiplexer 98 that perform a demuxing operation in response to the selection signal 54. 5, the first selector 120 includes a plurality of demultiplexers and a demultiplexer / demultiplexer. In addition to the demultiplexer and the demultiplexer / demultiplexer, It is needless to say that the present invention can be implemented by another circuit that performs a function of selecting one of two output signals.

The interface unit 120 includes a chip select signal / CS (Chip Select), a write enable signal / WE (Write Enable), and an output enable signal / OE (Output Enable) that follow the interface of the PSRAM when the selection signal is inactive. And a control signal 53 such as a wait signal WAIT and an address 111 to decode an address to access the DRAM memory array 160 to perform operations such as reading, writing, and refreshing.

When the selection signal is in an active state, the interface unit 120 outputs a chip selection signal / CS, a row strobe signal / RAS (row address strobe), a column strobe signal / CAS (column address strobe) Control signals 53 such as an enable signal / WE, a clock CLK 116 and an address 112, decodes the address, accesses the DRAM memory array 160, and performs operations such as reading, writing, and refreshing .

Hereinafter, the operation of the interface unit 120 will be described in detail with reference to FIG.

Referring to FIG. 6, the interface unit 120 includes a PSRAM interface unit 130 and a second SDRAM interface unit 140.

The PSRAM interface unit 130 includes a PSRAM control unit 132, an address decoder 136, a refresh setting register 138, a control register 139, and an input / output buffer 134.

Although not shown in the drawing, when the DRAM memory array 160 is composed of a plurality of banks, the PSRAM interface unit 130 and the second SDRAM interface unit 140 are provided for each bank.

For example, a specific one of the addresses 111 input to the PSRAM interface unit 130 may indicate one of the two banks, and the PSRAM interface unit 130 is provided for each of the two banks, Two PSRAM interface units 130 may be provided. In addition, for example, the address 114 input to the second SDRAM interface unit 140 may include a separate bank address BA. When the bank address is one bit, one of the two banks may be designated And a second SDRAM interface unit 140 may be provided for each of the two banks, thereby providing a total of two SDRAM interface units 140.

The address decoding unit 136 may include a row buffer, a column buffer, a refresh controller, a row decoder, and a column decoder. The row buffer provides the row address of the address 111 which is input under the control of the PSRAM control unit 132 to the row decoder and the column buffer supplies the column address of the address 111 input under the control of the PSRAM control unit 132 Buffered and provided to the column decoder. In order to perform the internal refresh operation under the control of the PSRAM controller 132, the refresh controller generates a row address indicating a word line to be refreshed at a timing of performing an internal refresh operation and provides the generated row address to the row decoder.

The row decoder decodes and outputs the row address output from the row buffer under the control of the PSRAM controller 132. The column decoder decodes and outputs the column address output from the column buffer under the control of the PSRAM controller 132. [

The refresh setting register 138 receives the address 111 under the control of the PSRAM controller 132 and stores information necessary for performing an internal refresh operation and supplies information necessary for performing the internal refresh operation to the PSRAM controller 132 ).

The control register 139 receives the address 111 under the control of the PSRAM controller 132 and stores information on the operation mode (asynchronous mode, synchronous burst mode, page mode), burst read or burst write operation And provides the operation mode information and the burst length information to the PSRAM controller 132. The PSRAM controller 132 receives the operation mode information and the burst length information.

The refresh setting register 138 and the control register 139 are set to a predetermined default value when the dual port memory 100 is powered up and are updated during the operation of the PSRAM interface unit 130. [ do. For example, the operating mode bits of control register 139 may be set to asynchronous mode at power-up and to synchronous burst mode during operation.

The PSRAM control unit 132 generates predetermined commands for controlling the read, write and refresh operations based on the control signal 113 (for example, / CS, / WE, / OE and WAIT-) And generates predetermined timing signals for performing the read, write, and refresh operations based on the predetermined commands, and outputs the timing signals to the address decoder 136, the refresh setting register 138, the control register 139, and the input / output buffer 134 ).

The input / output buffer 134 buffers the data 112 in the input buffer (not shown) based on the operation mode information and the burst length information under the control of the PSRAM controller 132, and then, in accordance with the write operation timing of the PSRAM, Reads the data 133 from the DRAM memory array 160, buffers the data 133 in the output buffer, and reads the data 133 according to the read operation timing of the PSRAM.

The second SDRAM interface unit 140 includes an SDRAM control unit 142, an address decoding unit 146, an MRS register (Mode Register Set) 148, and an input / output buffer 144.

The address decoder 146 may include a row buffer, a column buffer, a refresh counter, a row decoder, and a column decoder. The row buffer provides the row address of the address 112, which is input under the control of the SDRAM controller 142, to the row decoder, and the column buffer stores the column address of the address 112 input under the control of the SDRAM controller 142 Buffered and provided to the column decoder.

The refresh counter generates a row address indicating a word line to be refreshed at a timing of performing a refresh operation in order to perform a refresh operation under the control of the SDRAM controller 142 and provides the generated row address to the row decoder.

The row decoder decodes and outputs the row address output from the row buffer under the control of the SDRAM controller 142. The column decoder decodes and outputs the column address output from the column buffer under the control of the SDRAM controller 142. [

The MRS register 148 receives the address 111 under the control of the SDRAM controller 142 and receives data for controlling various operation modes of the SDRAM such as CAS latency, Information such as burst length, and the like, and provides the SDRAM controller 142 with information such as CAS latency and burst length.

The SDRAM control unit 142 receives certain commands for controlling the read, write and refresh operations based on the control signals 114 (e.g., / CS, / RAS, / CAS, and / And controls the address decoder 146, the MRS register 148, and the input / output buffer 144 by generating predetermined timing signals for performing the read, write, and refresh operations based on the predetermined commands.

The input / output buffer 144 buffers the data 118 in an input buffer (not shown) based on the CAS latency and burst length information under the control of the SDRAM controller 142 and then outputs the data 118 to the DRAM memory array 160, reads the data 143 from the DRAM memory array 160, buffers the data 143 in the output buffer, and reads the data 143 in accordance with the read operation timing of the SDRAM.

Referring to FIG. 8, the second selector 150a may include a plurality of muxes 152 and 156 and a mux / demux 158 that perform a muxing operation in response to the selection signal 54. Although the second selector 150a includes a plurality of muxes and muxes / demuxs in FIG. 8, the second selector 150a selects one of the two input signals in response to the selection signal 54 in addition to the mux and mux / The present invention is not limited thereto.

The mux 152 selects one of the row address 131a provided from the PSRAM interface unit 120 and the row address 141a provided from the second SDRAM interface unit 140 in response to the selection signal 54, 151a.

The mux 156 selects one of the column address 131b provided from the PSRAM interface unit 120 and the column address 141b provided from the second SDRAM interface unit 140 in response to the selection signal 54 and outputs the column address 151b.

The mux / demux 158 selects one of the data 117 provided from the PSRAM interface unit 120 and the data 118 provided from the second SDRAM interface unit 140 in a write operation in response to the selection signal 54 And outputs the data 153 read from the SDRAM memory array 160 in response to the selection signal 54 to the PSRAM interface unit 120 or the second SDRAM interface unit 140 in response to the selection signal 54 to provide.

In FIG. 6, the PSRAM interface unit 120 and the second SDRAM interface unit 140 have input / output buffers, respectively. However, the PSRAM interface unit 120 and the second SDRAM interface unit 140 may share one input / output buffer 154 as shown in FIG.

In FIG. 7, the remaining configuration blocks of the PSRAM interface unit 130 'and the second SDRAM interface unit 140' are the same as those of the configuration block of FIG. 6, and thus description thereof is omitted.

9, when the PSRAM interface unit 130 'and the second SDRAM interface unit 140' share one input / output buffer 154 as shown in FIG. 7, the first selector 110 ' A demultiplexer 92 for demultiplexing the address and a demultiplexer 94 for demultiplexing the control signal. In this case, the second selector 110 'includes a mux 152 for mowing the row address and a mux 156 for mowing the column address, as shown in FIG.

3, the first SDRAM interface 170 receives address 61, control signals 63, and clock 67 from the processor B 60, which has an SDRAM external interface bus 62, And outputs the decoded address 171 to the DRAM memory array 160. The address decoder 173 decodes the decoded address 171 to the DRAM memory array 160 and outputs the decoded address 171 to the DRAM memory array 160 in accordance with the operation timing of the SDRAM such as reading, 173 to and from the DRAM memory array 160. The first SDRAM interface 170 has the same configuration as the internal configuration block of the second SDRAM interface 140 of FIG.

Although FIGS. 3 and 4 illustrate a memory having a dual port, the present invention can also be applied to a memory device having a single port. Specifically, the present invention eliminates the first SDRAM interface 170 in the dual port memory devices of FIGS. 3 and 4 and further includes a first selection unit 110, an interface unit 120, a second selection unit 150, The present invention is also applicable to a memory device constituted by a DRAM memory array 160. [

11 is a timing chart showing a read and write operation when the dual port SDRAM operates in the SDRAM mode according to an embodiment of the present invention. The clock signals CLK, / CS, / RAS, / CAS, and / WE in FIG. 11 are the same as the clocks CLK, / CS, / RAS, / CAS, and / WE in FIG.

Referring to FIG. 11, while the selection signal transits from low to high, the SDRAM mode is operated while maintaining the high state, and data is read out from the dual port memory device in synchronization with the clock signal CLK, . When operating in the SDRAM mode, the clock enable signal CKE has a high state because it operates in synchronization with the clock signal. / RAS, / CAS and / WE are both high, it is a NOP (no operation) state. When / CS is high, / RAS, / CAS and / WE and address inputs are ignored. 11 shows a read and a write operation for a memory array corresponding to a specific bank indicated by a bank address.

First, the read operation is performed as follows. When the select signal is high, / CS is low, / WE is high, the low strobe signal / RAS is low, and the column strobe signal / CAS is high, a row address is applied to the address pin, If the word line corresponding to the row address is active and / CS is low, / WE is high, the low strobe signal / RAS is high and the column strobe signal / CAS is low, Data is read from the memory array 160 after a predetermined delay time (CAS Latency) from the moment the column strobe signal / CAS transitions from high to low. In FIG. 11, the case where the delay time (CAS Latency, CL) is two clocks is taken as an example.

Next, the write operation is performed as follows. The row address is applied to the address pin when the selection signal is high, / CS is low, / WE is low, the low strobe signal / RAS is low and the column strobe signal / CAS is high, When the word line corresponding to the row address is active (row active), / CS is low, / WE is low, the low strobe signal / RAS is high and the column strobe signal / CAS is low, And the data is written into the memory array 160. [

FIG. 12 is a timing chart showing a read and write operation when the dual port SDRAM according to an embodiment of the present invention operates in the PSRAM mode.

Referring to FIG. 12, while the selection signal maintains the low state, the system operates in the PSRAM mode to read data from the dual port memory or write data to the dual port memory.

First, the read operation is performed as follows. When the select signal is low, / CS is low, / WE is high, and / OE is low and / OE is low, the address is applied to the address pin and data is read out from the cell of the memory array 160 corresponding to the address.

Next, the write operation is performed as follows. When the selection signal is low, / CS is low, / WE is low, and / OE is high and / OE is high, an address is applied to the address pin and data is written into the cell of the memory array 160 corresponding to the address.

That is, when the selection signal is activated, the dual port SDRAM operates in the SDRAM mode, and the second SDRAM interface unit 140 of FIG. 4 is activated to perform the reading and writing operations. When the selection signal is inactive, The SDRAM operates in the PSRAM mode and the PSRAM interface unit 120 of FIG. 3 is activated to perform the read and write operations.

According to the dual port memory device and the dual port memory device operating method, a dual port memory device and a memory device can be selectively connected to processors having different memory interfaces.

Accordingly, in a portable terminal including processors having different memory interfaces, a dual port memory device using an efficient DRAM memory array in terms of layout area can be selectively connected to processors having different memory interfaces.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (20)

A memory array; A dual interface for accessing the memory array according to a first mode memory interface or for accessing the memory array according to the second mode memory interface based on an address and a control signal input via a first port in response to a selection signal; And And a first memory interface unit for accessing the memory array through the second mode memory interface based on an address and a control signal input through a second port. The dual port memory device of claim 1, wherein the control signal input through the first port is a signal that follows the first mode memory interface or the second mode memory interface. 3. The dual port memory device of claim 2, wherein the control signal input through the second port is a signal that follows the second mode memory interface. The apparatus of claim 1, wherein the dual interface unit Providing an address and control signal input via the first port in response to the selection signal to a first path accessing the memory array in accordance with the first mode memory interface, To a second path for accessing the second path; Based on an address and a control signal provided through the first path, an address and data for accessing the memory array in accordance with a first mode memory interface or outputting an address and data for accessing the memory array based on an address and a control signal provided through the second path, An interface for outputting an address and data for accessing the memory array according to the second mode memory interface; And An address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface and a control signal in response to the selection signal And a second selection unit. 5. The apparatus of claim 4, wherein the interface A first type memory interface unit for outputting an address and data for accessing the memory array in accordance with the first type memory interface based on an address and a control signal provided through the first path; And And a second mode memory interface unit for outputting an address and data for accessing the memory array according to the second mode memory interface based on an address and a control signal provided through the second path, Memory device. 5. The apparatus of claim 4, wherein the interface An input / output buffer connected between the first selector and the second selector for buffering data to be accessed by the memory array; Buffering data to be accessed to the memory array in the input / output buffer according to the first type memory interface based on an address and a control signal provided through the first path, decoding the address provided through the first path A first memory interface unit for outputting the first mode memory interface; And Buffering data to be accessed to the memory array in the input / output buffer according to the second type memory interface based on an address and a control signal provided through the second path, and decoding the address provided through the second path And a second mode memory interface unit for outputting the second mode memory interface. 5. The dual port memory device of claim 4, wherein the first selector includes a plurality of demuxes for demultiplexing an address and a control signal input through the first port in response to the selection signal. 5. The memory device according to claim 4, wherein the second selector is responsive to the selection signal to select an address for accessing the memory array according to the first mode memory interface and an address for accessing the memory array according to the second mode memory interface Wherein the dual port memory device is a dual port memory device. 2. The dual port memory device of claim 1, wherein the first mode memory interface is a PSRAM interface. 10. The dual port memory device of claim 9, wherein the second mode memory interface is an SDRAM interface and the memory array has a DRAM cell structure. A memory array; And And a dual interface portion for accessing the memory array in accordance with the first mode memory interface or for accessing the memory array in accordance with the second mode memory interface based on the address and control signal input through the first port in response to the select signal / RTI > 12. The system of claim 11, wherein the dual interface Providing an address and control signal input via the first port in response to the selection signal to a first path accessing the memory array in accordance with the first mode memory interface, To a second path for accessing the second path; Based on an address and a control signal provided through the first path, an address and data for accessing the memory array in accordance with a first mode memory interface or outputting an address and data for accessing the memory array based on an address and a control signal provided through the second path, An interface for outputting an address and data for accessing the memory array according to the second mode memory interface; An address for accessing the memory array in accordance with the first-type memory interface in response to the selection signal and an address for selecting one of an address and data for accessing the memory array in accordance with the second- 2 < / RTI > Accessing the memory array according to the first mode memory interface based on the address and control signal input through the first port while the select signal is inactive; And And accessing the memory array in accordance with a second mode memory interface based on the address and control signals input via the first port while the select signal is active. 14. The method of claim 13, Accessing the memory array according to the second mode memory interface based on the address and control signals input via the second port. 14. The method of claim 13, further comprising: providing an address and a control signal input through the first port to a first path accessing the memory array according to the first mode memory interface while the select signal is inactive; And And providing the memory array to a second path accessing the memory array according to the second mode memory interface while the select signal is active. 16. The method of claim 15, wherein accessing the memory array according to a first mode memory interface based on an address and a control signal input via a first port while the select signal is inactive And outputting an address and data for accessing the memory array according to the first mode memory interface based on an address and a control signal provided through the first path. . 17. The method of claim 16, wherein accessing the memory array in accordance with a second mode memory interface based on an address and a control signal input via the first port while the select signal is active And outputting an address and data for accessing the memory array according to the second mode memory interface based on an address and a control signal provided through the second path. Way. 18. The method of claim 17, Selecting an address for accessing the memory array in accordance with the first mode memory interface and an address for accessing the memory array in accordance with the second mode memory interface in response to the select signal, Lt; RTI ID = 0.0 > 2, < / RTI > 14. The method of claim 13, wherein the first mode memory interface is a PSRAM interface. 14. The method of claim 13, wherein the second mode memory interface is an SDRAM interface and the memory array has a DRAM cell structure.

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