KR100472860B1 - Dual Port RAM having DRAM cell and being compatible with SRAM - Google Patents

Abstract

SRAM compatible dual port RAM using DRAM cells will be published. Dual port RAM of the present invention comprises a memory array; A first port for accessing the memory array in response to the first chip select signal; And a second port for accessing the memory array in response to the second chip select signal. Each of the memory cells of the memory array is a DRAM cell that requires a refresh operation to be performed within a predetermined refresh period in order to effectively preserve stored data. Dual port RAM of the present invention is compatible with the SRAM while using a DRAM cell. Therefore, the dual port RAM of the present invention has considerable advantages in terms of layout area compared to the dual port RAM using a conventional SRAM cell.

Description

Dual Port RAM having DRAM cell and being compatible with SRAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a dual port RAM.

Dual port RAM is a type of memory with two input and output ports, and is used in the VME bus (VERSA module European bus) structure system used in the industrial field.

The dual port RAM has two input / output ports, so that one port can access the processor in its own board, and the other port can access the other board through the bus. The dual port RAM having such a structure enables data access from two ports.

By the way, the existing dual port RAM is a cell of the SRAM (SRAM) as a memory cell. The unit memory cell for storing one bit of information in the SRAM is implemented by four transistors forming a latch structure and two transistors serving as transfer gates. That is, since the conventional SRAM stores data in unit memory cells having a latch structure, a refresh operation for storing data is not required. In addition, SRAM has advantages such as faster operation speed and lower power consumption than DRAM.

However, since the unit memory cell of the SRAM is implemented with six transistors, there is a disadvantage in terms of the layout area required compared to the unit memory cell of the DRAM implemented with one transistor and one capacitor.

Accordingly, an object of the present invention is to solve the problems of the prior art, to provide a dual port RAM compatible with the SRAM while using a DRAM cell to reduce the layout requirements.

One aspect of the present invention for solving the above technical problem relates to a dual port RAM. The dual port RAM of the present invention has a memory array including a plurality of memory cells arranged on a matrix defined by rows and columns, and independently responds to the first chip select signal and the second chip select signal, respectively. Can be accessed. The dual port RAM of the present invention may be interfaced with an external system that simultaneously provides a row address for selecting a row of the memory array and a column address for selecting a column. The dual port RAM of the present invention includes the memory array; A first port accessing the memory array in response to the first chip select signal; And a second port for accessing the memory array in response to the second chip select signal. Each of the memory cells of the memory array is a DRAM cell in which each of the memory cells is required to perform a refresh operation within a predetermined refresh period in order to effectively preserve stored data. In addition, the dual port RAM does not require externally allocating an operation section for performing the refresh operation of the DRAM cell and supplying a signal for controlling the refresh operation.

Preferably, in the dual port RAM of the present invention, when the activation of the first chip selection signal and the activation of the second chip selection signal occur simultaneously, the access operation from the first port is performed from the second port. A control block for controlling to be performed prior to the access operation is further provided.

More preferably, the dual port RAM of the present invention further includes a refresh flag generator for generating a refresh flag for requesting to perform the refresh operation. The control block may include a first control to perform an access operation from the first port prior to performing the refresh operation when the activation of the first chip selection signal and the activation of the refresh flag occur simultaneously. A first control unit generating a signal; And generating a second control signal for performing the refresh operation prior to the access operation from the second port when the activation of the second chip select signal and the activation of the refresh flag occur simultaneously. A control unit is provided.

Another aspect of the present invention relates to a method of driving the dual port ram. A method of driving a dual port RAM of the present invention may include: A) accessing a memory array from a predetermined first port in response to a predetermined first chip selection signal; And B) accessing the memory array from the predetermined second port in response to the predetermined second chip select signal. Each of the memory cells of the memory array is a DRAM cell in which each of the memory cells is required to perform a refresh operation within a predetermined refresh period in order to effectively preserve stored data. In addition, the dual port RAM does not require externally allocating an operation section for performing the refresh operation of the DRAM cell and supplying a signal for controlling the refresh operation.

The dual port RAM of the present invention internally employs a DRAM cell and performs a refresh operation. However, like the conventional SRAM dual port RAM, an external control unit allocates an operation section for refreshing and separate control for controlling the refresh operation. No external provision of signals is required.

On the other hand, since the dual port RAM of the present invention employs a DRAM cell, it performs a refresh (REFRESH) operation. The refresh operation is an operation of activating a specific word line, outputting data of all DRAM cells connected to the word line from the DRAM cell, and then amplifying and writing the data again.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

1 is a block diagram for conceptually describing a dual port RAM according to an embodiment of the present invention. The dual port RAM of the present invention includes a memory array 10, a first port 21, a second port 33, a refresh flag generator 59, a first controller 45, and a second controller 51. do. The memory array 10 includes a plurality of memory cells 11 arranged on a matrix defined by rows and columns. The memory cell 11 is a cell requiring refreshing within a predetermined refresh period in order to preserve stored data. A representative example of the memory cell 11 is a 'DRAM cell'. Therefore, in the present specification, for convenience of description, the memory cell 11 may be referred to as a 'DRAM cell'. As illustrated in FIG. 2, the DRAM cell includes a capacitor configured to store data of a transfer transistor 11a gated by a word line WL and a bit line BL transmitted through the transfer transistor 11a. 11b).

The first port 21 can be accessed from another board, and can exchange data with external devices. That is, data input from an external device is passed through the input / output buffer 23, the bus amplifier 25, the column selector 27, and the bit line pairs BL and / BL of the memory array 10. It is written to the selected memory cell 11 in 10). In addition, the data drawn out from the selected memory cell 11 in the memory array 10 includes a bit line pair BL, / BL, a column selector 27, a bus amplifier 25, and an input / output buffer 23. Through, it may be transmitted to an external device.

The input / output buffer 23 and the bus amplifier 25 are enabled in response to the first buffer enable signal BUEN1 and the amplifier enable signal AMPEN provided from the first controller 45, respectively. Then, the column selector 27, in response to the column select signal YSEL provided from the Y-address decoder 35, the data provided from the specific bit line pairs BL and / BL and the bus amplifier 25. Electrically connect the bus DB.

The second port 33 is accessed by a processor in its own board, and data can be read. That is, data stored in the memory array 10 may be read and transmitted to the processor of the board through the second port 33. At this time, data of the selected row and all the columns that are connected to the column are drawn out to the bit line pairs BL and / BL, and the second port 33 is connected to the respective sense amplifiers and bit line buffers. Is sent to. Therefore, in the present invention, the second port 33 may be a transmission line BPO (1 to n) capable of simultaneously transmitting a plurality of data.

Meanwhile, in FIG. 1, n sense amplifiers connected to each of the n bit line pairs BL and / BL are illustrated as a sense amplifier block 29, and each of the n bit line pairs BL and / BL is illustrated. The bit line buffer for buffering the data of is shown as a buffer block 31 as a whole.

The sense amplifiers of the sense amplifier block 29 are also enabled in the data input / output operation through the first port 21 to amplify the data of the bit line pair.

The buffer block 31 and the sense amplifier block 29 are enabled in response to the sense amplifier enable signal SAEN and the second buffer enable signal BUEN2 provided from the internal control signal generator 43, respectively. do.

The refresh flag generator 59 incorporates a timer such as an oscillator to generate the refresh flag REFLG. The refresh flag REFLG is activated every predetermined refresh period, and requests the refresh operation of the memory cells of the dual port RAM according to the present invention to proceed.

The counter 57 generates a refresh address XADD_REF that sequentially increases or decreases in response to the activation of the refresh flag REFLG. The refresh address buffer 55 buffers the refresh address XADD_REF and provides it to the X-address mixer 41.

The second X-address buffer 53 buffers the second row address XADD_B and provides it to the X-address mixer 41. The second controller 51 receives the refresh flag REFLG and the second chip select signal CS_B, generates a second control signal group CONT2, and provides the second control signal group CONT2 to the internal control signal generator 43. Here, when the second chip select signal CS_B and the refresh flag REFLG are simultaneously activated, the second control signal group CONT2 may perform the dual port RAM refresh operation of the second control signal group CONT2. It has information that controls to proceed prior to the access operation to the memory array 10 at the port 33.

The first X-address buffer 49 buffers the first row address XADD_A and provides it to the X-address mixer 41. The Y-address buffer 47 buffers the column address YADD_A and provides it to the Y-address decoder 35.

The first control unit 45 receives the refresh flag REFLG, the first chip select signal CS_A, and the write enable signal / WE, and thus the first buffer enable signal BUEN1 and the amplifier enable signal. (AMPEN) is generated, and a first control signal group CONT2 is generated and provided to the internal control signal generator 43. Here, when the activation of the first chip select signal CS_A and the refresh flag REFLG occurs simultaneously in the first control signal group CONT1, the dual port RAM refresh operation of the first control signal group CONT1 may occur. After the access operation to the memory array 10 at the port 21 proceeds, it has information that controls to be performed.

The X-address messager 41 may include a buffered refresh address XADD_REF provided from the refresh address buffer 55 and a buffered second row address XADD_B provided from the second X-address buffer 53. And one of the buffered first row addresses XADD_A provided from the first X-address buffer 49 is selected by the predetermined control signal CONMX and provided to the X-address decoder 39. In addition, the control signal CONMX is a signal provided from the internal control signal generator 43, and controls the X-address mixer 41 to select as follows.

First, when the activation of the first chip select signal CS_A and the activation of the second chip select signal CS_B occur simultaneously, the buffered first row address XADD_A is selected to select the X-address decoder 39. To provide.

When the activation of the first chip select signal CS_A and the activation of the refresh flag REFLG occur at the same time, the buffered first row address XADD_A is selected and provided to the X-address decoder 39.

When the activation of the second chip select signal CS_B and the activation of the refresh flag REFLG occur at the same time, the buffered refresh address XADD_REF is selected and provided to the X-address decoder 39.

In the present specification, the first chip select signal CS_A and the second chip select signal CS_B are signals having independent timing. When either one of the first chip select signal CS_A and the second chip select signal CS_B is activated, the dual port RAM of the present invention is enabled. In the present specification, the first control unit 45, the second control unit 51, and the internal control signal generator 43 may be collectively referred to as a 'control block'.

The Y-address decoder 35 decodes the buffered column address YADD_A and provides the column selector 27 to select a column of the memory array 10.

The X-address decoder 39 decodes a row address selected by the X-address decoder 41 and provides the word line driver 47 to select a row of the memory array 10. The word line driver 47 drives the specified word line WL.

Next, referring to the timing diagrams of FIGS. 3 to 6, the operation timing of the dual port RAM of the present invention is described.

3 is an operation timing diagram of the dual port RAM according to the present invention, and illustrates a case where the memory array 10 is accessed through the first port while the refresh flag REFLG is not activated. In the timing diagram of Fig. 3, the write access operation and the read access operation are performed in succession.

Referring to FIG. 3, the second chip select signal CS_B is in an "L" state. In this case, in the write period in which the write enable signal / WE is "L", when the first chip select signal CS_A is activated, the first buffer enable signal BUEN1, the word line WL, and the column select signal YSEL, the amplifier enable signal AMPEN is activated in turn. That is, when the bit line pairs BL and / BL are developed and the sense amplifier enable signal SAEN is enabled, sensing and restoring operations are performed. Thereafter, when the column select signal YSEL is activated, the input data DIN is written in the selected memory cell 10.

In the read period in which the write enable signal / WE is "H", when the first chip select signal CS_A is activated, data stored in the selected memory cell 10 is transferred through the first port 21. It is drawn out to the output data DOUT.

FIG. 4 is another operation timing diagram of the dual port RAM according to the present invention, and illustrates a case where the memory array 10 is write-accessed through the first port while the refresh flag REFLG is activated.

As shown in FIG. 4, when the activation of the first chip select signal CS_A and the activation of the refresh flag REFLG occur simultaneously in the dual port RAM of the present invention, the access operation in the first port 21 is first performed. Is executed.

After the access operation on the first port 21 is completed, the refresh operation on the memory cells of the present invention is performed.

FIG. 5 is another operation timing diagram of the dual port RAM according to the present invention, and illustrates a case where the memory array 10 is accessed through the second port 33 while the refresh flag REFLG is not activated.

Referring to FIG. 5, the first chip select signal CS_A is in an "L" state. In this case, the amplifier enable signal AMPEN, the first buffer enable signal BUEN1, and the column select signal YSEL remain in the "L" state, thereby preventing access from the first port 21. When the second chip select signal CS_B is activated, the sense amplifier enable signal SAEN and the second buffer enable signal BUEN2 are activated. Therefore, data of the memory cells connected to the selected row is transmitted to the internal processor through the second port 33.

FIG. 6 also shows another operation timing diagram of the dual port RAM according to the present invention, in which the memory array 10 is accessed through the second port while the refresh flag REFLG is activated.

As shown in FIG. 6, when the activation of the second chip select signal CS_B and the activation of the refresh flag REFLG occur simultaneously in the dual port RAM of the present invention, the refresh operation of the memory array 10 of the present invention is performed. This is executed first.

After the refresh operation is performed on the memory array 10 of the present invention, the access operation on the second port 33 is performed.

When the access procedure in the case where the access at the first port 21, the access at the second port 33 and the refresh operation of the dual port RAM collide with each other is summarized, the access at the first port 21, The refresh operation proceeds in the order of access from the second port 33.

By such a procedure, there is an advantage that the refresh period can be increased while securing sufficient time for the access operation in the first port 21. That is, in the dual port RAM of the present invention, the time required for access at the first port 21 is relatively longer than the time required for access at the second port 33. In such a case, by performing the access operation on the first port 21 prior to the refresh operation, the interval for the access operation on the first port 21 can be increased. In addition, the refresh cycle can be increased by performing the refresh operation before the access operation at the second port 33.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

By the above structure, the dual port RAM of the present invention is compatible with the SRAM while using a DRAM cell. Therefore, the dual port RAM of the present invention has considerable advantages in terms of layout area compared to the dual port RAM using a conventional SRAM cell.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram for conceptually describing a dual port RAM according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating memory cells included in the memory array of FIG. 1.

3 is an operation timing diagram of the dual port RAM of the present invention, and illustrates a case where the memory array is accessed through the first port while the refresh flag is not activated.

4 is another operation timing diagram of the dual port RAM according to the present invention, and illustrates a case where the memory array is write-accessed through the first port while the refresh flag is activated.

FIG. 5 is another operation timing diagram of the dual port RAM according to the present invention, and illustrates a case where the memory array is accessed through the second port while the refresh flag is not activated.

FIG. 6 is another operation timing diagram of the dual port RAM according to the present invention, which illustrates a case where the memory array is accessed through the second port while the refresh flag is activated.

Claims (6)

A dual port RAM having a memory array including a plurality of memory cells arranged on a matrix defined by rows and columns, and capable of accessing the memory array independently of the first chip select signal and the second chip select signal. The dual port RAM, which may be interfaced with an external system that simultaneously provides a row address for selecting a row of the memory array and a column address for selecting a column. The memory array; A first port accessing the memory array in response to the first chip select signal; And A second port for accessing the memory array in response to the second chip selection signal, Each of the memory cells The DRAM cell is required to perform the refresh operation within a predetermined refresh period in order to effectively preserve the stored data. The dual port ram The dual port RAM, characterized in that it is not required to allocate the operation interval for performing the refresh operation of the DRAM cell, and to supply a signal for controlling the refresh operation. According to claim 1, When the activation of the first chip select signal and the activation of the second chip select signal occur simultaneously, a control block for controlling the access operation from the first port to be performed prior to the access operation from the second port. Dual port ram characterized in that it further comprises. The method of claim 2, And a refresh flag generator for generating a refresh flag for requesting to perform the refresh operation. The control block is When the activation of the first chip select signal and the activation of the refresh flag occur simultaneously, a first control signal for generating a first control signal for performing an access operation from the first port prior to performing the refresh operation. Control unit; And When the activation of the second chip select signal and the activation of the refresh flag occur at the same time, generating a second control signal to cause the refresh operation to proceed prior to performing the access operation from the second port. Dual port RAM comprising a control unit. A dual port RAM having a memory array including a plurality of memory cells arranged on a matrix defined by rows and columns, comprising: an external system for simultaneously providing a row address for selecting a row of the memory array and a column address for selecting a column; In the driving method of the dual port RAM that can be interfaced, A) in response to a predetermined first chip selection signal, accessing the memory array from a predetermined first port; And In response to a predetermined second chip select signal, accessing the memory array from a predetermined second port; Each of the memory cells The DRAM cell is required to perform the refresh operation within a predetermined refresh period in order to effectively preserve the stored data. The dual port ram And externally allocating an operation section for performing the refresh operation of the DRAM cell and supplying a signal for controlling the refresh operation. The method of claim 4, wherein If the activation of the first chip selection signal and the activation of the second chip selection signal occur simultaneously, step C) of controlling the access operation from the first port to be performed prior to the access operation from the second port. The method of driving a dual port RAM further comprising. The method of claim 5, And generating a refresh flag for requesting to perform the refresh operation. Step C) If activation of the first chip select signal and activation of the refresh flag occurs, controlling C1) to perform an access operation from the first port prior to performing the refresh operation; And And if the activation of the second chip select signal and the activation of the refresh flag occur, step C2) of controlling the execution of the refresh operation prior to the execution of the access operation from the second port. Dual port ram driving method.