KR20080026775A - Plasma display, and driving device and method thereof - Google Patents

Abstract

A plasma display apparatus, and an apparatus and a method for driving the same are provided to decrease the manufacturing cost of circuit by implementing transistors having a low breakdown voltage in a sustain discharge driver. A first end of a second capacitor(CS2) is connected to a first end of a first capacitor(CS1). A scan IC(Integrated Circuit)(510), of which output stages are connected to first electrodes, having first and second input stages selectively apply the voltage of the second input stage to corresponding first electrodes among the plural first electrodes during an address period. First and second transistors are connected between the first end of the first capacitor and the first input stage, and the first end of the first capacitor and the second input stages, respectively. A rising path, which is connected between the input stage and a contact point of the first and second capacitors, increases the voltage of the first electrodes. A falling path, which is connected between the second stage and the contact point, decreases the voltage of the first electrodes. A switch selectively applies a second voltage to the second end of the first or second capacitor.

Description

Plasma display device, driving device thereof and driving method thereof {PLASMA DISPLAY, AND DRIVING DEVICE AND METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 is a view showing a driving waveform according to a first embodiment of the present invention.

3 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 2.

4 is a diagram illustrating signal timing of the sustain discharge driving circuit 410 for generating the driving waveform of FIG. 2.

5A to 5H are views illustrating the operation of the sustain discharge driving circuit 410 of FIG. 3 according to the signal timing of FIG. 4, respectively.

6A to 6C are diagrams illustrating driving waveforms of the plasma display device according to the second to fourth embodiments, respectively.

The present invention relates to a plasma display device, a drive device thereof and a drive method thereof.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size.

In a plasma display device, one frame is divided into a plurality of subfields having respective weights and driven, and a gray level is displayed by a combination of weights of subfields in which a display operation occurs among the plurality of subfields. Cells to be turned on and cells not to be turned on during the address period of each subfield are selected, and sustain discharge is performed on the cells to be turned on to actually display an image during the sustain period.

In particular, since the high level voltage and the low level voltage are alternately applied to the electrodes performing sustain discharge in the sustain period, the transistor for applying the high level voltage and the low level voltage corresponds to at least the difference between the high level voltage and the low level voltage. Should have a voltage withstand voltage. As a result, the transistor having a high breakdown voltage increases the cost of the sustain discharge driving circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device, a driving device thereof, and a driving method thereof capable of reducing the unit cost of a sustain discharge driving circuit.

According to an aspect of the present invention, a plasma display device includes a plurality of first electrodes, a first transistor having a first end connected to a first power supply for supplying a first voltage, and a second voltage lower than the first voltage A second transistor having a first end connected to a second power source; a first end connected to a second end of the first transistor and a second end connected to a second end of the second transistor A third capacitor is charged with a third voltage and a first end is charged with a first capacitor and a fourth voltage connected with the second end of the first transistor, and a first end is connected to a second end of the first capacitor. A second capacitor connected between the second terminal of the first transistor and a fourth transistor connected between the first end of the first capacitor and the second end of the first transistor, and between the second end of the second capacitor and the second end of the second transistor. A fifth transistor connected to the A plurality of sixth transistors each having a first end connected to the number of first electrodes, a plurality of seventh transistors each having a first end connected to the plurality of first electrodes, and a second of the plurality of sixth transistors An eighth transistor connected between a terminal and a first end of the first capacitor, a ninth transistor connected between a second end of the plurality of seventh transistors and a second end of the second capacitor, and the plurality of sixth transistors A rising path connected between a second end of a transistor and a contact point of the first and second capacitors to increase a voltage of the plurality of first electrodes, and a second end of the plurality of seventh transistors and the first and second capacitors And a falling path connected between the contacts of the plurality of first electrodes to reduce voltages of the plurality of first electrodes.

According to another aspect of the present invention, a method of driving a plasma display device including a first electrode for performing a display operation is provided. The driving method includes applying a fourth voltage to the first electrode through a first power supply for supplying a first voltage and first and second capacitors respectively charging a second voltage and a third voltage, wherein the fourth voltage is applied to the first electrode. Increasing a voltage of the first electrode through a first power source and a first inductor connected to the first capacitor and the first electrode, and through the first power source, the second capacitor, and the first inductor Further increasing the voltage of the first electrode, further increasing the voltage of the first electrode through the second power supply supplying the fifth voltage higher than the first voltage and the second capacitor and the first inductor; Applying the sixth voltage to the first electrode through the second power source and the first and second capacitors, applying a second inductor, the second capacitor, and the second power source connected to the first electrode; Through awards Reducing the voltage of the first electrode, further reducing the voltage of the first electrode through the second inductor, the second capacitor and the first power source, and the second inductor, the first capacitor and And further reducing the voltage of the first electrode through the second power source.

According to still another feature of the present invention, a driving apparatus of a plasma display device including a plurality of first electrodes is provided. The driving device has a first capacitor, a first capacitor having a second capacitor connected to a first end of the first capacitor, a first and a second input terminal, and a plurality of first output terminals being the plurality of first electrodes. A scan integrated circuit connected to the first input terminal, the scan integrated circuit selectively applying a voltage of the second input terminal to a corresponding first electrode of the plurality of first electrodes during an address period, the first input terminal of the scan integrated circuit and the first capacitor A first transistor connected between a first end of the second transistor, a second transistor connected between a second input end of the scan integrated circuit and a first end of the second capacitor, a first input end of the scan integrated circuit and the first transistor A rising path connected between the contacts of the first and second capacitors to increase the voltage of the plurality of first electrodes, between the second input terminal of the scan integrated circuit and the contacts of the first and second capacitors A falling path connected to reduce voltages of the plurality of first electrodes, and switching means for selectively applying a first voltage and a second voltage lower than the first voltage to a second end of the first or second capacitor. Include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that the voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of the semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is very low, and thus the threshold voltage is regarded as 0V and approximated.

First, a plasma display device, a driving device thereof, and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating a driving waveform according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as "A electrodes") A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs with each other in the row direction (hereinafter, " X electrodes "(X1 to Xn) and scan electrodes (hereinafter referred to as" Y electrodes ") (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X electrode and the Y electrode perform a display operation for displaying an image in the sustain period. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 110. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes an address period and a sustain period.

The address electrodes, the scan electrodes, and the sustain electrode drivers 300, 400, and 500 are each of the A electrodes A1 to Am, the Y electrodes Y1 to Yn, and the X electrodes X1 to X according to the driving control signals from the controller 200. A driving voltage is applied to Xn).

Specifically, during the address period of each subfield, the address electrode, the scan electrode, and the sustain electrode driver 300, 400, and 500 select a discharge cell to be turned on and a discharge cell not to be turned on from the plurality of discharge cells 110. . During the sustain period of each subfield, as shown in FIG. 2, the scan electrode driver 400 alternately has a high level voltage (2 Vs) and a low level voltage (-Vs) at the plurality of Y electrodes Y1 to Yn. The sustain discharge pulse is applied a number of times corresponding to the weight of the subfield. The sustain electrode driver 500 applies a sustain discharge pulse to the plurality of X electrodes X1 to Xn in a phase opposite to that of the sustain discharge pulse applied to the Y electrodes Y1 to Yn. In this way, the voltage difference between each Y electrode and each X electrode alternates between the 3Vs voltage and the -3Vs voltage, whereby the sustain discharge is repeated a predetermined number of times in the discharge cell to be turned on.

Next, the sustain discharge driving circuit for supplying the sustain discharge pulse of FIG. 2 will be described in detail with reference to FIGS. 3, 4 and 5A to 5H.

3 is a diagram illustrating a sustain discharge driving circuit 410 of the scan electrode driver 400 for generating the driving waveform of FIG. 2. In FIG. 3, only the sustain discharge driving circuit 410 connected to the plurality of Y electrodes Y1 to Yn is illustrated for convenience of description, and the sustain discharge driving circuit 410 is formed in the scan electrode driver 400 of FIG. 1. Can be. In the sustain discharge driving circuit 410, only one X electrode and one Y electrode are illustrated for convenience of description, and a capacitive component formed by the X electrode and the Y electrode is illustrated as a panel capacitor Cp.

As shown in Fig. 3, the sustain discharge driving circuit 410 includes transistors Y1, Y2, Y3, Yp, Yn, YH, YL, capacitors Cs1, Cs2, inductor Ly, diodes D1, D2. And a scan integrated circuit (hereinafter referred to as a "scanning IC") 411. In FIG. 3, transistors Y1, Y2, Y3, Yp, Yn, YH, YL, Sch, and Scl are shown as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors. , Y2, Y3, Yp, Yn, YH, YL, Sch, Scl, body diodes may be formed from source to drain, and other transistors having similar functions instead of NMOS transistors may be used. Y3, Yp, Yn, YH, YL, Sch, and Scl) In addition, in Fig. 3, transistors Y1, Y2, Y3, Yp, Yn, YH, YL, Sch, and Scl are shown as one transistor each. However, the transistors Y1, Y2, Y3, Yp, Yn, YH, YL, Sch, and Scl may be formed of a plurality of transistors connected in parallel, respectively.

Referring to FIG. 3, the scanning IC 411 has a first input terminal and a second input terminal, and an output terminal is connected to the Y electrode of the panel capacitor Cp. The scan IC 411 selectively applies the voltage at the first input terminal and the voltage at the second input terminal to the corresponding Y electrodes in order to select a cell to be turned on in the address period. Although one Y electrode is connected to the scan IC 411 in FIG. 3, the scan IC 411 may have a plurality of output terminals. That is, the plurality of Y electrodes Y1 to Yk may be connected to the plurality of output terminals of the scan IC 411. In this case, when the number of output terminals of the scanning IC 411 is smaller than the number of the Y electrodes Y1 to Yn, the plurality of scanning ICs 411 may be used. The scanning IC 431 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode of the panel capacitor Cp. A second end of the inductor Ly having a first end connected to the first input end and the second input end of the scanning IC 411 is respectively connected to the second end of the capacitor Cs1 and the first end of the capacitor Cs2. It is connected. The transistor of the transistor Y1 having a source connected to the first end of the capacitor Cs1 is connected to the power supply Vs supplying the Vs voltage, and the drain of the transistor Ys is connected to the second end of the capacitor Cs2. The source of Y3 is connected to the ground terminal 0 which supplies the 0V voltage. The transistor Y2 is connected between the source of the transistor Y1 and the drain of the transistor Y3, and the transistor Yp is connected between the transistor Y1 and the first end of the capacitor Cs1. Transistor Yn is connected between Y3 and the second end of capacitor Cs2. In addition, a transistor YH is connected between the first terminal of the capacitor Cs1 and the first input terminal of the scanning IC 411, and the transistor (YH) is connected between the second terminal of the capacitor Cs2 and the second input terminal of the scanning IC 411. YL) is connected. In this case, the transistors Y1, Y2, Y3, Yp, and Yn operate as switching means for selectively applying a voltage of Vs or 0V to the first terminal of the capacitor Cs1 or the second terminal of the capacitor Cs2. The cathode of the diode D1 having an anode connected to the first end of the inductor Ly is connected to the first input terminal of the scan IC 411, and the cathode is connected to the first end of the inductor Ly. An anode of the diode D2 is connected to the second input terminal of the scanning IC 411. When the transistors Y3 and Yn are turned on, the transistors Y1 and Yp are turned on to form charge paths for charging the two capacitors Cs1 and Cs2 to the voltage Vs / 2, respectively. Cs2) is charged to the Vs / 2 voltage respectively. The diode D1 is for setting up a rising path that blocks the current path formed by the body diode of the transistor Sch and increases the voltage of the Y electrode, and the diode D2 is due to the body diode of the transistor Scl. To set the falling path to block the current path to be formed and to reduce the voltage of the Y electrode. In addition, although one inductor Ly is connected to the contacts of the diodes D1 and D2 in FIG. 3, the inductor may be connected to each of the rising path and the falling path.

Next, the operation of the sustain discharge driving circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 4 and 5A to 5H.

4 is a diagram illustrating signal timing of the sustain discharge driver circuit 410 for generating the driving waveform of FIG. 2, and FIGS. 5A to 5H are diagrams illustrating the sustain discharge driver circuit 410 of FIG. 3 according to the signal timing of FIG. 4, respectively. Is a view showing the operation. It is assumed that the transistors Y2, Y3, Yp, YL, and Scl are turned on before the mode 1 (M1) is started, and the -Vs voltage is applied to the Y electrode.

4 and 5A, in the mode 1 M1, the transistor Sch is turned on and the transistors YL, Scl are turned off, so that the ground terminal 0, the transistors Y3, Y2, Yp, and the capacitor Cs1 are turned on. ), Resonance occurs in the path of the Y electrode of the inductor Ly, the diode D1, the transistor Sch, and the panel capacitor Cp (①). Then, the energy charged in the capacitor Cs1 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from the voltage of -Vs to the voltage of 0V.

Subsequently, the transistor Yn is turned on and the transistors Y2 and Yp are turned off in the mode 2 (M2), so that the ground terminal 0, the transistors Y3 and Yn, and the capacitor Cs2 are shown in FIG. 5B. ), Resonance occurs in the path of the Y electrode of the inductor Ly, the diode D1, the transistor Sch, and the panel capacitor Cp (2). Then, the energy charged in the capacitor Cs2 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from the 0V voltage to the Vs voltage. At this time, since the drain of the transistor Y1 is connected to the power supply Vs and the source voltage of the transistor Y2 becomes the 0V voltage, the voltage difference between the two transistors Y1 and Y2 becomes the Vs voltage. Therefore, each of the transistors Y1 and Y2 can use a transistor having a voltage resistance of Vs / 2.

In mode 3 M3, transistors Y1 and Y2 are turned on and transistors Y3 are turned off, as shown in FIG. 5C, power supply Vs, transistors Y1, Y2, Yn, and capacitor Cs2. The resonance occurs in the path of the Y electrode of the inductor Ly, the diode D1, the transistor Sch, and the panel capacitor Cp (③). Then, the energy charged in the capacitor Cs2 is injected into the Y electrode through the inductor L so that the voltage of the Y electrode increases from the Vs voltage to the 2Vs voltage.

Next, in the mode 4 M4, the transistor YH is turned on, and as shown in FIG. 5D, the power supply Vs, the transistors Y1, Y2, Yn, the capacitors Cs2, Cs1, and the transistors YH, Sch And 2Vs voltage is applied to the Y electrode through the path of the Y electrode of the panel capacitor Cp (④). At this time, since the drain voltage of the transistor Y3 becomes the Vs voltage, the drain-source voltage difference of the transistor Y1 becomes the Vs voltage. Since the source voltage of the transistor Yp becomes the Vs voltage and the drain voltage of the transistor Yp becomes the 2Vs voltage, the drain-source voltage difference of the transistor Yp also becomes the Vs voltage. Therefore, the transistors Y3 and Yp may use transistors having a voltage of Vs. In addition, since the source voltage of the transistor YL becomes the Vs voltage and the drain voltage of the transistor Scl becomes the 2Vs voltage, the voltage difference across the two transistors Scl and YL becomes the Vs voltage. Therefore, each of the transistors Scl and YL may use a transistor having a breakdown voltage of Vs / 2 voltage.

In mode 5 (M5), transistor Scl is turned on and transistors Sch, YH are turned off, so that the Y electrode, transistor Scl, inductor Ly of panel capacitor Cp, as shown in FIG. 5E. The resonance occurs in the path of the diode D2, the capacitor Cs2, the transistors Yn, Y2, Y1 and the power supply Vs (5). Then, as the energy stored in the panel capacitor Cp is recovered to the power supply Vs through the inductor Ly, the voltage of the Y electrode decreases from the 2Vs voltage to the Vs voltage.

In mode 6 (M6), transistor Y3 is turned on and transistors Y1 and Y2 are turned off, so that the Y electrode, panel transistor Scl, diode D2 of panel capacitor Cp, as shown in FIG. 5F. The resonance occurs in the path of the inductor Ly, the capacitor Cs2, the transistors Yn, Y3, and the ground terminal 0 (6). Then, as the energy stored in the panel capacitor Cp is recovered to the ground terminal 0 through the inductor L, the voltage of the Y electrode decreases from the Vs voltage to the 0V voltage. At this time, the transistors Y1 and Yp are turned on to respectively supply the capacitors Cs1 and Cs2 through the paths of the power supply Vs, the transistors Y1 and Yp, the capacitors Cs1 and Cs2, the transistors Yn and Y3, and the ground terminal. Charge the voltage to Vs / 2.

In mode 7 M7, transistors Yp and Y2 are turned on and transistors Yn are turned off, so that the Y electrode, panel transistor Scl, diode D2 of panel capacitor Cp, as shown in FIG. 5G. The resonance occurs in the path of the inductor Ly, the capacitor Cs1, the transistors Yp, Y2, Y3 and the ground terminal 0 (⑦). Then, as the energy stored in the panel capacitor Cp is recovered to the ground terminal 0 through the inductor L, the voltage of the Y electrode decreases from the voltage of 0V to the voltage of -Vs.

Finally, in mode 8 (M8), transistor YL is turned on, as shown in FIG. 5H, Y electrode of panel capacitor Cp, transistors Scl, YL, capacitors Cs2, Cs1, and transistor ( The voltage -Vs is applied to the Y electrode through the path of Yp, Y2, Y3) and ground terminal 0 (8). At this time, since the source voltage of the transistor Y1 becomes the 0V voltage, the drain-source voltage difference of the transistor Y1 becomes the Vs voltage. Since the source voltage of transistor Yn becomes -Vs and the drain voltage of transistor Yn becomes 0V, the drain-source voltage difference of transistor Yn also becomes Vs. Therefore, the transistors Y1 and Yn may use transistors having a voltage of Vs. In addition, since the drain voltage of the transistor YH becomes 0V and the source voltage of the transistor Sch becomes -Vs, the voltage difference across the two transistors Sch and YH becomes Vs. Therefore, each of the transistors Sch and YH may use a transistor having a breakdown voltage of Vs / 2 voltage.

As described above, according to the exemplary embodiment of the present invention, the two transistors Sch and Scl and the transistors YH and YL of the scan IC 411 may have a high level voltage (2 Vs) and a low level voltage (−Vs) of a sustain discharge pulse. Transistors having a voltage of 1/6, i.e., Vs / 2, with a breakdown voltage can be used, and transistors Y1, Y2, Y3, Yp, and Yn are the high level voltage (2Vs) of the sustain discharge pulse. Since a transistor having one third of the voltage corresponding to the difference between the low level voltage (-Vs), that is, the voltage Vs can be used, the circuit cost is reduced. In the sustain period, the mode 1 to mode 8 (M1 to M8) may be repeated as many times as the weight of the corresponding subfield so that 2Vs voltage and -Vs voltage may be alternately applied to the Y electrode.

In the above, generating the driving waveform according to the first embodiment of the present invention has been described with reference to FIGS. 5A to 5H. On the other hand, in the driving waveform shown in Fig. 2, the voltage difference between each Y electrode and each X electrode alternately has a 3Vs voltage and a -3Vs voltage. At this time, if the voltage magnitude of 3Vs is equal to the voltage magnitude of Vs', a driving waveform as shown in FIGS. 6A to 6C may be applied. 6A to 6C are diagrams illustrating driving waveforms of the plasma display device according to the second to fourth embodiments, respectively.

As shown in Fig. 6A, during the sustain period, the plurality of Y electrodes Y1 to Yn and the plurality of X electrodes X1 to Xn alternately have a high level voltage Vs' and a low level voltage 0V. The sustain discharge pulse may be applied in reverse phase. 6B, the high level voltage Vs '/ 2 and the low level voltage Vs' / 2 are alternated between the plurality of Y electrodes Y1 to Yn and the plurality of X electrodes X1 to Xn. The branch may also apply the sustain discharge pulse in the opposite phase. That is, the scan electrode driver 400 sustains discharge having a plurality of Y electrodes Y1 to Yn alternately having a high level voltage Vs' or Vs' / 2 and a low level voltage 0V or -Vs' / 2. The pulses are applied as many times as the weights of the corresponding subfields, and the sustain electrode driver 500 supplies sustain discharge pulses to the plurality of X electrodes X1 to Xn and the sustain discharge pulses applied to the Y electrodes Y1 to Yn. Apply in reverse phase. Even in this manner, the voltage difference between each Y electrode and each X electrode alternates between the Vs 'voltage and the -Vs' voltage, whereby the sustain discharge is repeatedly generated a predetermined number of times in the discharge cell to be turned on.

In addition, unlike the second and third embodiments of the present invention, the sustain discharge pulse may be applied to only one of the X electrode and the Y electrode. That is, as shown in FIG. 6C, in the sustain period, a sustain discharge pulse having a voltage of Vs 'and a voltage of -Vs' may be applied to the Y electrode while the voltage of 0V is applied to the X electrode. Even in this manner, the voltage difference between each Y electrode and each X electrode alternates between the Vs 'voltage and the -Vs' voltage, whereby the sustain discharge may be repeatedly generated a predetermined number of times in the discharge cell to be turned on.

In addition, the driving waveforms according to the second to fourth embodiments of the present invention may also be generated through the sustain discharge driving circuit 410 of FIG. 3. Specifically, in the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to a power supply 2Vs' / 3 which supplies a voltage of 2Vs' / 3, and the source of the transistor Y1 is Vs' / 3. When connected to a power supply Vs '/ 3 that supplies a voltage, a sustain discharge pulse having an alternating voltage of Vs' and 0V can be applied to the Y electrode through the path shown in FIGS. 5A to 5H. In the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to the power supply Vs' / 6 which supplies the voltage Vs' / 6, and the source of the transistor Y3 is connected to -Vs' / 6. When connected to a power supply (-Vs' / 6) that supplies a voltage, a sustain discharge pulse having alternating voltages Vs' / 2 and -Vs' / 2 is applied to the Y electrode through the path shown in FIGS. 5A to 5H. Can be authorized. In the sustain discharge driving circuit 410 of FIG. 3, the drain of the transistor Y1 is connected to the power supply Vs' / 3 which supplies the voltage Vs' / 3, and the source of the transistor Y3 is -Vs' / 3 voltage. When connected to the power supply (-Vs' / 3), the sustain discharge pulse having the voltage Vs' and -Vs' alternately applied to the Y electrode can be applied to the Y electrode through the path shown in FIGS. 5A to 5H. At this time, a 0V voltage is applied to the X electrode.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the transistor having a low breakdown voltage can be used in the sustain discharge driving circuit, the circuit cost can be reduced.

Claims (16)

A plurality of first electrodes, A first transistor having a first end connected to a first power supply for supplying a first voltage, A second transistor having a first end connected to a second power supply for supplying a second voltage lower than the first voltage; A third transistor having a first end connected to a second end of the first transistor and a second end connected to a second end of the second transistor, A first capacitor charged with a third voltage and having a first end connected to a second end of the first transistor, A second capacitor charged with a fourth voltage and having a first end connected to a second end of the first capacitor, A fourth transistor connected between the first end of the first capacitor and the second end of the first transistor, A fifth transistor connected between the second end of the second capacitor and the second end of the second transistor, A plurality of sixth transistors each having a first end connected to the plurality of first electrodes, A plurality of seventh transistors having first ends connected to the plurality of first electrodes, respectively; An eighth transistor connected between a second end of the sixth transistor and a first end of the first capacitor, A ninth transistor connected between a second end of the plurality of seventh transistors and a second end of the second capacitor, A rising path connected between second ends of the plurality of sixth transistors and contacts of the first and second capacitors to increase voltages of the plurality of first electrodes, and A falling path connected between a second end of the plurality of seventh transistors and contacts of the first and second capacitors to reduce voltages of the plurality of first electrodes; Plasma display device comprising a. The method of claim 1, The upward path is, A first inductor and a first diode connected in series between the contacts of the first and second capacitors and the second ends of the plurality of sixth transistors, The descending path is, And a second inductor and a second diode connected in series between the contacts of the first and second capacitors and the second ends of the seventh transistors. The method of claim 2, And the first and second inductors are the same inductor. The method of claim 3, And the third voltage and the fourth voltage are respectively charged with an intermediate voltage between the first voltage and the second voltage. The method of claim 3, Wherein the first voltage is a positive voltage and the second voltage is a ground voltage. The method of claim 3, And the first and second voltages are positive voltages. The method of claim 3, Wherein the first voltage is a positive voltage and the second voltage is a negative voltage. The method according to any one of claims 1 to 7, The second, third, fourth and sixth transistors are turned on during a first period, the second, fifth, and sixth transistors are turned on during a second period, and the third period is The first, third, fifth, and sixth transistors are turned on, the first, third, sixth, and eighth transistors are turned on for a fourth period, and the first, third, fifth, and sixth transistors are turned on for a fourth period. Setting the third, fifth and seventh transistors to the on state, turning the second, fifth and seventh transistors to the on state for a sixth period and the second, third, fourth and A controller configured to set a seventh transistor to a turn on state and to set the second, third, fourth and ninth transistors to a turn on state for an eighth period; Plasma display device further comprising. The method of claim 8, And in the sixth period, the first transistor is turned on to charge the third voltage and the fourth voltage to the first and second capacitors, respectively. In the method of driving a plasma display device including a first electrode for performing a display operation, Applying a fourth voltage to the first electrode through a first power supply for supplying a first voltage and first and second capacitors respectively charging a second voltage and a third voltage, Increasing the voltage of the first electrode through the first power supply and the first inductor connected to the first capacitor and the first electrode, Further increasing the voltage of the first electrode through the first power source, the second capacitor, and the first inductor; Further increasing a voltage of the first electrode through a second power supply that supplies a fifth voltage higher than the first voltage, the second capacitor, and the first inductor; Applying the sixth voltage to the first electrode through the second power supply and the first and second capacitors, Reducing the voltage of the first electrode through a second inductor, the second capacitor, and the second power source connected to the first electrode; Further reducing the voltage of the first electrode through the second inductor, the second capacitor and the first power source, and Further reducing the voltage of the first electrode through the second inductor, the first capacitor, and the second power source Method of driving a plasma display device comprising a. The method of claim 10, Further reducing the voltage of the first electrode through the second inductor, the second capacitor and the first power source, And charging the first and second capacitors to the third voltage and the fourth voltage, respectively, through the second power supply. The method of claim 11, And the first and second inductors are the same inductor. In the driving device of the plasma display device including a plurality of first electrodes and a plurality of second electrodes, A first capacitor, A second capacitor having a first end connected to the first end of the first capacitor, And a plurality of first output terminals are respectively connected to the plurality of first electrodes, and the voltage of the second input terminal is connected to a corresponding first electrode of the plurality of first electrodes during an address period. Scanning integrated circuits that selectively apply; A first transistor connected between a first input end of the scan integrated circuit and a first end of the first capacitor, A second transistor connected between a second input terminal of the scan integrated circuit and a first terminal of the second capacitor, A rising path connected between a first input terminal of the scan integrated circuit and a contact point of the first and second capacitors to increase a voltage of the plurality of first electrodes, A falling path connected between a second input terminal of the scan integrated circuit and the contacts of the first and second capacitors to reduce voltages of the plurality of first electrodes, and Switching means for selectively applying a first voltage and a second voltage lower than the first voltage to a second end of the first or second capacitor Driving device comprising a. The method of claim 13, Increasing the voltage of the first electrode through the first capacitor and the rising path in a state where the second voltage is applied to the second end of the first capacitor, Further increasing the voltage of the first electrode through the second capacitor and the rising path in the state that the second voltage is applied to the second end of the second capacitor, After further increasing the voltage of the first electrode through the second capacitor and the rising path in a state where the first voltage is applied to the second end of the second capacitor, In the state where the first voltage is applied to the second terminal of the second capacitor, the first transistor is turned on to apply a third voltage to the first electrode. Reducing the voltage of the first electrode through the second capacitor and the falling path in the state where the first voltage is applied to the second end of the second capacitor, Further reducing the voltage of the first electrode through the second capacitor and the falling path in the state that the second voltage is applied to the second end of the second capacitor, After further reducing the voltage of the first electrode through the first capacitor and the falling path in the state that the second voltage is applied to the second end of the first capacitor, And a fourth voltage lower than the third voltage by turning on the second transistor while applying the second voltage to the second terminal of the first capacitor. The method of claim 14, Further comprising: an inductor having a first end connected to the contacts of the first and second capacitors, The rising path includes a first diode connected between a second end of the inductor and a first input end of the scan integrated circuit, And the falling path includes a second diode connected between the second end of the inductor and the second input end of the scan integrated circuit. The method of claim 14, The upward path is, A first inductor and a first diode connected in series between the contacts of the first and second capacitors and the first input terminal of the scan integrated circuit, The descending path is, And a second inductor and a second diode connected in series between the contacts of the first and second capacitors and the second input terminal of the scan integrated circuit.

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