KR20080021394A - Circuit of controlling redundancy in nand flash memory - Google Patents

Abstract

A redundancy control circuit of a NAND flash memory is provided to control on/off of a number of address fuse blocks with one guard fuse block in order to reduce area occupied by the guard fuse block. A number of address fuse blocks(210-250) store a column address of a defective cell. A guard fuse block(100) is connected to the address fuse blocks in common, and enables the address fuse blocks according to cutting of a guard fuse(GF10). The guard fuse block includes the guard fuse, three inverters(IN10-IN30), a first transistor(MN1) and a second transistor(MN2). The guard fuse is connected between a power supply voltage and a first node. Three inverters are serially connected between the first node and a second node connected to the address fuse blocks in common. The first transistor is connected between the first node and a ground voltage, and has a gate connected to an output node of a first inverter. The second transistor has a gate connected to the first node, and a drain and a source connected to the ground voltage.

Description

Redundancy control circuit of NAND flash memory {Circuit of controlling redundancy in nand flash memory}

1 is a block diagram showing the structure of a conventional NAND flash memory.

FIG. 2 is a detailed circuit diagram of the redundancy control circuit of FIG. 1.

3 is a detailed circuit diagram of a redundancy control circuit of a NAND flash memory according to an embodiment of the present invention.

4 is a detailed circuit diagram of a portion of FIG. 3.

* Brief description of the main parts of the drawings *

100: guard fuse block 210 to 230: address fuse block

The present invention relates to a redundancy control circuit of a NAND flash memory, and more particularly, to a redundancy control circuit of a NAND flash memory capable of reducing chip size by reducing a guard fuse block used for a repair operation.

In general, a NAND flash memory device adds a redundancy cell to a main memory cell in order to improve yield, and thus, if a defective memory cell exists, the defective cell is removed. The repair method replaces the redundancy cells.

1 is a block diagram showing the structure of a conventional NAND flash memory.

Referring to FIG. 1, a NAND flash memory includes a memory cell array 10, a redundancy cell array 20, a page buffer and a column decoder 30, a redundancy decoder 40, and a redundancy control unit 50. It is composed.

The memory cell array 10 includes a plurality of memory cells (not shown) capable of storing data, and the redundancy cell array 20 includes a memory cell that replaces a cell in which the memory cell array 10 has failed. It is configured by.

The page buffer and the column decoder 30 are used for programming, verifying, reading, and erasing input data, and the redundancy decoder 40 is configured as a redundant cell array connected to a corresponding address when the input address is a repaired address. 20) is used to select.

The redundancy controller 50 determines whether the input address is the address of the repaired cell, and informs the page buffer and column decoder 30 or the redundancy decoder 40 of this.

The redundancy control unit 50 includes a guard fuse block and an address fuse block. The guard fuse block includes a guard fuse for selecting whether to use the address fuse block, and cuts the guard fuse to activate the address fuse block. If the address fuse block is a repaired address, the address fuse block generates a current discharge path and outputs repair address information.

The redundancy control unit 50 uses a method of replacing all memory cells of the same row or column with redundancy cells for a single memory cell failure due to the characteristics of the NAND cell, and the redundancy control unit 50 redundancy with respect to the column. Replace the cell array.

The redundancy control circuit of the redundancy control unit 50 is configured as follows.

FIG. 2 is a detailed circuit diagram of the redundancy control circuit of FIG. 1.

Referring to FIG. 2, the redundancy control circuit includes a guard fuse block 51 and an address fuse block 52.

The guard fuse block 51 is also referred to as a master fuse block and performs a function of enabling the address fuse block 52. The guard fuse block 51 includes a guard fuse GF, first to third inverters IN1 to IN3, an NMOS transistor N2, and an NMOS capacitor N1.

The address fuse block 52 includes first to eighth fuses AF1 to AF8, third to eleventh NMOS transistors N3 to N11, PMOS transistors P1, and fourth and fourth transistors each having twice the column address. It consists of 5 inverters (IN4, IN5).

2 shows a redundancy address fuse circuit in the case of four column addresses (<3: 0>).

To repair a defective cell in a NAND flash memory device, eight redundancy line addresses (RLA) <3: 0> and four RLAb <3: 0> are required, for a total of eight fuses (AF1 to AF8). The address fuse block 52 stores address information of a defective cell through fuse cutting.

In FIG. 2, when a defect occurs in a memory cell having an address RLA <3: 0> of '0101' and a repair is to be performed, the first fuse AF1, the fourth fuse AF4, and the fifth The fuse AF5 and the eighth fuse AF8 are cut to store the defective cell address.

Next, when the guard fuse GF is cut, the redundancy control circuit is turned off, and the power is turned on again, the node A becomes the low in the guard fuse block 51, and thus the node B becomes high. The eleventh NMOS transistor N11 is turned on, and a path of a current discharge path is provided to the address fuse block 52.

In the address fuse block 52, a current discharge path is formed in the direction of an arrow P from the node C so that current flows. At this time, the repair signal REPb becomes low due to the current of the node C, and sends out information that the corresponding address is the repaired address.

By the above process, the corresponding address is accessed toward the repair cell. In this way, the redundancy control circuit is configured to receive the information of the column-address to be repaired and to blow out the fuse corresponding to the column address to output the repaired information.

In the above redundancy control circuit, one guard fuse block is connected to each of the address fuse blocks. Therefore, if there are 32 or 64 address fuse blocks, there are 32 or 64 guard fuse blocks. Therefore, the larger the number of address fuse blocks, the greater the number of guard fuse blocks, and the area occupied by the guard fuse blocks is a problem that cannot be ignored.

Therefore, the technical problem to be achieved by the present invention is to reduce the area occupied by the guard fuse block in the redundancy control circuit redundancy control circuit of the NAND flash memory to control the on and off of a plurality of address fuse block with one guard fuse block To provide.

Redundancy control circuit of the NAND flash memory according to an aspect of the present invention for achieving the above technical problem,

A plurality of address fuse blocks for storing column addresses of defective cells; And a guard fuse block commonly connected to the plurality of address fuse blocks to enable the plurality of address fuse blocks according to whether a guard fuse is cut.

The guard fuse block may include a guard fuse connected between a power supply voltage and a first node; First to third inverters connected in series between the first node and a second node commonly connected to the plurality of address fuse blocks; A first transistor connected between the first node and a ground voltage and having a gate connected to the output node of the first inverter; A first node and a gate are connected, and a drain and a source include a second transistor connected to a ground voltage.

The address fuse block may include: a first switching device unit including a plurality of switching units connected in series between a third node and a fourth node connected in parallel to a power supply voltage, respectively, and operated by a plurality of address signals; A second switching element unit including a plurality of switching units connected in series between the third node and the fourth node in parallel and respectively operated by inverted signals of the plurality of address signals; And a third switching element connected to a second node of the guard fuse block to connect a current discharge path generated by the first and second switching element units to a ground voltage.

In this case, the switching unit may include a transistor operated by each of the plurality of addresses and the inverted signal corresponding thereto; It characterized in that it comprises an address fuse connected in series to the bottom of the transistor.

In the first address fuse block for preventing the generation of the current discharge path among the address fuse blocks, all of the address fuses connected to the lower end of the switching element operated by at least one address signal and an inverted signal corresponding thereto are cut. It is characterized by.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a detailed circuit diagram of a redundancy control circuit of a NAND flash memory according to an embodiment of the present invention.

Referring to FIG. 3, a redundancy control circuit of a NAND flash memory according to an exemplary embodiment of the present invention may include a guard fuse block 100 and a plurality of first to Nth address fuse blocks commonly connected to the guard fuse block 100. It is configured to include (210 ~ 250).

The guard fuse block 100 includes a guard fuse GF10, first and third inverters IN10 to IN30, and first to second NMOS transistors MN1 and MN2.

In the guard fuse block 100, a guard fuse GF10 is connected between a power supply voltage and a node N1, and a node connected to the node N1 and the first to Nth address fuse blocks 210 to 250. The first to third inverters IN10 to IN30 are connected in series between the N2s.

The second NMOS transistor MN2 is connected between the node N1 and the ground voltage, and the gate of the second NMOS transistor MN2 is connected to the contact point of the first inverter IN10 and the second inverter IN20. do.

The second NMOS transistor MN1 is connected between the node N1 and the ground voltage. The node N1 and the gate are connected, and the drain and the source are commonly connected to the ground voltage.

The guard fuse block 100 configured as described above is also referred to as a master fuse block and performs a function of enabling the first to Nth address fuse blocks 210 to 250.

Each of the first to Nth address fuse blocks 210 to 250 may include a plurality of fuses (not shown), a plurality of NMOS transistors (not shown), a PMOS transistor (not shown), and a plurality of inverters each configured to have a multiple of a column address. (Not described in detail) and each address fuse block stores repair address information through fuse cutting to repair a defective cell.

In general, each of the address fuse blocks is connected to a separate guard fuse block to enable / disable control. In an embodiment of the present invention, even if one address fuse block is enabled, all of the address fuse blocks, that is, the first through the first through fuse blocks, are enabled. The guard fuse GF10 of the guard fuse block 100 to which the N-th address fuse blocks 210 to 250 are commonly connected is cut.

When the common guard fuse GF10 is cut as described above, all of the first to Nth address fuse blocks 210 to 250 are enabled and stored, and a current discharge path for the repair address is generated to generate a repair signal. Will print.

In the above configuration, if the first to N-th address fuse blocks 210 to 250 store respective repair addresses, there is no problem because all address fuse blocks must be enabled, but any one of the address fuse blocks may be removed. If you need to enable it, control it as follows:

According to an exemplary embodiment of the present invention, a method of disabling a corresponding address fuse block may be used by cutting a pair of fuses for an arbitrary address address in an address fuse block that is not enabled.

As described above, the address fuse blocks for disabling among the first to Nth address fuse blocks 210 to 250 which are commonly connected to one guard fuse block 100 will be described in more detail.

4 is a detailed circuit diagram of a portion of FIG. 3.

4 is a detailed circuit diagram of the first address fuse block 210 when the first address fuse block 210 is disabled. The guard fuse block 100 of FIG. 3 is connected to the node N2. (Not shown).

Referring to FIG. 4, the first address fuse block 210 includes a PMOS transistor MP1, third to eleventh NMOS transistors MN3 to MN11, first to eighth address fuses AF10 to AF80, and a first to eighth address fuses AF10 to AF80. And fourth and fifth inverters IN40 and IN50.

In the first address fuse block 210, the PMOS transistor MP1 is connected between the power supply voltage and the node N3, and the PMOS transistor MP1 is turned on by the ground voltage.

A switching means composed of a transistor operated by an address signal between the node N3 and the node N4 and an address fuse connected to the lower end of the transistor is connected side by side.

That is, each switching means is connected to the bottom of the third, fifth, seventh and ninth NMOS transistors MN3, MN5, MN7 and MN9 which are respectively operated by the address RLA <0: 3> signals. The first, third, fifth and seventh address fuses AF10, AF30, AF50, and AF70 are connected to each other, and switching means are configured in series between a node N3 and a node N4.

In addition, between the node N3 and the node N4, a switching means composed of a transistor operated by an inverted signal to the address signal and an address fuse connected to the lower end of the transistor is connected side by side.

That is, each switching means is connected to the fourth, sixth, eighth and tenth NMOS transistors MN4, MN6, MN8 and MN10, respectively, which are operated by the address RLAb <0: 3> signals, respectively. The second, fourth, sixth, and eighth address fuses A210, AF40, AF60, and AF80 may be connected, and switching means may be connected in series between the node N3 and the node N4.

In addition, the repair signal REPb is output through the node N43, and is configured to be output through the fourth and fifth inverters IN40 and IN50.

Finally, an eleventh NMOS transistor 11 operated by a signal of the node N2 of the guard fuse block 100 is connected between the node N4 and the ground voltage to establish a current discharge path for outputting a repair signal. To be created.

The first address fuse block 210 is configured for four address signals RLA <0: 3>, and the other second to Nth address fuse blocks 220 to 250 are configured in the same circuit. Each address fuse block stores unique repair address information by cutting address fuses AF10 to AF80.

As shown in FIG. 4, when the guard fuse GF10 of the guard fuse block 100 is cut, the eleventh NMOS transistor MN11 is turned on by the node N2 in the first address fuse block 210. Therefore, the seventh and eighth address fuses AF70 and AF80 corresponding to the addresses RLA <3> and RLAb <3> are cut in order to block and disable the current discharge path for the repair signal output. .

When the seventh and eighth address fuses AF70 and AF80 are cut as described above, the current discharge path can be controlled to prevent any current discharge path from occurring at any address.

That is, in the case of the address fuse block to be disabled among the first to Nth address fuse blocks 210 to 250 connected to one guard fuse block 100, one of one address RLA <3: 0> may be used. The current discharge path is blocked by simultaneously cutting a pair of address fuses corresponding to

In FIG. 4, the pair of address fuses AF70 and AF80 corresponding to the address RLA <3> are cut to prevent the current discharge path of the first address fuse block 210 from being generated.

Control can be performed by cutting a pair of address fuses corresponding to one address signal, such as the seventh and eighth address fuses AF70 and AF80.

Therefore, the use of only one guard fuse block for a plurality of address fuse blocks reduces the number of devices, and the control of each address fuse block can be simplified.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the redundancy control circuit of the NAND flash memory according to the present invention enables a single guard fuse block to control a plurality of address fuse blocks, thereby reducing the circuit area by reducing the guard fuse block, thereby reducing the chip size. have.

Claims (5)

A plurality of address fuse blocks for storing column addresses of defective cells; And The plurality of address fuse blocks are connected in common, and a guard fuse block capable of enabling the plurality of address fuse blocks according to whether a guard fuse is cut or not. Redundancy control circuit of the NAND flash memory comprising a. The method of claim 1, The guard fuse block, A guard fuse connected between the power supply voltage and the first node; First to third inverters connected in series between the first node and a second node commonly connected to the plurality of address fuse blocks; A first transistor connected between the first node and a ground voltage and having a gate connected to the output node of the first inverter; And a second transistor connected to a first node and a gate, and having a drain and a source connected to a ground voltage. The method of claim 2, The address fuse block, A first switching element unit including a plurality of switching units connected in series between a third node and a fourth node connected in parallel with a power supply voltage, respectively, and operated by a plurality of address signals; A second switching element unit including a plurality of switching units connected in series between the third node and the fourth node in parallel and respectively operated by inverted signals of the plurality of address signals; And a third switching element connected to a second node of the guard fuse block to connect a current discharge path generated by the first and second switching element units to a ground voltage. Redundancy Control Circuit. The method of claim 3, wherein The switching unit, Transistors each operated by the plurality of addresses and corresponding inverted signals; Redundancy control circuit of the NAND flash memory, characterized in that it comprises an address fuse connected in series to the lower end of the transistor. The method according to claim 3 or 4, Among the address fuse blocks, a first address fuse block for preventing a current discharge path from being generated may include: The redundancy control circuit of the NAND flash memory, characterized in that all of the address fuses connected to the lower end of the switching element operated by one or more address signals and corresponding inverted signals are cut.

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