KR100953028B1 - IO repair circuit and non volatile device having the same - Google Patents

Abstract

The present invention relates to an IO repair circuit of a nonvolatile memory device, comprising: first and second switching devices connected between a power supply voltage node and a ground node and operated by an enable signal, and having opposite characteristics to each other; IO circuits comprising an IO initialization circuit connected between the first and second switching elements and including a first fuse for setting an initial value of the IO.

Repair, IO, Fuse, Inverter

Description

IO repair circuit and nonvolatile memory device having the same {IO repair circuit and non volatile device having the same}

The present invention relates to a nonvolatile memory device, and more particularly, to an IO repair circuit capable of storing IO information with only one fuse and a nonvolatile memory device having the same.

In general, a nonvolatile flash memory device adds a redundancy cell to a main memory cell in order to improve yield. The repair method is replaced by a redundancy cell.

When the redundancy of the memory element is input, the redundancy detection circuit detects the address signal and outputs a repair control signal indicating whether the redundancy is repaired. The redundancy detection circuit stores repair address information programmed by the fuse element.

Repair of the nonvolatile memory device is performed in units of columns. The redundancy column is replaced in place of the failed column. At this time, IO (input output) for data input and output of the redundancy column is also repaired.

Redundancy for IO Repair IO uses a fuse to store initial information about whether or not it is used. At this time, one IO is connected to a fuse connected to the ground node (GND), and a fuse connected to the power supply voltage (VDD). If the fuse connected to the ground node is blown, '1' is input to the IO as an initial value, indicating that the corresponding redundancy IO does not operate. On the contrary, if the fuse connected to the power supply is blown, '0' is input to the IO as an initial value, indicating that the corresponding redundancy IO is operating.

This requires two fuses per IO. Therefore, the greater the number of redundancy IOs, the greater the number of fuses required. Since the fuse takes up a large area, the more fuses used, the larger the total size of the nonvolatile memory device.

Accordingly, an aspect of the present invention is to provide an IO repair circuit capable of reducing an area by reducing the number of fuse circuits for storing IO repair information and a nonvolatile memory device having the same.

IO repair circuit according to a feature of the present invention,

It is connected between a power supply voltage node and a ground node, and is operated by an enable signal, and is connected between the first and second switching elements having opposite characteristics and the first and second switching elements, and thus an initial value of IO. IO initialization circuits comprising a first fuse for setting the circuit.

The enable signal is initially input at a low level and is changed to a high level.

The first switching device is a PMOS transistor, the second switching device is characterized in that the NMOS transistor.

When the IO is not repaired, the fuse is cut.

The fuse is connected between a source terminal of the PMOS transistor and a drain terminal of the NMOS transistor.

The initial value of the IO is determined according to the voltage level of the source terminal of the PMOS transistor.

And a latch circuit for storing an initial value of the IO.

Nonvolatile memory device according to a feature of the present invention,

It is connected between a power supply voltage node and a ground node, and is operated by an enable signal, and is connected between the first and second switching elements having opposite characteristics and the first and second switching elements, and thus an initial value of IO. And an IO repair circuit including IO initialization circuits including a first fuse for setting the circuit.

The enable signal is initially input at a low level and is changed to a high level.

The first switching device is a PMOS transistor, the second switching device is characterized in that the NMOS transistor.

When the IO is not repaired, the fuse is cut.

The fuse is connected between a source terminal of the PMOS transistor and a drain terminal of the NMOS transistor.

The initial value of the IO is determined according to the voltage level of the source terminal of the PMOS transistor.

And a latch circuit for storing an initial value of the IO.

Nonvolatile memory device according to another aspect of the present invention,

A main cell array comprising a plurality of cells for data storage; A redundancy cell array configured to include a plurality of cells for repairing a defective cell separately from the main cell array; A page buffer unit configured to program, verify, and read data of the main cell array and the redundant cell array; And an IO controller including an IO controlling a data entry and exit path of the page buffer unit connected to the redundancy cell array, and including an IO repair circuit configured to store initial information on whether a corresponding IO is used or not. The repair circuit is connected between a power supply voltage node and a ground node and operated by an enable signal, and is connected between the first and second switching elements having opposite characteristics and the first and second switching elements. And an IO initialization circuit including a first fuse for setting an initial value of the IO.

And a latch circuit for storing the initial value of the IO of the IO initialization circuit.

As described above, the IO repair circuit and the nonvolatile memory device having the same according to the present invention reduce the number of fuses by reducing the number of fuses for storing information of the IO repair circuit to one, thereby reducing the number of fuses and the area occupied by the fuse. The total area of the volatile memory device can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the nonvolatile memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an IO controller 140, an X decoder 150, and a voltage providing unit ( 160 and the controller 170.

The memory cell array 110 includes a main cell array 111 and a redundancy cell array 112, and the page buffer unit 120 includes a main page buffer unit 121 and a redundancy page buffer unit 122. The IO controller 140 includes a main IO controller 141 and a redundant IO controller 142.

The main cell array 111 includes memory cells for data storage, and the memory cells are connected to bit lines and word lines. The redundancy cell array 112 includes memory cells and operates by replacing a failed column in the main cell array 110.

The main page buffer unit 121 is connected to a bit line of the main cell array 110 and includes page buffer circuits for storing data to be programmed in a memory cell or reading and storing data programmed in the memory cell.

The redundancy page buffer unit 122 includes page buffer circuits that are connected to and operate on the bit lines of the redundancy cell array 112.

The Y decoder 130 provides an input / output path of the page buffer circuit by the control signal, and the main IO controller 141 includes an IO for providing a path for data input / output. The IO is actually connected to an IO pin (Pin) that is connected to the outside, and consists of eight.

The redundancy IO controller 142 includes IO for data input and output of the redundancy page buffer unit 122.

The X decoder 150 selects a word line of the memory cell array 110 and connects the word line of the memory cell array 110 to an operating voltage line according to a control signal. The voltage provider 160 generates a voltage for operation according to the control signal and outputs the voltage to the operation voltage line.

The controller 170 performs necessary operation control according to the input command.

The redundancy IO control unit 142 includes a plurality of redundancy IO, a fuse is connected as follows, and whether information is used or not depending on whether the fuse is cut.

2 is a circuit diagram of a redundancy IO control unit.

2 illustrates some circuits of a redundancy IO controller of a nonvolatile memory device currently being used.

The redundancy IO control unit 200 includes four redundancy IOs (IO <0: 3>), and includes first to fourth PMOS transistors P1 to P4, first to fourth NMOS transistors N1 to N4, and One inverter IN1 and first to eighth fuses F1 to F8 are included.

The first fuse F1 and the first PMOS transistor P1 are connected between the power supply voltage VDD node and the first IO IO <0>. The second fuse F2 and the first NMOS transistor N1 are connected between the ground node GND and the first fuse IO <0>.

The third fuse F3 and the second PMOS transistor P2 are connected between the power supply voltage VDD and the second IO IO <1>, and the fourth fuse F4 and the second NMOS transistor N2. Is connected between the ground node GND and the second fuse IO <1>.

The fifth fuse F5 and the third PMOS transistor P3 are connected between the power supply voltage VDD and the third IO IO <2>, and the sixth fuse F6 and the third NMOS transistor N3. Is connected between the ground node GND and the third fuse IO <2>.

The seventh fuse F7 and the fourth PMOS transistor P4 are connected between the power supply voltage VDD node and the fourth IO IO <3>, and the eighth fuse F8 and the fourth NMOS transistor N4. ) Is connected between the ground node GND and the fourth IO (IO <3>).

The enable signal EN is input to the gates of the first to fourth NMOS transistors N1 to N4. The first inverter IN1 inverts the enable signal. In addition, an output signal of the first inverter IN1 is input to the gates of the first to fourth PMOS transistors P1 to P4.

Therefore, when power is applied to the nonvolatile memory device and the enable signal EN is input at a high level, both of the first to fourth NMOS transistors N1 to N4 and the first to fourth PMOS transistors P1 to P4 are all. It is turned on.

Initial values of the first to fourth IOs IO <0: 3> are set according to the cutting states of the first to eighth fuses F1 to F8.

The IO used by the repair is used as the initial value, and a value of '0' is input. The unused IO, because the repair is not performed, should have the value '1' as the initial value. Therefore, if the first and second IOs IO <0: 1> are used by the repair, the first and third fuses F1 and F3 are cut. If the remaining third and fourth IOs IO <2: 3> are not used, the sixth and eighth fuses F6 and F8 are cut.

When the enable signal EN is input in the cut state as described above, the first and second IOs IO <0: 1> are connected to the ground node GND, and a value of '0' is input. And a fourth IO (IO <2: 3>) is connected to a power supply voltage (VDD) node to input a value of '1'.

As described above, it is possible to determine whether the IO is operating by inputting an initial value to the IO used during the initial operation.

However, the above method requires a fuse connected to the power supply voltage VDD and the ground node GND for one IO. Therefore, if the number of redundancy IO is large, so many fuses are needed.

Therefore, the number of fuses is reduced by using the following redundancy IO circuit.

3A is a partial circuit diagram of an IO fuse unit according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, an IO fuse unit 300 included in a redundant IO controller according to an embodiment of the present invention has first to fourth IOs (IO <0: 3>), and includes first to fourth PMOS transistors. P10 to P40, first to fourth NMOS transistors N10 to N40, and first to fourth fuses F10 to F40.

The first PMOS transistor P10, the first fuse F10, and the first NMOS transistor N10 are connected in series between a power supply voltage VDD node and a ground node GND, and the second PMOS transistor P20. And the second fuse F20 and the second NMOS transistor N20 are also connected in series between the power supply voltage VDD node and the ground node GND.

In addition, the third PMOS transistor P30, the third fuse F30, and the third NMOS transistor N30 are connected in series between the power supply voltage VDD node and the ground node GND, and the fourth PMOS transistor P40. ) And the fourth fuse F40 and the fourth NMOS transistor N40 are also connected in series between the power supply voltage VDD node and the ground node GND.

The first PMOS transistor P10 and the first NMOS transistor N10 have an inverter circuit form and have a first fuse F10 between a source terminal of the first PMOS transistor P10 and a drain terminal of the first NMOS transistor N10. ) Is connected to form a first IO (IO <0>) circuit.

The enable signal EN is input to the gates of the first to fourth PMOS transistors P10 to P40 and the first to fourth NMOS transistors N10 to N40.

The initial value of the first I0 (IO <0>) is input according to the signal of the node K1, which is a contact of the source terminal of the first PMOS transistor P10 and the first fuse F10. The second to third IOs (IO <1: 3>) are also constituted by circuits of the same structure. Although not shown in FIG. 3, latch circuits for maintaining the values of the nodes K1 to K4 may be connected.

The operation of the circuit will be described as follows for the first and second IO (IO <0: 1>) circuits. In this case, it is assumed that the first fuse F10 is cut and the second fuse F20 is not cut.

When power is applied to the nonvolatile memory device, the enable signal EN is initially input at a low level. When the enable signal EN is input at the low level, the first and second PMOS transistors P10 and P20 are turned on. Accordingly, the nodes K1 and K2 are at a high level, and a value of '1' is input to the first and second IOs IO <0: 1>.

Thereafter, the enable signal EN is changed back to the high level. When the enable signal EN is changed to the high level, the first and second NMOS transistors N10 and N20 are turned on, and the first and second PMOS transistors P10 and P20 are turned off.

However, the first fuse F10 is in a cutting state. Therefore, the node K1 is not connected to the ground node GND, so the high level is maintained. At this time, the latch circuit may be connected to maintain the high level of the node K1. The initial value '1' is maintained in the first IO (IO <0>).

The second fuse F20 is not cut. Therefore, the node K2 is connected to the ground node GND and changed to the low level. Therefore, the initial value of the second IO (IO <1>) is changed to '0'.

As mentioned earlier, if the initial value of IO is '0', the corresponding IO is used. If the initial value is '1', it is not used. Therefore, the first IO (IO <0>) is not used and the second IO (IO <1>) is used, and an initial value is input.

If the above circuit is used, one fuse is required for one IO, and the initial value can be input by configuring a redundant IO circuit with only the number of fuses reduced in half compared to the conventional one.

The IO fuse unit 300 includes a plurality of redundant IO controllers. As mentioned above, the latch circuit is applied to prevent the data value from changing due to the floating of the fuse with the enabled signal. In this case, the latches may be connected in common since the first IOs IO <0> in each IO fuse unit 300 are all nodes tied to the first IOs IO <0>.

FIG. 3B is a block diagram connecting the IO fuse unit and the latch of FIG. 3A.

Referring to FIG. 3B, a configuration in which IO <0: 2> output from the plurality of IO fuses 300 is commonly connected to the first to third latches L1 to L3 may be made. In this case, the area increased due to the latch is smaller than the number of fuses is reduced in half, so that it is possible to configure only a smaller area than when two conventional fuses.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

2 is a circuit diagram of a redundancy IO control unit.

3A is a partial circuit diagram of an IO fuse unit according to an exemplary embodiment of the present invention.

FIG. 3B is a block diagram connecting the IO fuse unit and the latch of FIG. 3A.

* Brief description of the main parts of the drawings *

100 nonvolatile memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: IO control unit 150: X decoder

160: voltage providing unit 170: control unit

Claims (16)

IO between a power supply node and a ground node to turn on or turn off in response to an enable signal, but connected between the first and second switching devices and the first and second switching devices that operate opposite to each other. IO fuse parts comprising first to nth (n is a natural number greater than 1) IO initialization circuits including first fuses for setting an initial value of K of the IO fuse portions (

, k is a natural number). The method of claim 1, The enable signal is initially input at a low level and is changed to a high level. The method of claim 1, And said first switching element is a PMOS transistor and said second switching element is an NMOS transistor. The method of claim 1, IO repair circuit of the first to nth (n is a natural number greater than 1) of the IO initialization circuit, characterized in that for cutting the first fuse of the IO initialization circuit connected to the IO not repaired. The method of claim 3, wherein And the first fuse is connected between a source end of the PMOS transistor and a drain end of the NMOS transistor. The method of claim 5, The initial value of the IO is an IO repair circuit, characterized in that determined according to the voltage level of the source terminal of the PMOS transistor. delete IO between a power supply node and a ground node to turn on or turn off in response to an enable signal, but connected between the first and second switching devices and the first and second switching devices that operate opposite to each other. IO fuse parts comprising first to nth (n is a natural number greater than 1) IO initialization circuits including first fuses for setting an initial value of K of the IO fuse portions (

, k is a natural number. 1. The method of claim 8, And the enable signal is initially input at a low level and is changed to a high level. The method of claim 8, And the first switching element is a PMOS transistor, and the second switching element is an NMOS transistor. The method of claim 8, And a first fuse of an IO initialization circuit connected to an unrepaired IO among the first to nth (n is a natural number greater than 1) IO initialization circuits. The method of claim 10, And the first fuse is connected between a source terminal of the PMOS transistor and a drain terminal of the NMOS transistor. The method of claim 12, The initial value of the IO is determined according to the voltage level of the source terminal of the PMOS transistor. delete A main cell array comprising a plurality of cells for data storage; A redundancy cell array configured to include a plurality of cells for repairing a defective cell separately from the main cell array; A page buffer unit configured to program, verify, and read data of the main cell array and the redundant cell array; And An IO controller including an IO controlling a data entry and exit path of the page buffer unit connected to the redundancy cell array, and including an IO repair circuit for storing initial information on whether a corresponding IO is used or not; The IO repair circuit is connected between a power supply voltage node and a ground node and operated by an enable signal, and is connected between the first and second switching devices and the first and second switching devices that operate in opposite directions. IO fuse parts comprising first to nth (n is a natural number greater than 1) IO initialization circuits including first fuses for setting an initial value of K of the IO fuse portions (

k are natural numbers). The first through nth latches are connected to the outputs of the initialization circuits, respectively. Nonvolatile memory device comprising a. delete

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