KR20080020091A - Gradation votlage generating circuit of data driver - Google Patents

Abstract

A circuit for generating a gray scale voltage of a data driver is provided to improve the reduction of a voltage due to parasite resistance by implementing compensation circuits in the circuit for generating the gray scale voltage. A circuit for generating a gray scale voltage includes resistor strings(231,232) and compensation circuits(237,238,239). The resistor strings receive first and second reference voltages through first and second nodes respectively, and generates plural gray scale voltages. The compensation circuits which are connected to the first and second nodes compensate for the rise and fall of the gray scale voltages due to parasite resistance at the first and second nodes.

Description

Gradation voltage generating circuit of data driving circuit {Gradation Votlage Generating circuit of DATA DRIVER}

1 shows a liquid crystal display device 10 having a data driving circuit according to the present invention.

2 shows a data driving circuit according to the present invention.

3 is an embodiment of a gray voltage generator circuit of the data driver circuit according to the present invention.

Figure 4 shows the simulation results for the output of the gray voltage when using the gray voltage generating circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: liquid crystal display device 100: liquid crystal panel

200: data driving circuit 400: timing control circuit

210: register 220: level shifter

230: gradation voltage generating circuit 240: decoder

250: amplifier

237,238,239: compensation circuit 233,234: reference voltages

231,232 gamma resistances 235,236 parasitic resistances

PM1, PM2: PMOS transistor NM: NMOS transistor

The present invention relates to a data driving circuit of a liquid crystal display (LCD), and more particularly, to a gray scale voltage generating circuit of a data driving circuit.

A liquid crystal display (LCD) includes a liquid crystal material having dielectric anisotropy between an alignment layer of an upper substrate on which a common electrode and a color filter are formed, and an alignment layer of a lower substrate on which a thin film transistor and a pixel electrode are formed. Injecting and changing the arrangement of the liquid crystal molecules by applying an electric voltage to the pixel electrode and the common electrode to form an electric field, thereby adjusting the transmittance of light to display an image.

Such a liquid crystal display (LCD) is thin and light, so that it is easy to miniaturize, and has a low driving voltage and power consumption, and at the same time, an image quality close to a cathode ray tube can be realized. Therefore, LCDs are used in various devices such as mobile communication terminals, monitors, and notebook computers. In particular, most mobile communication terminals represented by mobile phones use a liquid crystal display (LCD) as a display means.

The conventional gray voltage generator circuit has a gamma resistance structure. When the gamma voltage is applied, the gray voltage generator circuit divides the voltage according to the resistance ratio of the gamma resistor string and outputs the gray voltage.

However, parasitic resistors exist on the pads to which the gamma voltage is applied in the actual chip by wirings (metal, via, and CNT) to the gamma resistor string. Such parasitic resistance causes a problem of voltage drop and voltage increase in the output gray level voltage.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a data driving circuit including a gradation voltage generation circuit for solving the voltage drop and voltage rise problems of the gradation voltage due to parasitic resistance.

In the data driving circuit of the liquid crystal display of the present invention, the gray scale voltage generation circuit is supplied with a first reference voltage and a second reference voltage to a second node through a first node, wherein the first node and the second node are supplied. A resistor string for generating a plurality of gray voltages therebetween; And a compensation circuit connected to the first node and the second node, respectively, to compensate for a voltage drop and a voltage rise caused by parasitic resistances of the first node and the second node.

In this embodiment, a plurality of reference voltages between the first reference voltage and the second reference voltage are supplied to each of some of the respective nodes between the resistors in the resistor string.

In this embodiment, the compensation circuit is connected to the first node, the first compensator to compensate for the voltage drop by the parasitic resistance of the first node; And a second compensator connected to the second node to compensate for the voltage rise caused by the parasitic resistance of the second node.

The first compensator may include a PMOS transistor having a source connected to a driving voltage and a gate connected to a drain; And a first resistor connected between the first node and the drain of the PMOS transistor.

In this embodiment, the second compensator includes: an NMOS transistor having a source connected to a ground and a gate connected to a drain; And a second resistor connected between the second node and the drain of the NMOS transistor.

In the data driving circuit of the liquid crystal display device of the present invention, the gradation voltage generation circuit supplies a first reference voltage to one node, a second reference voltage to a second node, and the first node and the second node. A first resistor string connected in series between nodes to generate a plurality of gray voltages; A second resistor string configured to supply a third reference voltage to a third node, supply a fourth reference voltage to a fourth node, and be connected in series between the third node and the fourth node to generate a plurality of gray voltages; ; A first compensation circuit connected to the first node and compensating for a voltage drop caused by a parasitic resistance of the first node; A second compensation circuit connected between the second node and the third node, and configured to compensate for a voltage increase and a voltage drop caused by respective parasitic resistances at the second node and the third node; And a third compensation circuit connected to the fourth node, the third compensation circuit compensating for the voltage rise caused by the parasitic resistance of the fourth node, wherein the first reference voltage level is higher than the second reference voltage level, and the second reference voltage level is higher than the second reference voltage level. The reference voltage level is higher than the third reference voltage level, and the third reference voltage level is higher than the fourth reference voltage.

In this embodiment, each of some of the nodes of the resistors of the first resistor string is supplied with a plurality of reference voltages between the first reference voltage and the second reference voltage, and the nodes of the resistors of the second resistor string. Some of the plurality of reference voltages are supplied between the third reference voltage and the fourth reference voltage.

The first compensation circuit may include: a first PMOS transistor having a source connected to a driving voltage and a gate connected to a drain; And a first resistor connected to a drain of the first PMOS transistor and a first node connected to the first node, wherein the second compensation circuit includes: a source having a source connected to the second node and a gate connected to the drain; 2 PMOS transistor; And a second resistor connected to the drain of the second PMOS transistor and the third node, wherein the third compensation circuit comprises: an NMOS transistor having a source connected to ground and a gate connected to the drain; And a third resistor connected between the fourth node and the drain of the NMOS transistor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 shows a liquid crystal display device 10 having a data driving circuit according to the present invention. The liquid crystal display device 10 includes a liquid crystal panel 100, a data driving circuit 200, a gate driving circuit 300, a timing control circuit 400, and a common voltage generating circuit 500.

The liquid crystal panel 100 is a thin film transistor TFT formed at an intersection of n gate lines G1 to Gn and m data lines D1 to Dm, and a liquid crystal capacitor arranged in a matrix form and connected to the thin film transistor. (Clc).

The thin film transistor TFT supplies data from the data lines D1 to Dm to the liquid crystal cell in response to the gate signal from the gate lines G1 to Gn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, and thus may be equivalently represented by a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the front gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The data driving circuit 200 converts the data R, G, and B supplied from the timing control circuit 400 into a video signal, which is an analog signal, so that one horizontal period in which the gate signal is supplied to the gate lines G1 to Gn. Each horizontal video signal is supplied to the data lines D1 to Dm.

The data driving circuit 200 selects a gamma voltage having a predetermined DC level according to the luminance values of the data R, G, and B, and supplies the selected gamma voltage to the data lines D1 to Dm.

The gate driving circuit 300 sequentially supplies the gate signals to the gate lines G1 to Gn according to the control signal from the timing control circuit 400.

The timing control circuit 400 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE and data from an external system. The timing control circuit 400 that receives the data clock DCLK, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable DE includes the data driving circuit 200 and the gate driving circuit 300. Control signals such as timing signals and polarity inversion signals for controlling timing are generated.

The common voltage generation circuit 500 generates a common voltage Vcom and supplies the generated common voltage Vcom to a common electrode which is one side electrode of the liquid crystal capacitor Clc. The common voltage generation circuit 500 includes a variable resistor for dividing the voltage of the common voltage source supplied from the outside.

The liquid crystal display device 10 is generally driven in an inversion manner. Therefore, the video signal supplied to the data lines D1 to Dm is divided into a positive video signal and a sub video signal. That is, when the gate signal is sequentially supplied to the gate lines G1 to Gn, the positive or negative video signal is commonly supplied to the data lines D1 to Dm.

As such, the video signals supplied to the data lines D1 to Dm are charged in the liquid crystal cell until the next video signals are supplied. In this case, a predetermined image is displayed on the liquid crystal panel 100 corresponding to the video signals charged in the liquid crystal cell. At this time, the image actually displayed on the liquid crystal panel 100 is displayed according to the difference between the charged video signal and the common voltage Vcom. Therefore, the quality of the image displayed on the liquid crystal panel 100 is determined according to the voltage value of the common voltage Vcom.

2 shows a data driving circuit 200 according to the present invention.

Referring to FIG. 2, the data driving circuit 200 includes a register 210, a level shifter 220, a decoder 240, a gray voltage generator circuit 240, and an amplifier 250.

The register 210 stores digital image data provided from the timing control circuit 400.

The level shifter 220 converts the voltage level of the digital data provided to the register 210. Since the register 210 operates at a low voltage (0.6 to 3.3 V) and the decoder 240 and the amplifier 250 operate at a high voltage (3.8 to 18 V), the level shifter 220 converts a voltage level of digital data. It passes to the decoder 240.

The gray voltage generator 230 generates gray voltages that make the input voltage nonlinear to linearly express the brightness of light.

The decoder 240 converts the digital data passed through the level shifter 220 into analog data. In general, the decoder 240 is configured as a digital-to-analog converter (DAC). The decoder 240 outputs one of the plurality of gray voltages as an analog signal in response to the digital passing through the level shifter 220.

The amplifier 250 buffers the analog signal of the decoder 240 to provide the source line of the liquid crystal panel.

3 is an embodiment of a gray voltage generator 230 of the data driving circuit 200 according to the present invention. Referring to FIG. 3, the gray voltage generator circuit 230 includes gamma resistors 231 and 232, reference voltages 233 and 234, parasitic resistors 235 and 236, and compensation circuits 237, 238 and 239.

The first gamma resistors R1 to R10: 231 are connected in series between the node N1 and the node N2. The first gamma resistors 231 distribute the reference voltages 233 to generate grayscale voltages VH1 to VH63 of high voltage. The first reference voltages VG1 to VG6: 233 are supplied between the first gamma resistors 231 connected in series. The reason for supplying the plurality of reference voltages 233 is to stabilize the output gray voltage. The first parasitic resistors r1 ˜ r6: 235 are parasitic resistors of a wiring supplying the respective first reference voltages 233.

The second gamma resistors R11 to R20: 232 are connected in series between the node N3 and the node N4. The second gamma resistors 232 distribute the reference voltages 234 to generate gray voltages VL1 to VL63 of low voltage. The second reference voltages VG7 to VG12: 234 are supplied between the second gamma resistors 232 connected in series. The reason for supplying the plurality of reference voltages 234 is to stabilize the output gray voltage. The second parasitic resistors r7 to r12: 236 are parasitic resistors of a wiring through which the second reference voltages 234 supply the respective second reference voltages 234.

The first compensation circuit 233 is connected between the driving voltage VDD and the node N1. The first compensation circuit 233 includes a PMOS transistor PM1 and a resistor RP. The PMOS transistor PM1 has a gate connected to a source and a drain connected to the driving voltage VDD. The resistor RP is connected between the drain of the PMOS transistor PM1 and the node N1.

The second compensation circuit 238 is connected between the node N2 and the node N3. The second compensation circuit 238 includes a PMOS transistor PM2 and a resistor RM. The PMOS transistor PM2 has a source connected to the node N2 and a gate connected to the drain. The resistor RM is connected between the drain of the PMOS transistor PM2 and the node N3.

The third compensation circuit 239 is connected between the node N4 and the ground GND. The third compensation circuit 239 includes an NMOS transistor NM and a resistor RN. The resistor RN is connected to the node N4 and the drain of the NMOS transistor NM. NMOS transistor (NM) has a gate connected to the drain and a source connected to the ground (GND).

The gray voltage generator circuit 230 of the present invention minimizes the voltage drop due to the parasitic resistance of the gamma resistor. The following describes some of the gradation voltage output processes.

The output of the gray voltage VH0 at the node N1 is as follows. The reference voltage VG1 is supplied to the node N1 through a wiring. At this time, the current I1 flows through the wiring. Therefore, the voltage drop Vr1 according to the parasitic resistance r1 of the wiring is as follows.

Current Ia flows through the first compensation circuit 237 of the present invention. Accordingly, the first compensation circuit 237 compensates the following voltage Vc1 at the node N1.

Here, the voltage VDS1 is a voltage applied between the drain and the source in the turn-on state of the PMOS transistor PM1.

 Therefore, the gray voltage VH0 at the node N1 satisfies the following equation.

 Therefore, if the resistance RP of the first compensation circuit 237 is appropriately adjusted, the gray scale voltage VH0 can be made equal to the reference voltage VG1.

The output of the gray voltage VH63 at the node N2 is as follows. The reference voltage VG6 is supplied to the node N2 through a wiring. At this time, the current I2 flows through the wiring. Therefore, the voltage rise Vr6 due to the parasitic resistance r6 of the wiring is as follows.

Current Ib flows through the second compensation circuit 238 of the present invention. Accordingly, the second compensation circuit 238 compensates the following voltage Vc2 at the node N2.

Here, the voltage VDS2 is a voltage applied between the drain and the source in the turn-on state of the PMOS transistor PM2.

 Therefore, the gray voltage VH63 at the node N2 satisfies the following equation.

 Therefore, if the resistance RM of the second compensation circuit 238 is appropriately adjusted, the gray voltage VH63 may be made equal to the reference voltage VG6.

The output of the gray voltage VL0 at the node N3 is as follows. The reference voltage VG7 is supplied to the node N3 through a wiring. At this time, a current I7 flows through the wiring. Therefore, the voltage drop Vr7 due to the parasitic resistance r7 of the wiring is as follows.

Current Ib flows through the second compensation circuit 238 of the present invention. Therefore, the second compensation circuit 238 compensates the following voltage Vc3 at the node N2.

Here, the voltage VDS2 is a voltage applied between the drain and the source in the turn-on state of the PMOS transistor PM2.

 Therefore, the gray voltage VL0 at the node N3 satisfies the following equation.

 Therefore, when the resistance RM of the second compensation circuit 238 is properly adjusted, the gray voltage VL0 may be made equal to the reference voltage VG7.

The output of the gray voltage VL63 at the node N4 is as follows. The reference voltage VG12 is supplied to the node N4 via a wiring. At this time, a current I12 flows through the wiring. Therefore, the voltage rise Vr12 due to the parasitic resistance r12 of the wiring is as follows.

The current Ic flows through the third compensation circuit 239 of the present invention. Accordingly, the third compensation circuit 239 compensates the following voltage Vc4 at the node N4.

Here, the voltage VDS is a voltage applied between the drain and the source in the turn-on state of the NMOS transistor NM.

 Therefore, the gray voltage VL63 at the node N4 satisfies the following equation.

 Therefore, if the resistance RN of the third compensation circuit 239 is appropriately adjusted, the gray voltage VL63 may be made equal to the reference voltage VG12.

The compensation circuits 237, 238, and 239 apply voltages for compensating voltage drops by parasitic resistances at the nodes N1, N2, N3, and N4. Therefore, the gray voltage generator 230 according to the present invention includes compensation circuits 237, 238, and 239, thereby reducing the influence of voltage drop due to parasitic resistance.

4 shows a simulation result for the output of the gray voltage when the gray voltage generator circuit 230 according to the present invention is used. Here, the parasitic resistance of each wiring is assumed to be 30 ohms. Referring to FIG. 4, when a conventional gray voltage generator circuit is used, there is a significant difference between the ideal gray voltage of the gray voltage and the actual gray voltage Vreal. However, when the gray voltage generator circuit 230 of the present invention is used, there is almost no difference between the ideal gray voltage and the actual gray voltage Vreal.

The gray voltage generator circuit 230 of the data driving circuit 200 according to the present invention can reduce the shift due to the voltage drop and the voltage rise of the gray voltage due to parasitic resistance.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the gray scale voltage generation circuit of the data driving circuit according to the present invention includes a compensation circuit, thereby improving a shift problem due to the voltage drop and the voltage rise of the gray scale voltage due to parasitic resistance.

Claims (8)

In the data driving circuit of the liquid crystal display device: A resistor string configured to receive a first reference voltage through a first node and a second reference voltage through a second node to generate a plurality of gray voltages; And And a compensation circuit connected to each of the first node and the second node, the compensation circuit compensating for voltage drop and voltage rise caused by parasitic resistance of the first node and the second node. The method of claim 1, And a plurality of reference voltages between the first reference voltage and the second reference voltage are respectively supplied to some of the nodes between the resistors in the resistor string. The method of claim 1, The compensation circuit A first compensator coupled to the first node to compensate for a voltage drop caused by a parasitic resistance of the first node; And And a second compensator connected to the second node, the second compensator compensating for the voltage rise caused by the parasitic resistance of the second node. The method of claim 3, wherein The first compensator, A PMOS transistor having a source connected to a driving voltage and a gate connected to a drain; And And a first resistor connected between the first node and a drain of the PMOS transistor. The method of claim 3, wherein The second compensator, An NMOS transistor having a source connected to ground and a gate connected to a drain; And And a second resistor connected between the second node and the drain of the NMOS transistor. In the data driving circuit of the liquid crystal display device: A first resistor string supplied with a first reference voltage and a second reference voltage through a first node, and connected between the first node and the second node to generate a plurality of gray voltages; A second resistor string configured to receive a third reference voltage from a third node, receive a fourth reference voltage from a fourth node, and be connected between the third node and the fourth node to generate a plurality of gray voltages; A first compensation circuit connected to the first node and compensating for a voltage drop caused by a parasitic resistance of the first node; A second compensation circuit connected between the second node and the third node, and configured to compensate for a voltage increase and a voltage drop caused by respective parasitic resistances at the second node and the third node; And A third compensation circuit connected to the fourth node and compensating for a voltage increase caused by a parasitic resistance of the fourth node, The first reference voltage level is higher than the second reference voltage level, the second reference voltage level is higher than the third reference voltage level, and the third reference voltage level is higher than the fourth reference voltage. . The method of claim 6, A plurality of reference voltages between the first reference voltage and the second reference voltage are respectively supplied to some of the nodes of the resistors of the first resistor string. And a gradation voltage generating a gradation voltage supplied to a plurality of reference voltages between the third reference voltage and the fourth reference voltage at some of the nodes of the resistors of the second resistance column. The method of claim 6, The first compensation circuit, A first PMOS transistor having a source connected to a driving voltage and a gate connected to a drain; And A first resistor connected to a drain of the first PMOS transistor and a first node connected to the first node, The second compensation circuit, A second PMOS transistor having a source connected to the second node and a gate connected to the drain; And A second resistor connected to the drain of the second PMOS transistor and the third node, The third compensation circuit, An NMOS transistor having a source connected to ground and a gate connected to the drain; And And a third resistor connected between the fourth node and the drain of the NMOS transistor.

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